CN112181753B - Debugging method, system and readable storage medium - Google Patents
Debugging method, system and readable storage medium Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention provides a debugging method, a debugging system and a readable storage medium. The method comprises the following steps: when the CPLD of the debugging small plate receives a debugging instruction sent by the upper computer, determining an object to be debugged corresponding to the debugging instruction; the CPLD of the debugging platelet and the CPLD of the single disc respectively set the communication protocols of the serial debugging interfaces of the debugging platelet and the single disc as target communication protocols corresponding to the object to be debugged; the CPLD of the debugging platelet sends a debugging instruction to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging platelet and the single disc; the CPLD of the single disk executes the received debugging instructions. In the embodiment, the protocol types of the debugging instructions from the upper computer are switched by debugging the small board and the CPLD of the single disk, and the single disk is debugged based on the serial debugging interfaces at the two ends. The serial debugging interface only needs fewer signal pins, namely, the debugging connector with fewer pins is selected to meet the debugging requirement, and the number of the needed debugging connectors is greatly reduced.
Description
Technical Field
The present invention relates to the field of embedded hardware technologies, and in particular, to a debugging method, a debugging system, and a readable storage medium.
Background
With the increase of complexity of electronic devices and products, the number and types of IC (Integrated Circuit) devices used on a single disk are increasing, and communication protocols of debug interfaces used by different IC devices are different, and the communication protocols of common debug interfaces include JTAG (Joint test action Group), UART (universal asynchronous Receiver/Transmitter), I2C (Integrated Circuit two-wire Serial bus developed by Philips), SPI (Serial Peripheral Interface), SMBUS (System Management bus), MDIO (Management Data Input/output), and the like.
In order to meet the debugging requirements of all IC devices on a single disk, a debugging connector needs to be arranged on the single disk for each IC device, so that the number of the debugging connectors used by the single disk is large, meanwhile, the area of a Printed Circuit Board (PCB) occupied by the debugging connector is large, and the high-density and small-size design of the PCB is not facilitated; the signal pins required by the debugging connectors of different communication protocols are different, and different debugging connectors are required to be selected, so that the normalization of debugging connector devices is not facilitated; the thickness of a product is an important factor for measuring the competitiveness of the product, in order to reduce the overall thickness of the product, the distance between a single-disk radiator and the single-disk radiator needs to be compressed as much as possible when the single-disk radiator is designed, a debugging connector is generally the highest device on the single disk, the distance between the single-disk radiator and the single-disk radiator is reduced by generally adopting a method that a radiator is grooved to avoid the single-disk debugging connector when the single-disk radiator is designed, and the design difficulty and the material cost of the single-disk radiator are greatly increased due to excessive debugging connectors; every debugging connector of single-disk all needs several cables and debugging platelet to link to each other, and too much debugging connector can cause the debugging cable special complicacy of connecting debugging connector and debugging platelet, is unfavorable for the construction of single-disk engineering problem debugging environment.
Disclosure of Invention
The invention mainly aims to provide a debugging method, a debugging system and a readable storage medium, and aims to solve the technical problem that a plurality of debugging connectors are required to be arranged in order to meet the debugging requirements of all IC devices of a single disk in the prior art.
In a first aspect, the present invention provides a debugging method, including:
when the CPLD of the debugging small plate receives a debugging instruction sent by the upper computer, the CPLD of the debugging small plate determines an object to be debugged corresponding to the debugging instruction;
the CPLD of the debugging small plate and the CPLD of the single disc respectively set the communication protocols of the serial debugging interfaces of the debugging small plate and the single disc as target communication protocols corresponding to the object to be debugged;
the CPLD of the debugging platelet sends a debugging instruction to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging platelet and the single disc;
the CPLD of the single disk executes the received debug instruction.
Optionally, when the object to be debugged is a CPLD of a single disc, the step of setting the communication protocols of the serial debug interfaces of the debug platelet and the single disc as the target communication protocols corresponding to the object to be debugged, respectively, by the CPLD of the debug platelet and the CPLD of the single disc includes:
the CPLD of the debugging platelet sets a communication protocol of a serial debugging interface of the debugging platelet as an SPI protocol;
the CPLD of the debugging platelet sends a first write command corresponding to the CPLD of the single disc of the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging platelet and the single disc;
the CPLD of the single disk writes a first preset value corresponding to the first write command into a debugging interface register of the CPLD of the single disk;
the CPLD of the single disk sets a communication protocol of a serial debugging interface of the single disk as a JTAG protocol corresponding to the first preset value;
and the CPLD of the debugging platelet sets the communication protocol of the serial debugging interface of the debugging platelet as a JTAG protocol.
Optionally, the step of sending the debugging instruction to the CPLD of the single disk based on the target communication protocol and the serial debugging interface of the debugging platelet and the single disk includes:
and the CPLD of the debugging platelet converts the communication protocol type of the debugging instruction into the JTAG protocol type, and sends the JTAG protocol type to the CPLD of the single disk through serial debugging interfaces of the debugging platelet and the single disk.
Optionally, when the debug instruction is a reset instruction, the step of executing, by the CPLD of the single disk, the received debug instruction includes:
the CPLD of the single disk switches the communication protocol of the serial debugging interface of the single disk from the JTAG protocol to the SPI protocol.
Optionally, when the object to be debugged is an IC device other than the CPLD on the single disk, the step of setting the communication protocol of the serial debug interface of the debug platelet and the communication protocol of the serial debug interface of the single disk as the target communication protocol corresponding to the object to be debugged respectively includes:
the CPLD of the debugging platelet sets the communication protocol of the serial debugging interface of the debugging platelet as an SPI protocol;
the CPLD of the debugging platelet sends second write commands corresponding to other IC devices of the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging platelet and the single disc;
the CPLD of the single disk writes a second preset value corresponding to the second write command into a debugging interface register of the CPLD of the single disk;
and when the CPLD of the single disk detects that the value in the debugging interface register of the CPLD of the single disk is not the first preset value, the CPLD of the single disk keeps the communication protocol of the serial debugging interface of the single disk to be the SPI protocol.
Optionally, the step of sending the debugging instruction to the CPLD of the single disk based on the target communication protocol and the serial debugging interface of the debugging platelet and the single disk includes:
the CPLD of the debugging platelet converts the communication protocol type of the debugging instruction into the SPI protocol type, and sends the SPI protocol type to the CPLD of the single disc through the serial debugging interfaces of the debugging platelet and the single disc.
Optionally, the step of executing the received debug instruction by the CPLD of the single disk includes:
and the CPLD of the single disk converts the debugging instruction of the SPI protocol type into a debugging instruction of the protocol type corresponding to the second preset value, and sends the debugging instruction to the other IC devices.
Optionally, when the CPLD of the debug platelet receives the debug instruction sent by the upper computer, the step of determining the object to be debugged corresponding to the debug instruction by the CPLD of the debug platelet includes:
when the CPLD of the debugging small plate receives a debugging instruction sent by the upper computer, detecting whether the value in a debugging interface register of the CPLD of the single disc is a third preset value;
and if the preset value is the third preset value, the CPLD of the debugging small plate determines an object to be debugged corresponding to the debugging instruction.
In a second aspect, the present invention further provides a debugging system, where the debugging system includes a debugging platelet and a single disk, where the debugging platelet and the single disk are respectively provided with a CPLD, and the debugging system includes:
the CPLD of the debugging platelet is used for determining an object to be debugged corresponding to the debugging instruction when receiving the debugging instruction sent by the upper computer; setting a communication protocol of a serial debugging interface of a debugging platelet as a target communication protocol corresponding to the object to be debugged;
the CPLD of the single disk is used for setting the communication protocol of the serial debugging interface of the single disk as a target communication protocol corresponding to the object to be debugged;
the CPLD of the debugging platelet is also used for sending the received debugging instruction sent by the upper computer to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging platelet and the single disc;
the single-disk CPLD is also used for executing the received debugging instructions.
In a third aspect, the present invention further provides a readable storage medium, in which a debugging program is stored, where the debugging program, when executed by a processor, implements the steps of the debugging method as described above.
In the invention, when the CPLD of the debugging small plate receives a debugging instruction sent by an upper computer, the CPLD of the debugging small plate determines an object to be debugged corresponding to the debugging instruction; the CPLD of the debugging small plate and the CPLD of the single disc respectively set the communication protocols of the serial debugging interfaces of the debugging small plate and the single disc as target communication protocols corresponding to the object to be debugged; the CPLD of the debugging small plate sends a debugging instruction to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging small plate and the single disc; the CPLD of the single disk executes the received debug instruction. The invention switches the protocol types of the debugging instructions from the upper computer through the debugging small plate and the CPLD of the single disk, and can realize the debugging of the single disk based on the serial debugging interfaces at the two ends. The serial debugging interface only needs fewer signal pins, namely the debugging connector with fewer pins is selected for use, so that the debugging requirement can be met, the number of the needed debugging connectors is greatly reduced, the PCB space occupied by the debugging connector is reduced, the materials of the debugging connector are normalized, the design difficulty and the cost of a single-disc radiator are reduced, and the construction of a single-disc engineering problem debugging environment is simplified.
Drawings
FIG. 1 is a flowchart illustrating a debugging method according to an embodiment of the present invention;
FIG. 2 is a block diagram of a debug system according to an embodiment.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
In a first aspect, an embodiment of the present invention provides a debugging method.
Referring to fig. 1, fig. 1 is a flowchart illustrating a debugging method according to an embodiment of the present invention. In one embodiment, a debugging method includes:
step S10, when the CPLD of the debugging small plate receives a debugging instruction sent by the upper computer, the CPLD of the debugging small plate determines an object to be debugged corresponding to the debugging instruction;
in this embodiment, the upper computer sends a debug instruction to the CPLD of the debug platelet to start debugging. And when the CPLD of the debugging small plate receives a debugging instruction sent by the upper computer, determining an object to be debugged according to the debugging instruction. The object to be debugged refers to the CPLD of the single disk or other IC devices except the CPLD on the single disk. Specifically, the debug instruction includes a field for identifying the identity of the object to be debugged, and according to the field, the CPLD of the debug platelet can determine whether the object to be debugged corresponding to the debug instruction is a CPLD of a single disc or other IC devices on the single disc except the CPLD.
Step S20, debugging the CPLD of the small board and the CPLD of the single disc, and respectively setting the communication protocols of the serial debugging interfaces of the small board and the single disc as target communication protocols corresponding to the object to be debugged;
in this embodiment, after the object to be debugged is determined, the CPLD of the small board and the CPLD of the single disc are debugged, that is, the communication protocols of the serial debug interfaces of the small board and the single disc may be set as the target communication protocols corresponding to the object to be debugged, respectively.
Further, in an embodiment, when the object to be debugged is a CPLD with a single disk, step S20 includes:
the CPLD of the debugging platelet sets a communication protocol of a serial debugging interface of the debugging platelet as an SPI protocol; the CPLD of the debugging platelet sends a first write command corresponding to the CPLD of the single disc of the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging platelet and the single disc; the CPLD of the single disk writes a first preset value corresponding to the first write command into a debugging interface register of the CPLD of the single disk; the CPLD of the single disk sets a communication protocol of a serial debugging interface of the single disk as a JTAG protocol corresponding to the first preset value; and the CPLD of the debugging small plate sets the communication protocol of the serial debugging interface of the debugging small plate as a JTAG protocol.
In this embodiment, when the object to be debugged is a CPLD of a single disk, it is necessary to implement communication between the CPLD of the debug platelet and the CPLD of the single disk through the JTAG protocol. Since the default of the communication protocol of the serial debugging interface of the single disk is set as the SPI protocol, the CPLD of the debugging platelet sets the communication protocol of the serial debugging interface of the debugging platelet as the SPI protocol. And then, sending a first write command corresponding to the single-disk CPLD of the SPI protocol type to the single-disk CPLD. And after receiving the first write command, the CPLD of the single disk acquires a first preset value from the first write command, and writes the first preset value into a debugging interface register of the CPLD of the single disk. And then, the CPLD of the single disk sets the communication protocol of the serial debugging interface of the single disk to be a JTAG protocol corresponding to the first preset value, and the CPLD of the debugging small plate also sets the communication protocol of the serial debugging interface of the debugging small plate to be the JTAG protocol so as to realize the communication between the CPLD of the debugging small plate and the CPLD of the single disk based on the JTAG protocol. The first preset value may be 0xf0, or other values may be used as the first preset value, which is specifically set according to actual needs.
Further, in another embodiment, when the object to be debugged is another IC device on the single disk except the CPLD, step S20 includes:
the CPLD of the debugging platelet sets the communication protocol of the serial debugging interface of the debugging platelet as an SPI protocol; the CPLD of the debugging small plate sends a second write command corresponding to other IC devices of the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging small plate and the single disc; the CPLD of the single disk writes a second preset value corresponding to the second write command into a debugging interface register of the CPLD of the single disk; and when the CPLD of the single disk detects that the value in the debugging interface register of the CPLD of the single disk is not the first preset value, the CPLD of the single disk keeps the communication protocol of the serial debugging interface of the single disk to be the SPI protocol.
In this embodiment, when the object to be debugged is another IC device on the single disc except the CPLD, the communication between the CPLD of the debug platelet and the CPLD of the single disc needs to be implemented by the SPI protocol. Because the default of the communication protocol of the serial debugging interface of the single disk is set as the SPI protocol, the CPLD of the debugging platelet sets the communication protocol of the serial debugging interface of the debugging platelet as the SPI protocol, and sends second write commands corresponding to other IC devices of the SPI protocol type to the CPLD of the single disk through the serial debugging interfaces of the debugging platelet and the single disk. And after receiving the second write command, the CPLD of the single disk acquires a second preset value from the second write command, and writes the second preset value into a debugging interface register of the CPLD of the single disk. Wherein, the other IC devices are any one of a CPU, a clock chip, a power supply chip, a port physical layer chip and a field programmable gate array chip. Each type of IC device has a corresponding second write command. For example, the second write command corresponding to the CPU is: write 0x00 or write 0x01; the second write command corresponding to the clock chip is: after writing 0x02 or 0x03.. The value in the debugging interface register of the CPLD of the single disk is not the first preset value, the communication protocol of the serial debugging interface of the single disk does not need to be modified to the JTAG protocol, that is, the CPLD of the single disk keeps the communication protocol of the serial debugging interface of the single disk to be the SPI protocol, so that the communication between the CPLD of the debugging platelet and the CPLD of the single disk is realized based on the SPI protocol.
Step S30, the CPLD of the debugging platelet sends a debugging instruction to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging platelet and the single disc;
in this embodiment, both the communication protocols of the serial debug interfaces of the debug platelet and the single disk are set as target communication protocols. After the CPLD of the debug platelet receives the debug instruction sent by the upper computer, the communication protocol type of the debug instruction needs to be converted into the target communication protocol type, and then the target communication protocol type is sent to the CPLD of the single disk through the serial debug interfaces of the debug platelet and the single disk.
Further, in an embodiment, the step S30 includes:
and the CPLD of the debugging platelet converts the received communication protocol type of the debugging instruction sent by the upper computer into the JTAG protocol type, and sends the communication protocol type to the CPLD of the single disk through the serial debugging interfaces of the debugging platelet and the single disk.
In this embodiment, when the object to be debugged is a CPLD of a single disk, both the communication protocols of the debug platelet and the serial debug interface of the single disk have been set to the JTAG protocol. Therefore, the CPLD of the debugging small board converts the communication protocol type of the received debugging instruction sent by the upper computer into the JTAG protocol type, and sends the debugging instruction to the CPLD of the single disk through the serial debugging interfaces of the debugging small board and the single disk. The communication protocol type of the debugging instruction sent by the upper computer is generally a USB protocol type.
Further, in another embodiment, the step S30 includes:
and the CPLD of the debugging platelet converts the received communication protocol type of the debugging instruction sent by the upper computer into the SPI protocol type, and sends the SPI protocol type to the CPLD of the single disc through the serial debugging interfaces of the debugging platelet and the single disc.
In this embodiment, when the object to be debugged is an IC device other than the CPLD on the single disk, the communication protocols of the serial debug interfaces of the debug platelet and the single disk are both set to the SPI protocol. Therefore, the CPLD of the debugging platelet converts the communication protocol type of the received debugging instruction sent by the upper computer into the SPI protocol type, and sends the communication protocol type to the CPLD of the single disk through the serial debugging interfaces of the debugging platelet and the single disk. The communication protocol type of the debugging instruction sent by the upper computer is generally a USB protocol type.
And step S40, the CPLD of the single disk executes the received debugging instruction.
In this embodiment, when the object to be debugged is a CPLD of a single disk, the CPLD of the single disk directly executes after receiving the debugging instruction. When the object to be debugged is other IC devices on the single disc except the CPLD, the CPLD of the single disc needs to further forward the debug instruction to the corresponding IC device after receiving the debug instruction. It is easy to understand that, after each debugging instruction is executed, the CPLD of the single disk returns a completion message to the CPLD of the debugging platelet, and the CPLD of the debugging platelet feeds back the completion message to the upper computer, so that the upper computer continues to send a new debugging instruction or finishes debugging.
Further, in an embodiment, when the debugging instruction is a reset instruction, the step S40 includes:
and the CPLD of the single disk switches the communication protocol of the serial debugging interface of the single disk from the JTAG protocol to the SPI protocol.
In this embodiment, when the object to be debugged is a CPLD of a single disk, the CPLD of the single disk directly executes after receiving the debugging instruction. When the debugging instruction is a reset instruction, it indicates that the debugging is finished, and the CPLD of the single disk restores the communication protocol of the serial debugging interface of the single disk to the default protocol, that is, the CPLD of the single disk switches the communication protocol of the serial debugging interface of the single disk from the JTAG protocol to the SPI protocol.
Further, in another embodiment, the step S40 includes:
and the CPLD of the single disk converts the debugging instruction of the SPI protocol type into a debugging instruction of the protocol type corresponding to the second preset value, and sends the debugging instruction to the other IC devices.
In this embodiment, when the object to be debugged is an IC device other than the CPLD on the single disk. And the single-disk CPLD converts the debugging instruction of the SPI protocol type into a debugging instruction of the protocol type corresponding to the second preset value and sends the debugging instruction to other IC devices. For example, if the other IC device is a CPU and the second preset value is 0x00, the CPLD of the single disk converts the debugging instruction of the SPI protocol type into a debugging instruction of the JTAG protocol type corresponding to 0x00, and sends the debugging instruction to the CPU, so as to complete the debugging of the CPU. Similarly, when the other IC devices are CPUs and the second preset value is 0x01, the CPLD of the single disk converts the debugging instruction of the SPI protocol type into a debugging instruction of the UART protocol type corresponding to 0x01, and sends the debugging instruction to the CPU to complete the debugging of the CPU. Aiming at the problem, the debugging of IC devices such as a clock chip, a power supply chip, a port physical layer chip, a field programmable gate array chip and the like can be realized in the same way.
In the embodiment, when the CPLD of the debugging platelet receives a debugging instruction sent by the upper computer, the CPLD of the debugging platelet determines an object to be debugged corresponding to the debugging instruction; the CPLD of the debugging small plate and the CPLD of the single disc respectively set the communication protocols of the serial debugging interfaces of the debugging small plate and the single disc as target communication protocols corresponding to the object to be debugged; the CPLD of the debugging platelet sends a debugging instruction to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging platelet and the single disc; the CPLD of the single disk executes the received debug instruction. In the embodiment, the protocol types of the debugging instructions from the upper computer are switched by debugging the small board and the CPLD of the single disk, and the single disk can be debugged based on the serial debugging interfaces at the two ends. The serial debugging interface only needs fewer signal pins, namely the debugging connector with fewer pins is selected for use, so that the debugging requirement can be met, the number of the needed debugging connectors is greatly reduced, the PCB space occupied by the debugging connector is reduced, the materials of the debugging connector are normalized, the design difficulty and the cost of a single-disc radiator are reduced, and the construction of a single-disc engineering problem debugging environment is simplified.
Further, in an embodiment, the step S10 includes:
when the CPLD of the debugging small plate receives a debugging instruction sent by the upper computer, detecting whether the value in a debugging interface register of the CPLD of the single disc is a third preset value; and if the preset value is the third preset value, the CPLD of the debugging platelet determines an object to be debugged corresponding to the debugging instruction.
In this embodiment, when the CPLD of the debug platelet receives the debug instruction sent by the upper computer, the CPLD of the debug platelet switches the protocol of the serial debug interface of the debug platelet to the SPI protocol, and sends a read command to the CPLD of the single disk through the SPI protocol, so as to read the value in the status register of the CPLD of the single disk. And detecting whether the value is a third preset value, if so, indicating that the single disk supports the serial debugging interface, and then carrying out the subsequent steps.
Further, in an embodiment, the debugging method is applied to a debugging system, and fig. 2 is a schematic diagram of an architecture of the debugging system in an embodiment. As shown in fig. 2, the debugging platelet includes an upper computer chip, a debugging platelet CPLD, and a serial debugging interface; the single disk comprises a serial debugging interface, an analog switch, a single disk CPLD, a CPU, a clock chip, a power chip, a PHY and an FPGA. The upper computer and the debugging small plate are connected through a USB line, and the two ends of the debugging cable are respectively connected with the serial debugging interfaces of the single disk and the debugging small plate. The debugging method applied to the debugging system comprises the following steps:
step S101: and the upper computer sends a debugging instruction, starts debugging and then goes to the step S102.
Step S102: the debugging platelet CPLD switches the serial debugging interface of the debugging platelet into an SPI protocol, sends a command to the single-disk CPLD through the SPI protocol and reads the state register of the single-disk CPLD. If the default communication protocol of the single-disk serial debugging interface is SPI, if the value of reading the single-disk CPLD state register is 0xa5, the single disk supports the serial debugging interface, and the step S103 is carried out; if the value of the read single-disk CPLD state register is not 0xa5, the single disk does not support the serial debugging interface, and the debugging platelet returns a debugging error of the upper computer and waits for a next debugging instruction.
Step S103: and the debugging small-plate CPLD judges whether the debugging instruction is used for debugging the single-disk CPLD or other single-disk IC devices according to the debugging instruction of the upper computer. If the debugging is the single-disk CPLD, the step S104 is carried out. If the other IC device is debugged for a single disk, the process proceeds to step S111.
Step S104: and the debugging small CPLD sends a command to the single-disk CPLD through the SPI protocol, writes a debugging interface register of the single-disk CPLD, writes data of 0xf0, and shifts to the step S105.
Step S105: the single-disc CPLD modifies the communication protocol of the single-disc serial debug interface by modifying the state of the single-disc analog switch control signal according to the data of the debug interface register (if 0xf0, the control analog switch is switched to the JTAG protocol, and if not 0xf0, the control analog switch is switched to the SPI protocol), because in step S104, the debug small-disc CPLD writes the debug interface register of the single-disc CPLD to 0xf0, and here, the single-disc CPLD controls the analog switch to be switched to the JTAG protocol, and then the process goes to step S106.
Step S106: the debugging small plate CPLD also switches the communication of the serial debugging interface of the debugging small plate to the JTAG protocol, and the process goes to step S107.
Step S107: the upper computer sends a command to debug the single-disk CPLD, the debugging platelet modifies the upper computer command into a JTAG protocol to communicate with the single-disk debugging interface, the debugging of the single-disk CPLD is completed, and the step S108 is switched.
Step S108: the upper computer sends a command to reset the single-disk CPLD, the debugging platelet modifies the command of the upper computer into a JTAG protocol to communicate with the single disk, the resetting of the single-disk CPLD is completed, and the step S109 is carried out.
Step S109: after the single-disk CPLD is reset, the single-disk CPLD switches the control signal of the single-disk analog switch to the default state, and at this time, the communication protocol of the serial debug interface of the single-disk CPLD is SPI, and the step S110 is performed.
Step S110: the debugging platelet CPLD feeds back a debugging instruction completion signal to the upper computer, and the step S115 is carried out.
Step S111: the debugging platelet CPLD confirms the debugging protocol type used by the single-disk device needing to be debugged according to the debugging instruction of the upper computer, sends a command to the single-disk CPLD through the SPI protocol, writes the debugging interface register of the single-disk CPLD according to the debugging protocol type of the single-disk device, and then the step S112 is carried out.
The corresponding relation between the single-disk CPLD debugging interface register value and the type of the debugging protocol of the single-disk debugging IC device is as follows:
0x00: CPU _ JTAG (JTAG interface of CPU)
0x01: CPU _ UART (UART interface of CPU)
0x02: CLK _ I2C (I2C interface of clock chip)
0x03: CLK _ SPI (SPI interface of clock chip)
0x04: POWER _ I2C (I2C interface of POWER supply chip)
0x05: POWER _ SMBUS (SMBUS interface of POWER supply chip)
0x06: PHY _ MDIO (MDIO interface of port physical layer chip)
0x07: PHY _ I2C (I2C interface of port physical layer chip)
0x08: PHY _ SMBUS (SMBUS interface of port physical layer chip)
0x09: FPGA _ JTAG (JTAG interface of field programmable gate array chip)
Step S112: the debugging platelet CPLD switches the communication protocol of the serial debugging interface into the SPI protocol; the communication protocol of the single-disk serial debugging interface is defaulted to be the SPI protocol, and the step S113 is carried out without changing.
Step S113: the upper computer sends a command to debug other IC devices of the single-disk non-CPLD, the small debugging plate CPLD converts the instruction of the upper computer into an SPI protocol to communicate with the single-disk debugging interface, and the step S114 is carried out.
Step S114: and the single-disk CPLD converts the SPI protocol sent by the debugging platelet into a communication protocol required by the debugging of other single-disk IC devices according to the value of the debugging register of the single-disk CPLD, finishes the debugging of the other single-disk IC devices and then shifts to the step S110.
Step S115: and judging whether other debugging instructions need to be executed by the upper computer. If no other debugging instructions exist, the step S116 is carried out; if there are other debug instructions, the process proceeds to step S101.
Step S116: and finishing debugging.
In the communication flow of the serial debugging interface, the serial debugging interface can meet the debugging function requirements of all the IC devices of a single disk in the embodiment, the types of the debugging interfaces of the IC devices related to the single disk are not limited to the listed types, but only smooth expansion and upgrading are needed on the basis, the types of debugging interface registers of the CPLD of the single disk are increased, and the normalization design of the serial debugging interface is finally ensured.
In a second aspect, an embodiment of the present invention further provides a debugging system.
In one embodiment, the debugging system includes a debugging platelet and a single disk, and CPLDs are respectively disposed on the debugging platelet and the single disk, wherein:
the CPLD of the debugging platelet is used for determining an object to be debugged corresponding to the debugging instruction when receiving the debugging instruction sent by the upper computer; setting a communication protocol of a serial debugging interface of a debugging platelet as a target communication protocol corresponding to the object to be debugged;
the CPLD of the single disk is used for setting the communication protocol of the serial debugging interface of the single disk as a target communication protocol corresponding to the object to be debugged;
the CPLD of the debugging platelet is also used for sending the received debugging instruction sent by the upper computer to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging platelet and the single disc;
and the single-disk CPLD is also used for executing the received debugging instruction.
Further, in an embodiment, when the object to be debugged is a CPLD of a single disk:
the CPLD of the debugging platelet is used for setting a communication protocol of a serial debugging interface of the debugging platelet as an SPI protocol; sending a first write command corresponding to the CPLD of the single disc of the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging small plate and the single disc;
the single-disc CPLD is used for writing a first preset value corresponding to the first write command into a debugging interface register of the single-disc CPLD; setting a communication protocol of a serial debugging interface of the single disk as a JTAG protocol corresponding to the first preset value;
and the CPLD of the debugging platelet is used for setting the communication protocol of the serial debugging interface of the debugging platelet as a JTAG protocol.
Further, in one embodiment:
and the CPLD of the debugging platelet is used for converting the communication protocol type of the debugging instruction into the JTAG protocol type and sending the JTAG protocol type to the CPLD of the single disk through serial debugging interfaces of the debugging platelet and the single disk.
Further, in one embodiment, when the debug instruction is a reset instruction:
and the single-disk CPLD is used for switching the communication protocol of the serial debugging interface of the single disk from the JTAG protocol to the SPI protocol.
Further, in an embodiment, when the object to be debugged is an IC device other than the CPLD on the single disk:
the CPLD of the debugging platelet is used for setting a communication protocol of a serial debugging interface of the debugging platelet as an SPI protocol; sending second write commands corresponding to other IC devices of the SPI protocol type to the single-disk CPLD through serial debugging interfaces of the debugging small plate and the single disk;
the CPLD of the single disk is used for writing a second preset value corresponding to the second write command into a debugging interface register of the CPLD of the single disk; and if the value in the debugging interface register of the single-disk CPLD is not the first preset value, the single-disk CPLD keeps the communication protocol of the serial debugging interface of the single disk to be the SPI protocol.
Further, in one embodiment:
and the CPLD of the debugging platelet is used for converting the communication protocol type of the debugging instruction into the SPI protocol type and sending the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging platelet and the single disc.
Further, in one embodiment:
and the single-disk CPLD is used for converting the debugging instruction of the SPI protocol type into a debugging instruction of the protocol type corresponding to the second preset value and sending the debugging instruction to the other IC devices.
Further, in one embodiment:
the CPLD of the debugging small plate is used for detecting whether the value in the debugging interface register of the CPLD of the single disc is a third preset value or not when receiving a debugging instruction sent by the upper computer; and if the preset value is the third preset value, debugging the object to be debugged corresponding to the instruction.
The specific embodiment of the debugging system is basically the same as each embodiment of the debugging method, and is not described in detail here.
In a third aspect, an embodiment of the present invention further provides a readable storage medium.
The readable storage medium of the present invention stores a debugging program, wherein the debugging program implements the steps of the debugging method as described above when being executed by a processor.
The method for implementing the debugging program when executed may refer to various embodiments of the debugging method of the present invention, and will not be described herein again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or system comprising the element.
The above-mentioned serial numbers of the embodiments of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention or the portions contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) as described above and includes several instructions for causing a terminal device to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields are also included in the scope of the present invention.
Claims (9)
1. A debugging method, characterized in that the debugging method comprises:
when the CPLD of the debugging small plate receives a debugging instruction sent by the upper computer, the CPLD of the debugging small plate determines an object to be debugged corresponding to the debugging instruction;
the CPLD of the debugging platelet and the CPLD of the single disc respectively set the communication protocols of the serial debugging interfaces of the debugging platelet and the single disc as target communication protocols corresponding to the object to be debugged;
the CPLD of the debugging platelet sends a debugging instruction to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging platelet and the single disc;
the CPLD of the single disk executes the received debugging instruction;
when the object to be debugged is a CPLD of a single disc, the step of setting the communication protocols of the serial debug interfaces of the debug platelet and the single disc as the target communication protocols corresponding to the object to be debugged respectively by the CPLD of the debug platelet and the CPLD of the single disc includes:
the CPLD of the debugging platelet sets a communication protocol of a serial debugging interface of the debugging platelet as an SPI protocol;
the CPLD of the debugging platelet sends a first write command corresponding to the CPLD of the single disc of the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging platelet and the single disc;
writing a first preset value corresponding to the first write command into a debugging interface register of the CPLD of the single disk by the CPLD of the single disk;
the CPLD of the single disk sets a communication protocol of a serial debugging interface of the single disk as a JTAG protocol corresponding to the first preset value;
and the CPLD of the debugging small plate sets the communication protocol of the serial debugging interface of the debugging small plate as a JTAG protocol.
2. The debugging method of claim 1, wherein the step of sending the debugging instructions to the CPLD of the single disk based on the target communication protocol and serial debugging interfaces of the debugging platelet and the single disk comprises:
and the CPLD of the debugging small plate converts the communication protocol type of the debugging instruction into the JTAG protocol type and sends the communication protocol type of the debugging instruction to the CPLD of the single disk through the serial debugging interfaces of the debugging small plate and the single disk.
3. The debugging method according to claim 2, wherein when the debugging command is a reset command, the step of executing the received debugging command by the CPLD of the single disk comprises:
the CPLD of the single disk switches the communication protocol of the serial debugging interface of the single disk from the JTAG protocol to the SPI protocol.
4. The debugging method according to claim 1, wherein when the object to be debugged is an IC device other than a CPLD on a single disc, the step of setting the communication protocol of the serial debugging interfaces of the debugging platelet and the single disc to the target communication protocol corresponding to the object to be debugged, respectively, by the CPLD of the debugging platelet and the CPLD of the single disc, comprises:
the CPLD of the debugging platelet sets a communication protocol of a serial debugging interface of the debugging platelet as an SPI protocol;
the CPLD of the debugging platelet sends second write commands corresponding to other IC devices of the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging platelet and the single disc;
the CPLD of the single disk writes a second preset value corresponding to the second write command into a debugging interface register of the CPLD of the single disk;
and when the CPLD of the single disk detects that the value in the debugging interface register of the CPLD of the single disk is not the first preset value, the CPLD of the single disk keeps the communication protocol of the serial debugging interface of the single disk to be the SPI protocol.
5. The debugging method of claim 4, wherein the step of sending the debugging instruction to the CPLD of the single disk based on the target communication protocol and the serial debugging interfaces of the debugging platelet and the single disk comprises:
the CPLD of the debugging platelet converts the communication protocol type of the debugging instruction into the SPI protocol type, and sends the SPI protocol type to the CPLD of the single disc through the serial debugging interfaces of the debugging platelet and the single disc.
6. The debugging method according to claim 5, wherein the step of the single-disk CPLD executing the received debugging instructions comprises:
and the CPLD of the single disk converts the debugging instruction of the SPI protocol type into a debugging instruction of the protocol type corresponding to the second preset value, and sends the debugging instruction to the other IC devices.
7. The debugging method according to any one of claims 1 to 6, wherein the step of determining, by the CPLD of the debugging platelet, the object to be debugged corresponding to the debugging instruction when the CPLD of the debugging platelet receives the debugging instruction sent by the upper computer comprises:
when the CPLD of the debugging small plate receives a debugging instruction sent by the upper computer, detecting whether the value in a debugging interface register of the CPLD of the single disc is a third preset value;
and if the preset value is the third preset value, the CPLD of the debugging platelet determines an object to be debugged corresponding to the debugging instruction.
8. A debugging system is characterized by comprising a debugging platelet and a single disk, wherein the debugging platelet comprises an upper computer chip, a CPLD (complex programmable logic device) of the debugging platelet and a serial debugging interface; the single disk comprises a serial debugging interface, an analog switch and a CPLD of the single disk; connect host computer and debugging platelet through the USB line, the serial debugging interface of single-disk and debugging platelet is inserted respectively at debugging cable both ends, wherein:
the CPLD of the debugging platelet is used for determining an object to be debugged corresponding to the debugging instruction when receiving the debugging instruction sent by the upper computer; setting a communication protocol of a serial debugging interface of a debugging platelet as a target communication protocol corresponding to the object to be debugged;
the CPLD of the single disk is used for setting a communication protocol of a serial debugging interface of the single disk as a target communication protocol corresponding to the object to be debugged;
the CPLD of the debugging platelet is also used for sending the received debugging instruction sent by the upper computer to the CPLD of the single disc based on a target communication protocol and serial debugging interfaces of the debugging platelet and the single disc;
the single-disk CPLD is also used for executing the received debugging instruction;
when the object to be debugged is a single-disk CPLD, the CPLD of the debugging platelet sets the communication protocol of the serial debugging interface of the debugging platelet as an SPI protocol; the CPLD of the debugging platelet sends a first write command corresponding to the CPLD of the single disc of the SPI protocol type to the CPLD of the single disc through serial debugging interfaces of the debugging platelet and the single disc; writing a first preset value corresponding to the first write command into a debugging interface register of the CPLD of the single disk by the CPLD of the single disk; the single-disk CPLD modifies the state of the single-disk analog switch control signal according to the data of the debugging interface register, so that the communication protocol of the serial debugging interface of the single disk is set as the JTAG protocol corresponding to the first preset value; and the CPLD of the debugging small plate sets the communication protocol of the serial debugging interface of the debugging small plate as a JTAG protocol.
9. A readable storage medium having a debugger program stored thereon, wherein the debugger program, when executed by a processor, implements the steps of the debugging method as recited in any of claims 1-7.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1570877A (en) * | 2004-04-27 | 2005-01-26 | 中兴通讯股份有限公司 | Universal serial communication interface debugging device and method |
| CN103186458A (en) * | 2011-12-29 | 2013-07-03 | 联芯科技有限公司 | Embedded operating system-based simulation debugging system and method |
| CN105718339A (en) * | 2015-12-31 | 2016-06-29 | 山东大学 | FPGA/CPLD remote debugging system and method |
| CN206149268U (en) * | 2016-09-19 | 2017-05-03 | 昆明理工大学 | A wireless data transmission device for connecting mobile device |
| CN106776183A (en) * | 2016-12-22 | 2017-05-31 | 歌尔科技有限公司 | A kind of debug circuit, debugging apparatus, modulating system and a kind of electronic equipment |
| CN109815184A (en) * | 2017-11-21 | 2019-05-28 | 中兴通讯股份有限公司 | Debugging single board device and its control method, computer readable storage medium |
| CN110083560A (en) * | 2019-04-03 | 2019-08-02 | 杭州迪普科技股份有限公司 | A kind of more jtag interfaces switching chip, method and debugging single board system |
-
2020
- 2020-09-25 CN CN202011026850.0A patent/CN112181753B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1570877A (en) * | 2004-04-27 | 2005-01-26 | 中兴通讯股份有限公司 | Universal serial communication interface debugging device and method |
| CN103186458A (en) * | 2011-12-29 | 2013-07-03 | 联芯科技有限公司 | Embedded operating system-based simulation debugging system and method |
| CN105718339A (en) * | 2015-12-31 | 2016-06-29 | 山东大学 | FPGA/CPLD remote debugging system and method |
| CN206149268U (en) * | 2016-09-19 | 2017-05-03 | 昆明理工大学 | A wireless data transmission device for connecting mobile device |
| CN106776183A (en) * | 2016-12-22 | 2017-05-31 | 歌尔科技有限公司 | A kind of debug circuit, debugging apparatus, modulating system and a kind of electronic equipment |
| CN109815184A (en) * | 2017-11-21 | 2019-05-28 | 中兴通讯股份有限公司 | Debugging single board device and its control method, computer readable storage medium |
| CN110083560A (en) * | 2019-04-03 | 2019-08-02 | 杭州迪普科技股份有限公司 | A kind of more jtag interfaces switching chip, method and debugging single board system |
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