CN112164671A - Laminated hole structure and manufacturing method thereof - Google Patents
Laminated hole structure and manufacturing method thereof Download PDFInfo
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- CN112164671A CN112164671A CN202010943998.4A CN202010943998A CN112164671A CN 112164671 A CN112164671 A CN 112164671A CN 202010943998 A CN202010943998 A CN 202010943998A CN 112164671 A CN112164671 A CN 112164671A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
The application discloses a laminated hole structure and a manufacturing method thereof, and relates to the field of semiconductor manufacturing. The method comprises forming a first inter-metal dielectric layer; forming a first through hole in the first metal interlayer dielectric layer, wherein the first through hole is formed by a vertical structure and a bowl-shaped structure, the bowl-shaped structure is positioned above the vertical structure, and the size of an opening of the bowl-shaped structure is larger than that of the opening of the vertical structure; filling the first through hole, and forming a Ti/TiN layer on the top of the bowl-shaped structure in the first through hole; forming a second metal interlayer dielectric layer on the surface of the first metal interlayer dielectric layer; forming a second through hole in the second metal interlayer dielectric layer, wherein the second through hole is connected with the first through hole, and the bottom of the second through hole is surrounded by the bowl-shaped structure of the first through hole; filling the second through hole; the problem that through holes in a thicker metal interlayer dielectric layer are easy to be not qualified is solved; the effect of forming the through hole of the laminated structure meeting the requirements in the thicker metal interlayer dielectric layer is achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a laminated hole structure and a manufacturing method thereof.
Background
In the back end of the line of integrated circuit fabrication, some devices that need to withstand high voltages typically require thicker inter-metal dielectric (IMD) layers, such as: the thickness of the IMD is greater than 6um to protect the underlying device.
In the actual manufacturing process, the thickness of the single-layer IMD is limited by the deposition time of a PCO (grown oxide film) machine and the identity in the CMP process, and cannot exceed 3 um. In order to meet the thickness requirement of IMD, a layered growth mode can be adopted. The specific method comprises the following steps: forming IMD for many times, forming a through hole in each IMD after each IMD is formed, and filling the through hole to form a tungsten plug; the vias in each IMD are aligned.
However, when etching the upper IMD to form the via hole, there is a possibility of breaking the tungsten plug in the lower IMD, and the degree of alignment of the via hole in each IMD is limited by the overlay accuracy.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a stacked via structure and a method for fabricating the same. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a method for manufacturing a stacked pore structure, where the method includes:
forming a first metal interlayer dielectric layer;
forming a first through hole in the first metal interlayer dielectric layer, wherein the first through hole is formed by a vertical structure and a bowl-shaped structure, the bowl-shaped structure is positioned above the vertical structure, and the size of an opening of the bowl-shaped structure is larger than that of the opening of the vertical structure;
filling the first through hole, and forming a Ti/TiN layer on the top of the bowl-shaped structure in the first through hole;
forming a second metal interlayer dielectric layer on the surface of the first metal interlayer dielectric layer;
forming a second through hole in the second metal interlayer dielectric layer, wherein the second through hole is connected with the first through hole, and the bottom of the second through hole is surrounded by the bowl-shaped structure of the first through hole;
filling the second through hole.
Optionally, forming a first via in the first inter-metal dielectric layer includes:
defining a first through hole pattern above the first metal interlayer dielectric layer through a photoetching process;
etching the first metal interlayer dielectric layer by adopting an isotropic etching mode within preset time according to the first through hole pattern to form a bowl-shaped structure of the first through hole;
and continuously etching the first metal interlayer dielectric layer by adopting an anisotropic etching mode according to the first through hole pattern to form a vertical structure of the first through hole.
Optionally, filling the first via and forming a Ti/TiN layer on top of the bowl-shaped structure in the first via, includes:
depositing tungsten, and filling the first through hole with the tungsten;
etching the substrate back until a barrier layer space is formed at the top of the bowl-shaped structure;
forming a Ti/TiN layer until the barrier layer space at the top of the bowl-shaped structure is filled with the Ti/TiN layer;
and removing the Ti/TiN layer on the surface of the substrate.
Optionally, forming a second through hole in the second metal interlayer dielectric layer includes:
defining a second through hole pattern above the second metal interlayer dielectric layer through a photoetching process, wherein the second through hole pattern is surrounded by the bowl-shaped structure;
and etching the second metal interlayer dielectric layer by adopting an anisotropic etching mode according to the second through hole pattern to form a second through hole.
Optionally, filling the second via includes:
depositing tungsten, and filling the second through hole with the tungsten;
and removing the tungsten on the surface of the second metal interlayer dielectric layer by a CMP process.
Optionally, before depositing the tungsten, the method further includes:
an adhesive layer is formed.
Optionally, the bonding layer is a Ti/TiN layer.
Optionally, before forming the first inter-metal dielectric layer, the method further includes:
forming an x metal layer, wherein x is a positive integer;
after filling the second through hole, the method further comprises the following steps:
forming the x +1 th metal layer.
In a second aspect, embodiments of the present application provide a stacked via structure, including at least a first via and a second via;
the first through hole is positioned in the first metal interlayer dielectric layer, the second through hole is positioned in the second metal interlayer dielectric layer, and the second metal interlayer dielectric layer is positioned above the surface of the first metal interlayer dielectric layer;
the first through hole is composed of a vertical structure and a bowl-shaped structure, the bowl-shaped structure is positioned above the vertical structure, and the size of an opening of the bowl-shaped structure is larger than that of the opening of the vertical structure;
the second through hole is of a vertical structure, is connected with the first through hole, and the bottom of the second through hole is surrounded by the bowl-shaped structure of the first through hole;
the vertical structure in the first through hole is filled with tungsten, the bowl-shaped structure in the first through hole is filled with tungsten, and a Ti/TiN layer is formed at the top of the bowl-shaped structure;
the second via is filled with tungsten.
Optionally, an adhesive layer is further disposed in the first through hole and the second through hole;
the adhesion layer is located outside the tungsten.
Optionally, the bonding layer is a Ti/TiN layer.
Optionally, the first inter-metal dielectric layer and the second inter-metal dielectric layer are located between the xth metal layer and the xth +1 metal layer, where x is a positive integer.
The technical scheme at least comprises the following advantages:
by forming the first metal interlayer dielectric layer, forming the first through hole in the first metal interlayer dielectric layer, filling the first through hole, forming the second through hole in the first metal interlayer dielectric layer, filling the second through hole, and expanding the alignment precision when the second through hole is etched by using the bowl-shaped structure in the first through hole, the problem that the through hole in the metal interlayer dielectric layer is not qualified easily due to step-by-step etching after the thicker metal interlayer dielectric layer is grown in a layered manner is solved; the effect of forming the through hole with the laminated structure meeting the requirements when the thicker metal interlayer dielectric layer grows in a laminated manner is achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a stacked via structure according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a first through hole provided in an embodiment of the present application during a manufacturing process;
fig. 3 is a schematic structural diagram of a first through hole provided in an embodiment of the present application;
FIG. 4 is a schematic diagram of a second via provided in an embodiment of the present application during a fabrication process;
FIG. 5 is a schematic diagram of a second via provided in an embodiment of the present application during a fabrication process;
FIG. 6 is a schematic diagram of a stacked via structure provided by an embodiment of the present application during fabrication;
FIG. 7 is a schematic diagram of a stacked via structure provided by an embodiment of the present application during fabrication;
FIG. 8 is a schematic diagram of a stacked via structure provided by an embodiment of the present application during fabrication;
FIG. 9 is a schematic diagram of a stacked via structure provided by an embodiment of the present application during fabrication;
FIG. 10 is a schematic diagram of a stacked via structure provided by an embodiment of the present application during fabrication;
FIG. 11 is a schematic diagram of a stacked via structure provided by an embodiment of the present application during fabrication;
FIG. 12 is a schematic diagram of a stacked via structure provided by an embodiment of the present application during fabrication;
fig. 13 is a schematic diagram of a stacked pore structure provided in an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for fabricating a stacked via structure according to an embodiment of the present application is shown, where the stacked via is used to connect two metal layers, and the method at least includes the following steps:
Forming a first metal interlayer dielectric layer on the surface of the x metal layer; x is a positive integer.
The thickness of the first metal interlayer dielectric layer is determined according to actual conditions, and the first metal interlayer dielectric layer is not conductive.
And 102, forming a first through hole in the first metal interlayer dielectric layer, wherein the first through hole is formed by a vertical structure and a bowl-shaped structure, the bowl-shaped structure is positioned above the vertical structure, and the opening size of the bowl-shaped structure is larger than that of the vertical structure.
Optionally, a first through hole is formed in the first metal interlayer dielectric layer through photolithography and etching processes.
As shown in fig. 2, a first through hole 22 is formed in the first metal interlayer dielectric layer 21, the first through hole 22 is formed by a vertical structure 222 and a bowl-shaped structure 221, the bowl-shaped structure 221 is located above the vertical structure 222, the bowl-shaped structure 221 is communicated with the vertical structure 222, the size of an opening of the bowl-shaped structure 221 is larger than that of the opening of the vertical structure 222, and the size of the bottom of the bowl-shaped structure 221 is the same as that of the opening of the vertical structure 222.
And 103, filling the first through hole, and forming a Ti/TiN layer on the top of the bowl-shaped structure in the first through hole.
As shown in fig. 3, the bowl-shaped structure 221 and the vertical structure 222 constituting the first via-hole 22 are filled with a metal, and a Ti/TiN layer 223 is formed on the top of the bowl-shaped structure 221; the Ti/TiN layer 223 is composed of stacked Ti and TiN, and the Ti and TiN of the Ti/TiN layer are formed in the same process step.
Optionally, the filler metal is tungsten.
The Ti/TiN layer on the top of the bowl-shaped structure is used as a barrier layer, so that the filled first through hole can be prevented from being damaged when the second through hole is formed.
And 104, forming a second metal interlayer dielectric layer on the surface of the first metal interlayer dielectric layer.
And depositing on the surface of the first metal interlayer dielectric layer to form a second metal interlayer dielectric layer, wherein the thickness of the second metal interlayer dielectric layer is determined according to the actual condition.
Optionally, the sum of the thickness of the first metal interlayer dielectric layer and the thickness of the second metal interlayer dielectric layer is greater than 6 um.
As shown in fig. 4, the second inter-metal dielectric layer 23 covers the first inter-metal dielectric layer 21.
And 105, forming a second through hole in the second metal interlayer dielectric layer, wherein the second through hole is connected with the first through hole, and the bottom of the second through hole is surrounded by the bowl-shaped structure of the first through hole.
Optionally, a second through hole is formed in the second metal interlayer dielectric layer through photolithography and etching processes.
As shown in fig. 5, the second via 24 is located above the first via, and the second via 24 connects the first via, and the bottom of the second via 24 is surrounded by the bowl-shaped structure 221 of the first via, and the bottom of the second via 24 is in contact with the Ti/TiN layer on top of the bowl-shaped structure 221 of the first via.
Because the opening size of the bowl-shaped structure of the first through hole is larger than that of the first through hole or the second through hole, even if slight deviation occurs in the position of the second through hole relative to the position of the vertical structure in the first through hole when the second through hole is formed, the connection between the first through hole and the second through hole is not influenced, and the conduction effect of the laminated hole in the first metal interlayer dielectric layer and the second metal interlayer dielectric layer can be ensured.
Optionally, the second via hole is filled with metal, and after the filling is completed, the residual metal on the surface of the dielectric layer between the second metal layers is removed.
In summary, in the method for manufacturing a stacked hole provided in the embodiment of the present application, the first inter-metal dielectric layer is formed, the first through hole is formed in the first inter-metal dielectric layer, the first through hole is filled, the second through hole is formed in the first inter-metal dielectric layer, and the second through hole is filled, so that the alignment precision during etching of the second through hole is increased by using the bowl-shaped structure in the first through hole, and the problem that the through hole in the inter-metal dielectric layer is not satisfactory easily due to step-by-step etching after the thicker inter-metal dielectric layer is grown in layers is solved; the effect of forming the through hole with the laminated structure meeting the requirements when the thicker metal interlayer dielectric layer grows in a laminated manner is achieved.
In an alternative embodiment based on the embodiment shown in fig. 1, the first inter-metal dielectric layer and the second inter-metal dielectric layer are located between the x-th metal layer and the x + 1-th metal layer, and the surface of the second inter-metal dielectric layer is formed with the x + 1-th metal layer, so that the method further includes forming the x-th metal layer before step 101; after step 105, forming an x +1 th metal layer; x is a positive integer.
Another embodiment of the present application provides a method for manufacturing a stacked via structure, which at least includes the following steps:
step 201, forming an x-th metal layer.
Step 202, a first inter-metal dielectric layer is formed.
And forming a first metal interlayer dielectric layer on the surface of the x-th metal layer.
In step 203, a first via pattern is defined above the first inter-metal dielectric layer by a photolithography process.
A photoresist 25 is spin-coated on the surface of the first inter-metal dielectric layer 21, and after exposure and development by using a mask including a first via pattern, a first via pattern 26 is formed, as shown in fig. 6.
The opening size of the first via pattern is the same as the opening size of the vertical structure in the first via.
And 204, etching the first metal interlayer dielectric layer by adopting an isotropic etching mode within preset time according to the first through hole pattern to form a bowl-shaped structure of the first through hole.
The depth of the bowl is related to the etching time, and the predetermined time is determined according to the design depth of the bowl. It should be noted that the shape of the bowl-shaped structure is determined according to the actual etching result, and the embodiment of the present application is only an exemplary illustration.
As shown in fig. 7, a bowl-shaped structure 221 is formed in the first inter-metal dielectric layer 21 under the first via pattern 26.
Due to the fact that the isotropic etching mode is adopted for etching, the size of the opening of the bowl-shaped structure is larger than that of the opening of the first through hole pattern.
And step 205, continuously etching the first metal interlayer dielectric layer by adopting an anisotropic etching mode according to the first through hole pattern to form a vertical structure of the first through hole.
Due to the fact that anisotropic etching is adopted for etching, the size of the opening of the vertical structure is the same as that of the opening of the first through hole pattern.
The first via is used to connect the x-th metal layer under the first intermetal dielectric layer 21.
As shown in fig. 8, a vertical structure 222 is formed in the first inter-metal dielectric layer 21, the bowl-shaped structure 221 is communicated with the vertical structure 222, and the vertical structure 222 is located below the bowl-shaped structure 221.
And after the etching is finished, removing the photoresist on the surface of the substrate.
In step 206, tungsten is deposited and the first via is filled with tungsten.
Tungsten is deposited, the vertical structures 222 and the bowl-shaped structures 221 in the first via hole are filled with tungsten 27, and the surface of the first intermetal dielectric layer 21 is also formed with tungsten 27, as shown in fig. 9.
Step 207, the substrate is etched back until a barrier space is formed on top of the bowl.
Etching back the surface of the substrate to remove tungsten on the surface of the first metal interlayer dielectric layer; and after removing the tungsten on the surface of the first metal interlayer dielectric layer, continuing etching until a barrier layer space is formed at the top of the bowl-shaped structure, and stopping etching.
As shown in fig. 10, after etching, no tungsten remains on the surface of the first ild layer 21, and a barrier space 28 is formed on the top of the bowl 221.
The barrier space 28 is used to form a Ti/TiN layer.
And step 208, forming a Ti/TiN layer until the barrier layer space at the top of the bowl-shaped structure is filled with the Ti/TiN layer.
Step 209, the Ti/TiN layer on the surface of the substrate is removed.
When a Ti/TiN layer is formed on the top of the bowl-shaped structure, a Ti/TiN layer is also formed on the surface of the first metal interlayer dielectric layer, and the redundant Ti/TiN layer on the surface of the first metal interlayer dielectric layer is removed through a wet etching process; the resulting first via structure is shown in fig. 3.
Step 210, a second inter-metal dielectric layer is formed on the surface of the first inter-metal dielectric layer.
This step is explained in step 104 above and will not be described here.
Step 211, defining a second via pattern over the second inter-metal layer dielectric by a photolithography process, the second via pattern being surrounded by the bowl-shaped structure.
And (3) spinning photoresist 31 on the surface of the second metal interlayer dielectric layer 23, exposing by using a mask plate with a second through hole pattern, and developing to form a second through hole pattern 32, wherein the second through hole pattern 32 is aligned to the bowl-shaped structure 221 as shown in fig. 11.
And 212, etching the second metal interlayer dielectric layer by adopting an anisotropic etching mode according to the second through hole pattern to form a second through hole.
And the size of the opening of the second through hole formed in the second metal interlayer dielectric layer is the same as that of the opening of the second through hole pattern due to the adoption of the anisotropic etching mode.
And after the etching is finished, removing the photoresist on the surface of the second metal interlayer dielectric layer.
The second via formed in the second intermetal dielectric layer is shown in fig. 5.
In step 213, tungsten is deposited and the second via is filled with tungsten.
Tungsten is deposited, the second via hole 24 is filled with tungsten 27, and the surface of the second intermetal dielectric layer 23 is also formed with tungsten 27, as shown in fig. 12.
Step 214, removing the tungsten on the surface of the second inter-metal dielectric layer by a CMP process.
As shown in fig. 13, the tungsten on the surface of the second ild layer 23 is removed.
Step 215, forming the x +1 th metal layer.
And forming an x +1 metal layer on the surface of the second metal interlayer dielectric layer.
In an alternative embodiment to the above embodiment, an adhesion layer is formed within the via prior to filling the via with tungsten; that is, before filling the first via hole, an adhesive layer is formed within the first via hole; an adhesive layer is formed within the second via hole prior to filling the second via hole. After the filling of the through hole is completed, the redundant adhesive layer on the surface of the metal interlayer dielectric layer is also removed.
Optionally, the adhesion layer is a Ti/TiN barrier layer. When the bonding layer is formed, Ti is firstly deposited and used as a bonding agent, the Ti reacts with the lower layer material to reduce the contact resistance, and then TiN is deposited and used as a diffusion barrier layer of tungsten.
The present embodiment provides a stacked via structure, which includes at least a first via and a second via 24, as shown in fig. 13.
The first via hole is located in the first inter-metal dielectric layer 21, the second via hole 24 is located in the second inter-metal dielectric layer 23, and the second inter-metal dielectric layer 23 is located above the surface of the first inter-metal dielectric layer 21.
The first through hole is composed of a vertical structure 222 and a bowl-shaped structure 221, the bowl-shaped structure 221 is located above the resin structure 222, and the opening size of the bowl-shaped structure 221 is larger than that of the vertical structure. The bowl-shaped structure 221 is communicated with the vertical structure 222, and the bottom size of the bowl-shaped structure 221 is the same as the opening size of the vertical structure 222.
The vertical structure 22 in the first via is filled with tungsten, the bowl structure 221 in the first via is filled with tungsten, and a Ti/TiN layer 223 is formed on top of the bowl structure 221. In the bowl-like structure 221, tungsten is under the Ti/TiN layer 223.
The Ti/TiN layer 223 on the top of the bowl-shaped structure 221 serves as a barrier layer to prevent a tungsten plug formed in the first inter-metal dielectric layer from being damaged when the second through hole in the second inter-metal dielectric layer is formed by etching.
The second via hole 24 is filled with tungsten.
Optionally, an adhesive layer is further disposed in the first through hole and the second through hole; the adhesion layer is located outside the tungsten.
Optionally, the bonding layer is a Ti/TiN layer. And forming a Ti/TiN layer in the first through hole and the second through hole, and filling tungsten.
The first inter-metal dielectric layer 21 and the second inter-metal dielectric layer 23 are located between the x-th metal layer and the x + 1-th metal layer, and x is a positive integer.
When a thicker metal interlayer dielectric layer (for example, a thickness greater than 6um) needs to be formed between 2 metal layers, and a through hole is formed in the metal interlayer dielectric layer, the stacked hole structure shown in fig. 13 can be formed by using the method provided in the embodiment of the present application.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (12)
1. A method of fabricating a stacked via structure, the method comprising:
forming a first metal interlayer dielectric layer;
forming a first through hole in the first metal interlayer dielectric layer, wherein the first through hole is composed of a vertical structure and a bowl-shaped structure, the bowl-shaped structure is positioned above the vertical structure, and the size of an opening of the bowl-shaped structure is larger than that of the opening of the vertical structure;
filling the first through hole, and forming a Ti/TiN layer on the top of the bowl-shaped structure in the first through hole;
forming a second metal interlayer dielectric layer on the surface of the first metal interlayer dielectric layer;
forming a second through hole in the second metal interlayer dielectric layer, wherein the second through hole is connected with the first through hole, and the bottom of the second through hole is surrounded by the bowl-shaped structure of the first through hole;
and filling the second through hole.
2. The method of claim 1, wherein forming a first via in the first intermetal dielectric layer comprises:
defining a first through hole pattern above the first metal interlayer dielectric layer through a photoetching process;
etching the first metal interlayer dielectric layer by adopting an isotropic etching mode within preset time according to the first through hole pattern to form a bowl-shaped structure of a first through hole;
and continuously etching the first metal interlayer dielectric layer by adopting an anisotropic etching mode according to the first through hole pattern to form a vertical structure of the first through hole.
3. The method of claim 1, wherein the filling the first via and forming a Ti/TiN layer on top of the bowl-shaped structure in the first via comprises:
depositing tungsten, wherein the first through hole is filled with tungsten;
back etching the substrate until a barrier layer space is formed at the top of the bowl-shaped structure;
forming a Ti/TiN layer until the barrier layer space at the top of the bowl-shaped structure is filled with the Ti/TiN layer;
and removing the Ti/TiN layer on the surface of the substrate.
4. The method of claim 1, wherein forming a second via in the second intermetal dielectric layer comprises:
defining a second via pattern over the second inter-metal dielectric layer by a photolithography process, the second via pattern being surrounded by the bowl;
and etching the second metal interlayer dielectric layer by adopting an anisotropic etching mode according to the second through hole pattern to form the second through hole.
5. The method of claim 1, wherein the filling the second via comprises:
depositing tungsten, wherein the second through hole is filled with tungsten;
and removing the tungsten on the surface of the second metal interlayer dielectric layer by a CMP process.
6. The method of claim 3 or 5, wherein prior to said depositing tungsten, the method further comprises:
an adhesive layer is formed.
7. The method of claim 6, wherein the adhesion layer is a Ti/TiN layer.
8. The method of any of claims 1 to 7, further comprising, prior to forming the first intermetal dielectric layer:
forming an x metal layer, wherein x is a positive integer;
after the filling of the second through hole, the method further comprises:
forming the x +1 th metal layer.
9. A stacked via structure comprising at least a first via and a second via;
the first through hole is positioned in the first metal interlayer dielectric layer, the second through hole is positioned in the second metal interlayer dielectric layer, and the second metal interlayer dielectric layer is positioned above the surface of the first metal interlayer dielectric layer;
the first through hole is formed by a vertical structure and a bowl-shaped structure, the bowl-shaped structure is positioned above the vertical structure, and the size of an opening of the bowl-shaped structure is larger than that of the opening of the vertical structure;
the second through hole is of a vertical structure, is connected with the first through hole, and is surrounded by the bowl-shaped structure of the first through hole at the bottom;
the vertical structure in the first through hole is filled with tungsten, the bowl-shaped structure in the first through hole is filled with tungsten, and a Ti/TiN layer is formed at the top of the bowl-shaped structure;
the second via is filled with tungsten.
10. The laminated via structure of claim 9, wherein an adhesive layer is further disposed within the first and second vias;
the adhesion layer is located on the outer side of the tungsten.
11. The laminated pore structure of claim 10, wherein said adhesion layer is a Ti/TiN layer.
12. The stacked via structure of claim 10, wherein the first and second intermetal dielectric layers are located between an x-th metal layer and an x + 1-th metal layer, x being a positive integer.
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| CN1967845A (en) * | 2005-11-15 | 2007-05-23 | 东部电子股份有限公司 | Semiconductor device and its manufacturing method |
| CN101635272A (en) * | 2008-07-25 | 2010-01-27 | 台湾积体电路制造股份有限公司 | Method for forming interconnect structures |
| CN102683274A (en) * | 2012-06-05 | 2012-09-19 | 上海集成电路研发中心有限公司 | Air-gap process applied to copper interconnection |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1967845A (en) * | 2005-11-15 | 2007-05-23 | 东部电子股份有限公司 | Semiconductor device and its manufacturing method |
| CN101635272A (en) * | 2008-07-25 | 2010-01-27 | 台湾积体电路制造股份有限公司 | Method for forming interconnect structures |
| CN102683274A (en) * | 2012-06-05 | 2012-09-19 | 上海集成电路研发中心有限公司 | Air-gap process applied to copper interconnection |
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