CN112162936A - Method and system for dynamically enhancing FLASH erasing frequency - Google Patents

Method and system for dynamically enhancing FLASH erasing frequency Download PDF

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CN112162936A
CN112162936A CN202011062884.5A CN202011062884A CN112162936A CN 112162936 A CN112162936 A CN 112162936A CN 202011062884 A CN202011062884 A CN 202011062884A CN 112162936 A CN112162936 A CN 112162936A
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written
address
data
page
read
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CN112162936B (en
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苏昆
肖灵
何涛
董逢华
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Wuhan Tianyu Information Industry Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a method and a system for dynamically enhancing FLASH erasing times, which relate to the field of intelligent cards, wherein the method comprises the following operations of writing FLASH data and reading FLASH data, and the operations of writing FLASH data comprise the following steps: acquiring data to be written and a target address of the data to be written; dividing a target address of data to be written into a plurality of addresses to be written according to a page alignment mode, dividing the data to be written into a plurality of data blocks to be written, and enabling the addresses to be written of the target address to correspond to the data blocks to be written of the data to be written; sequentially judging whether each address to be written is a bad page, if so, acquiring a new page corresponding to the current address to be written, and writing a data block to be written corresponding to the current address to be written into the address of the new page; if not, writing the corresponding data block to be written in the current address to be written; the invention can effectively improve the use efficiency of FLASH.

Description

Method and system for dynamically enhancing FLASH erasing frequency
Technical Field
The invention relates to the field of smart cards, in particular to a method and a system for dynamically enhancing the erasing times of FLASH.
Background
In the design and development of the smart card, the service life of a FLASH (FLASH memory) chip of a common smart card is only 10W times, but in the actual application process, some applications require that the erasing times of the card is far more than 10W times, and even millions of times are needed to meet the actual use requirements. The current common methods include two methods, one method is to apply for a plurality of pages in advance for a specific application, the write operation is used in the pages in a polling manner, and the erasing times of the application are improved in this way, but the highest erasing times are based on the number of the pages applied in advance, and at the very beginning, it must be clearly known which data erasing times of the application need enhancement processing, the actual erasing times of the application without enhancement processing can only depend on the life of the FLASH, and a JAVA (object-oriented programming language) card commonly used at present in the smart card can download a plurality of applications, which can be downloaded in the using process, so the using times of the applications downloaded later can only depend on the life of the FLASH of the chip, and the enhancement processing cannot be achieved; the other is to perform rotation processing on all FLASH areas of the whole chip, which can improve the erasing times of all data of all applications, but this scheme needs to reserve more FLASH blank areas for rotation processing and needs more FLASH spaces to meet the requirements.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a method and a system for dynamically enhancing the erasing times of FLASH, which can effectively improve the use efficiency of FLASH.
In order to achieve the above object, the present invention provides a method for dynamically enhancing FLASH erasing times, which is used for implementing operations of writing FLASH data and reading FLASH data applied in an intelligent card,
the FLASH data writing operation comprises the following steps:
acquiring data to be written and a target address of the data to be written;
dividing a target address of data to be written into a plurality of addresses to be written according to a page alignment mode, dividing the data to be written into a plurality of data blocks to be written, and enabling the addresses to be written of the target address to correspond to the data blocks to be written of the data to be written;
sequentially judging whether each address to be written is a bad page, if so, acquiring a new page corresponding to the current address to be written, and writing a data block to be written corresponding to the current address to be written into the address of the new page; if not, writing the corresponding data block to be written in the current address to be written;
the FLASH data reading operation comprises the following steps:
acquiring a target address of data to be read;
dividing a target address of data to be read into a plurality of addresses to be read according to a page alignment mode;
and sequentially judging whether each address to be read is a bad page, if so, acquiring a new page corresponding to the address to be read, and reading data from the address of the new page, otherwise, reading data from the current address to be read, wherein the bad pages all correspond to the new page.
On the basis of the technical proposal, the device comprises a shell,
in the multiple addresses to be written of the target address of the data to be written, except for the 1 st address to be written and the last 1 address to be written, the lengths of other addresses to be written are the length of one unit page;
in the multiple addresses to be read of the data to be read, except for the 1 st address to be read and the last 1 address to be read, the lengths of the other addresses to be read are the length of one unit page.
On the basis of the technical proposal, the device comprises a shell,
for the length of the 1 st address to be written, the calculation formula is as follows:
LEN1＝PAGESIZE-(ADDR&～PAGESIZE)
therein, LEN1Indicating the length of the 1 st address to be written, and if LEN1Is 0, then the LEN is corrected1PAGESIZE, where PAGESIZE represents the length of a unit page, and ADDR represents the start address of the target address of the data to be written;
and for the length of the last 1 address to be written, subtracting the sum of the lengths of all addresses to be written except the last 1 address to be written from the total length of the target address of the data to be written.
On the basis of the technical proposal, the device comprises a shell,
judging whether the address to be written is a bad page, specifically: judging whether the requirements are met
EADDRm≤ADDRiAnd ADDRi≤EADDRm+PAGESIZE
If yes, the current address to be written is a bad page, if not, the current address to be written is not a bad page, wherein the EADDRmIndicating the starting address, ADDR, of a bad pageiAnd the starting address of the ith address to be written is shown, and i is a positive integer.
On the basis of the technical scheme, a solving formula of the initial address of the new page corresponding to the address to be written is as follows:
NADDRi＝NADDRm+ADDRi&(～PAGESIZE)
wherein, the NADDRiIndicating the starting address of the new page, NADDRmDenotes EADDRmCorresponding to the starting address of the new page.
On the basis of the technical proposal, the device comprises a shell,
when the data block to be written is written into the address of the new page, if the writing fails, acquiring the new page, writing the data block to be written into the newly acquired address of the new page, and recording the new page corresponding to the address to be written corresponding to the current data block to be written as the newly acquired new page;
when the data block to be written is written into the address to be written, if the writing fails, a new page is obtained, the data block to be written is written into the newly obtained address of the new page, and the address to be written corresponding to the current data block to be written is recorded to be corresponding to the obtained new page.
On the basis of the technical scheme, the method further comprises the step of recovering the FLASH space operation, wherein the step of recovering the FLASH space operation comprises the following steps:
acquiring a target address to be recovered and the length of data to be recovered;
and judging whether the FLASH space to be recovered has a bad page or not based on the target address to be recovered, if so, deleting the bad page in the FLASH space to be recovered, marking the rest FLASH space to be recovered as an available FLASH space, and otherwise, marking the FLASH space to be recovered as the available FLASH space.
The invention provides a system for dynamically enhancing FLASH erasing times, which is used for realizing the method and comprises the following steps:
the read-write management module is used for writing data to be written into the chip storage area and reading the data to be read from the chip storage area when the application calls the platform layer to perform read-write operation of the FLASH data;
the bad page management module is used for recording a new page corresponding to a bad page in the chip storage area;
and the available space dynamic management module is used for recovering the FLASH space and eliminating bad pages when the FLASH space is recovered.
On the basis of the above technical solution, when writing data to be written into the chip storage area, the read-write management module is specifically configured to:
acquiring data to be written and a target address of the data to be written;
dividing a target address of data to be written into a plurality of addresses to be written according to a page alignment mode, dividing the data to be written into a plurality of data blocks to be written, and enabling the addresses to be written of the target address to correspond to the data blocks to be written of the data to be written;
sequentially judging whether each address to be written is a bad page, if so, acquiring a new page corresponding to the current address to be written, and writing a data block to be written corresponding to the current address to be written into the address of the new page; and if not, writing the corresponding data block to be written in the current address to be written.
On the basis of the above technical solution, when reading data to be written in a chip storage area, the read-write management module is specifically configured to:
acquiring a target address of data to be read;
dividing a target address of data to be read into a plurality of addresses to be read according to a page alignment mode;
and sequentially judging whether each address to be read is a bad page, if so, acquiring a new page corresponding to the address to be read, and reading data from the address of the new page, otherwise, reading data from the current address to be read, wherein the bad pages all correspond to the new page.
Compared with the prior art, the invention has the advantages that: extra space does not need to be reserved in advance for protecting specific application data, application data with high use frequency can be automatically detected in the use process, and the erasing times are enhanced by pertinently distributing the space; according to the requirement of the application data in the actual use process, dynamically allocating an additional space for enhancing the erasing times; the available space of the chip is optimal, all data of all applications on the smart card can be effectively covered, the erasing times of the application data can be increased all the time as long as the unused available space remains on the smart card, and the use efficiency of the FLASH is effectively improved.
Drawings
FIG. 1 is a flow chart of the operation of writing FLASH data according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a FLASH data read operation according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a system for dynamically enhancing FLASH erase times according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a method for dynamically enhancing FLASH erasing times, which does not need to reserve extra space in advance for protecting specific application data, can automatically detect application data with high use frequency in the use process, and purposely allocates the space to enhance the erasing times. The embodiment of the invention correspondingly provides a system for dynamically enhancing the FLASH erasing times.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, an embodiment of the present invention provides a method for dynamically enhancing FLASH erasing times, which is used for implementing operations of writing FLASH data and reading FLASH data applied in an intelligent card. The FLASH data writing operation comprises the following steps:
s101: and acquiring the data to be written and the target address of the data to be written.
When writing FLASH data, the data to be written and the target address of the data to be written need to be known, and further the data length of the data to be written can be known.
S102: dividing a target address of data to be written into a plurality of addresses to be written according to a page alignment mode, dividing the data to be written into a plurality of data blocks to be written, and enabling the addresses to be written of the target address to correspond to the data blocks to be written of the data to be written. In a plurality of addresses to be written of a target address of data to be written, except for the 1 st address to be written and the last 1 address to be written, the lengths of other addresses to be written are the length of one unit page.
For example, the target address to be accessed is [0x0D1320, 0x0D1560), the page size is 0x100, and then the 3 blocks [0x0D1320, 0x0D1400 ], [0x0D1400, 0x0D1500) and [0x0D1500, 0x0D1560) can be divided in a page aligned manner.
Length of block 1:
LEN1＝PAGESIZE(0x100)-(ADDR(0x0D1320)&～PAGESIZE(～0x100))＝0x100-0x20＝0xE0
the middle block length is one page size:
LEN2＝0x0D1500-0x0D1400＝0x100
tail block size:
LEN3＝srclen(0x0D1560-0x0D1320)-len1(0xE0)-len2(0x100)＝0x240-0xE0-0x100＝0x60。
s103: sequentially judging whether each address to be written is a bad page, if so, acquiring a new page corresponding to the current address to be written, and writing a data block to be written corresponding to the current address to be written into the address of the new page; if not, writing the corresponding data block to be written in the current address to be written;
in the embodiment of the invention, when judging whether the address to be written is a bad page, judging whether the current address to be written is a bad page according to the sequence from beginning to end, taking out each bad page to compare with the current address to be written, if the current address to be written is a bad page, acquiring a new page corresponding to the bad page, and writing a data block to be written corresponding to the current address to be written into the new page; and if the page is not bad, directly writing the corresponding data block to be written in the current address to be written. Before writing, a whole page of data where an address to be written is located needs to be read into a Random Access Memory (RAM) for backup, and a current data block to be written is used for covering corresponding data in the RAM.
In the embodiment of the invention, when a data block to be written is written into an address of a new page, if the writing fails, the new page is obtained, the data block to be written is written into the newly obtained address of the new page, and the new page corresponding to the address to be written corresponding to the current data block to be written is recorded as the newly obtained new page; when the data block to be written is written into the address to be written, if the writing fails, a new page is obtained, the data block to be written is written into the newly obtained address of the new page, and the address to be written corresponding to the current data block to be written is recorded to be corresponding to the obtained new page.
Specifically, during the above-mentioned write operation, a failure in writing a normal page or a new page may occur due to the number of times of erasing and writing of the target page reaching the life of the chip (there are various ways to detect the write failure, such as checking whether the written data is consistent with the re-read data after the write operation, or some chips may provide a flag indicating whether the write is successful or not). If the writing fails, recording the page of the current address to be written as a bad page A, then newly applying for a new page B, then traversing the existing records, if the bad page A is a new page in a record C, updating the new page in the record C into the new page B, and adding a new record containing the bad page A and the new page B; if the bad page A does not exist in the record, only one record comprising the bad page A and the new page B needs to be added.
Referring to fig. 2, in the embodiment of the present invention, the operation of reading FLASH data includes:
s201: acquiring a target address of data to be read;
s202: dividing a target address of data to be read into a plurality of addresses to be read according to a page alignment mode; in the multiple addresses to be read of the data to be read, except for the 1 st address to be read and the last 1 address to be read, the lengths of the other addresses to be read are the length of one unit page.
S203: and sequentially judging whether each address to be read is a bad page, if so, acquiring a new page corresponding to the address to be read, and reading data from the address of the new page, otherwise, reading data from the current address to be read, wherein the bad pages all correspond to the new page.
In the embodiment of the present invention, for the length of the 1 st address to be written, the calculation formula is:
LEN1＝PAGESIZE-(ADDR&～PAGESIZE)
therein, LEN1Indicating the length of the 1 st address to be written, and if LEN1Is 0, then the LEN is corrected1PAGESIZE, where PAGESIZE represents the length of a unit page, and ADDR represents the start address of the target address of the data to be written; the initial address of the subsequent address to be written is obtained by calculation according to the initial address and the length of the previous address to be written, and the calculation formula is as follows:
ADDRi＝ADDRi-1+LENi-1
wherein ADDRiIndicating the starting address, ADDR, of the ith address to be writteni-1Indicating the starting address, LEN, of the i-1 th address to be writteni-1Indicating the length of the i-1 th address to be written.
And for the length of the last 1 address to be written, subtracting the sum of the lengths of all addresses to be written except the last 1 address to be written from the total length of the target address of the data to be written.
In the embodiment of the present invention, determining whether an address to be written is a bad page specifically includes: judging whether the requirements are met
EADDRm≤ADDRiAnd ADDRi≤EADDRm+PAGESIZE
If yes, the current address to be written is a bad page, if not, the current address to be written is not a bad page, wherein the EADDRmIndicating the starting address, ADDR, of a bad pageiAnd the starting address of the ith address to be written is shown, and i is a positive integer.
In the embodiment of the present invention, a solving formula of the start address of the new page corresponding to the address to be written is:
NADDRi＝NADDRm+ADDRi&(～PAGESIZE)
wherein, the NADDRiIndicating the starting address of the new page, NADDRmDenotes EADDRmCorresponding to the starting address of the new page. The starting addresses of block 2 and subsequent blocks of data to be written are both page aligned and may be directly equal to NADDRm, but the address of block 1 is in the middle of a page and the actual address to be written must be calculated. Such as:
ADDRi 0x0D1330, NADDRm 0x082500, page size 0x100
Then naddir 0x082500+0x0D1330&0xFF 0x 082530.
It should be noted that, in the embodiment of the present invention, the calculation formula or the determination formula for the address to be read and whether the address to be read is a bad page is similar to that described above.
The method for dynamically enhancing the FLASH erasing times of the embodiment of the invention also comprises the step of recovering FLASH space operation, wherein the step of recovering FLASH space operation comprises the following steps:
a: acquiring a target address to be recovered and the length of data to be recovered;
b: and judging whether the FLASH space to be recovered has a bad page or not based on the target address to be recovered, if so, deleting the bad page in the FLASH space to be recovered, marking the rest FLASH space to be recovered as an available FLASH space, and otherwise, marking the FLASH space to be recovered as the available FLASH space.
According to the method for dynamically enhancing the FLASH erasing times, provided by the embodiment of the invention, no extra space needs to be reserved in advance for protecting specific application data, the application data with high use frequency can be automatically detected in the use process, and the erasing times are enhanced by pertinently distributing the space; according to the requirement of the application data in the actual use process, dynamically allocating an additional space for enhancing the erasing times; the available space of the chip is optimal, all data of all applications on the smart card can be effectively covered, the erasing times of the application data can be increased all the time as long as the unused available space remains on the smart card, and the use efficiency of the FLASH is effectively improved.
Referring to fig. 3, the system for dynamically enhancing FLASH erase times according to the embodiment of the present invention is configured to implement the method described above, and specifically, the system for dynamically enhancing FLASH erase times according to the embodiment of the present invention includes a read-write management module, a bad page management module, and an available space dynamic management module.
The read-write management module is used for writing data to be written into the chip storage area and reading the data to be read from the chip storage area when the application calls the platform layer to perform read-write operation of the FLASH data; the bad page management module is used for recording a new page corresponding to a bad page in the chip storage area; the available space dynamic management module is used for recovering the FLASH space and eliminating bad pages when the FLASH space is recovered.
Specifically, the table recorded by the bad page management module is shown in table 1 below.
TABLE 1
Record 1 Bad page address 1 New page address 1
Record 2 Bad page address 2 New page address 2
…
Record n Bad page address n New page address n
The table of available space dynamic management module records is shown in table 2 below.
TABLE 2
Record 1 Marking Available space address 1 Length of available space 1
Record 2 Marking Available space address 2 Length of available space 2
…
Record n Marking Available space address n Length n of available space
When writing data to be written into the chip storage area, the read-write management module is specifically configured to:
acquiring data to be written and a target address of the data to be written;
dividing a target address of data to be written into a plurality of addresses to be written according to a page alignment mode, dividing the data to be written into a plurality of data blocks to be written, and enabling the addresses to be written of the target address to correspond to the data blocks to be written of the data to be written;
sequentially judging whether each address to be written is a bad page, if so, acquiring a new page corresponding to the current address to be written, and writing a data block to be written corresponding to the current address to be written into the address of the new page; and if not, writing the corresponding data block to be written in the current address to be written.
When reading the data to be written in the chip storage area, the read-write management module is specifically configured to:
acquiring a target address of data to be read;
dividing a target address of data to be read into a plurality of addresses to be read according to a page alignment mode;
and sequentially judging whether each address to be read is a bad page, if so, acquiring a new page corresponding to the address to be read, and reading data from the address of the new page, otherwise, reading data from the current address to be read, wherein the bad pages all correspond to the new page.
The record writing times in the read-write management module are far less than the service life of the chip, and the problem that the erasing times are over-limited when the record is written in the read-write management module is not required to be considered. When applying for a new FLASH space, the available space dynamic management module records all the pages which can be normally used, so that the allocation is carried out according to the normal operation.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method for dynamically enhancing FLASH erasing times is used for realizing FLASH data writing and reading operations applied in an intelligent card, and is characterized in that:
the FLASH data writing operation comprises the following steps:
acquiring data to be written and a target address of the data to be written;
dividing a target address of data to be written into a plurality of addresses to be written according to a page alignment mode, dividing the data to be written into a plurality of data blocks to be written, and enabling the addresses to be written of the target address to correspond to the data blocks to be written of the data to be written;
sequentially judging whether each address to be written is a bad page, if so, acquiring a new page corresponding to the current address to be written, and writing a data block to be written corresponding to the current address to be written into the address of the new page; if not, writing the corresponding data block to be written in the current address to be written;
the FLASH data reading operation comprises the following steps:
acquiring a target address of data to be read;
dividing a target address of data to be read into a plurality of addresses to be read according to a page alignment mode;
and sequentially judging whether each address to be read is a bad page, if so, acquiring a new page corresponding to the address to be read, and reading data from the address of the new page, otherwise, reading data from the current address to be read, wherein the bad pages all correspond to the new page.
2. The method for dynamically enhancing FLASH erase times of claim 1, wherein:
in the multiple addresses to be written of the target address of the data to be written, except for the 1 st address to be written and the last 1 address to be written, the lengths of other addresses to be written are the length of one unit page;
in the multiple addresses to be read of the data to be read, except for the 1 st address to be read and the last 1 address to be read, the lengths of the other addresses to be read are the length of one unit page.
3. The method for dynamically enhancing FLASH erase times of claim 2, wherein:
for the length of the 1 st address to be written, the calculation formula is as follows:
LEN1＝PAGESIZE-(ADDR&～PAGESIZE)
therein, LEN1Indicating the length of the 1 st address to be written, and if LEN1Is 0, then the LEN is corrected1PAGESIZE, where PAGESIZE represents the length of a unit page, and ADDR represents the start address of the target address of the data to be written;
and for the length of the last 1 address to be written, subtracting the sum of the lengths of all addresses to be written except the last 1 address to be written from the total length of the target address of the data to be written.
4. The method for dynamically enhancing FLASH erase times of claim 1, wherein:
judging whether the address to be written is a bad page, specifically: judging whether the requirements are met
EADDRm≤ADDRiAnd ADDRi≤EADDRm+PAGESIZE
If yes, the current address to be written is a bad page, if not, the current address to be written is not a bad page, wherein the EADDRmIndicating the starting address, ADDR, of a bad pageiAnd the starting address of the ith address to be written is shown, and i is a positive integer.
5. The method for dynamically enhancing FLASH erasing times as claimed in claim 4, wherein the solving formula of the starting address of the new page corresponding to the address to be written is as follows:
NADDRi＝NADDRm+ADDRi&(～PAGESIZE)
wherein, the NADDRiIndicating the starting address of the new page, NADDRmDenotes EADDRmCorresponding to the starting address of the new page.
6. The method for dynamically enhancing FLASH erase times of claim 1, wherein:
when the data block to be written is written into the address of the new page, if the writing fails, acquiring the new page, writing the data block to be written into the newly acquired address of the new page, and recording the new page corresponding to the address to be written corresponding to the current data block to be written as the newly acquired new page;
when the data block to be written is written into the address to be written, if the writing fails, a new page is obtained, the data block to be written is written into the newly obtained address of the new page, and the address to be written corresponding to the current data block to be written is recorded to be corresponding to the obtained new page.
7. The method of claim 1, further comprising a reclaim FLASH space operation, wherein the reclaim FLASH space operation comprises:
acquiring a target address to be recovered and the length of data to be recovered;
and judging whether the FLASH space to be recovered has a bad page or not based on the target address to be recovered, if so, deleting the bad page in the FLASH space to be recovered, marking the rest FLASH space to be recovered as an available FLASH space, and otherwise, marking the FLASH space to be recovered as the available FLASH space.
8. A system for dynamically enhancing FLASH erase counts, for implementing the method of claim 1, comprising:
the read-write management module is used for writing data to be written into the chip storage area and reading the data to be read from the chip storage area when the application calls the platform layer to perform read-write operation of the FLASH data;
the bad page management module is used for recording a new page corresponding to a bad page in the chip storage area;
and the available space dynamic management module is used for recovering the FLASH space and eliminating bad pages when the FLASH space is recovered.
9. The system for dynamically enhancing FLASH erasing times according to claim 8, wherein when writing data to be written in the chip storage area, the read-write management module is specifically configured to:
acquiring data to be written and a target address of the data to be written;
dividing a target address of data to be written into a plurality of addresses to be written according to a page alignment mode, dividing the data to be written into a plurality of data blocks to be written, and enabling the addresses to be written of the target address to correspond to the data blocks to be written of the data to be written;
sequentially judging whether each address to be written is a bad page, if so, acquiring a new page corresponding to the current address to be written, and writing a data block to be written corresponding to the current address to be written into the address of the new page; and if not, writing the corresponding data block to be written in the current address to be written.
10. The system for dynamically enhancing FLASH erasing times according to claim 8, wherein when reading data to be written in the chip storage area, the read-write management module is specifically configured to:
acquiring a target address of data to be read;
dividing a target address of data to be read into a plurality of addresses to be read according to a page alignment mode;
and sequentially judging whether each address to be read is a bad page, if so, acquiring a new page corresponding to the address to be read, and reading data from the address of the new page, otherwise, reading data from the current address to be read, wherein the bad pages all correspond to the new page.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101441552A (en) * 2007-11-19 2009-05-27 深圳市朗科科技股份有限公司 Flash memory medium bad block processing method
CN103577121A (en) * 2013-11-05 2014-02-12 中船重工（武汉）凌久电子有限责任公司 High-reliability linear file access method based on nand flash
CN103823640A (en) * 2014-03-03 2014-05-28 山西科泰微技术有限公司 High-efficiency storage method of Flash storage
US20140372838A1 (en) * 2012-05-09 2014-12-18 Tencent Technology (Shenzhen) Company Limited Bad disk block self-detection method and apparatus, and computer storage medium
CN104536847A (en) * 2014-12-18 2015-04-22 飞天诚信科技股份有限公司 Method for improving data writing integrity
CN105975209A (en) * 2016-04-26 2016-09-28 浪潮(北京)电子信息产业有限公司 Multichannel data write-in method and system
US20180349041A1 (en) * 2017-05-31 2018-12-06 Alibaba Group Holding Limited Method and system for implementing byte-alterable write cache
US20190304562A1 (en) * 2018-04-03 2019-10-03 SK Hynix Inc. Memory system and method for bad block management

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101441552A (en) * 2007-11-19 2009-05-27 深圳市朗科科技股份有限公司 Flash memory medium bad block processing method
US20140372838A1 (en) * 2012-05-09 2014-12-18 Tencent Technology (Shenzhen) Company Limited Bad disk block self-detection method and apparatus, and computer storage medium
CN103577121A (en) * 2013-11-05 2014-02-12 中船重工（武汉）凌久电子有限责任公司 High-reliability linear file access method based on nand flash
CN103823640A (en) * 2014-03-03 2014-05-28 山西科泰微技术有限公司 High-efficiency storage method of Flash storage
CN104536847A (en) * 2014-12-18 2015-04-22 飞天诚信科技股份有限公司 Method for improving data writing integrity
CN105975209A (en) * 2016-04-26 2016-09-28 浪潮(北京)电子信息产业有限公司 Multichannel data write-in method and system
US20180349041A1 (en) * 2017-05-31 2018-12-06 Alibaba Group Holding Limited Method and system for implementing byte-alterable write cache
US20190304562A1 (en) * 2018-04-03 2019-10-03 SK Hynix Inc. Memory system and method for bad block management

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
张伟,张太镒,陈志刚,吕娜: "用存储器映射的方法实现片外FLASH的擦写", 半导体技术, no. 07, pages 50 - 52 *

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