CN112154503A

CN112154503A - Low power, high bandwidth, low latency data bus

Info

Publication number: CN112154503A
Application number: CN201980036366.5A
Authority: CN
Inventors: J·K·波尔森
Original assignee: Synaptic
Current assignee: Google LLC
Priority date: 2018-05-31
Filing date: 2019-05-31
Publication date: 2020-12-29
Also published as: JP2023123529A; JP7293257B2; JP2021536151A; WO2019232482A1

Abstract

The data bus includes a device controller coupled to the first interface for digital communication using a first communication protocol, the device controller including a master bus controller to control the multi-drop bus using a second communication protocol, and a slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the device controller using the second communication protocol. Each transmission line end is terminated using a device attached at one end of the transmission line and by another device attached at the other end. The second communication protocol supports multiple data rates using a fixed frame format. Secure synchronization may be established by systematically eliminating all error locations rather than searching for valid candidates. Noise in the audio band may be reduced by scrambling the data using a pseudo-random generator.

Description

Low power, high bandwidth, low latency data bus

Cross Reference to Related Applications

The present application claims priority and benefit from U.S. provisional patent application No.62/678,993 filed on 31/5/2018 and U.S. provisional patent application No.62/721,412 filed on 22/8/2018; each of these patent applications is incorporated herein by reference in its entirety.

This application is a continuation-in-part of U.S. patent application No.16/125,617 filed on 7.9.2018, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to data communication, and more particularly, for example, to systems and methods for communicating digital data between devices.

Background

Various interfaces for transmitting and receiving digital data between electronic devices are known in the art. However, existing interfaces do not meet all of the needs of many modern systems. It is generally desirable to enable high bandwidth communications for a variety of connected devices while maintaining reliability and good signal quality and meeting the needs of low cost, low power devices. For example, Adaptive Noise Cancellation (ANC) headsets may require complex and expensive equipment, and high bandwidth communication between the ANC headset and the host device may be desirable for certain applications, such as processing noise cancellation signals on the host device.

In some approaches, high bandwidth communications are achieved through a digital communications link that is terminated at the receiver. These approaches may provide satisfactory signal integrity for certain configurations, but static power consumption in the receiver terminal may be undesirable if there is a concurrent requirement for low power consumption. Furthermore, many of these approaches are not optimized for low latency data transmission, as data communication may take a complete sampling period to be transmitted over a digital communication link. Some systems typically have additional requirements such as supporting connections to multiple devices and supporting physical links that meet certain length requirements (e.g., 1-2 meters). Additional requirements may include communication, support and flexibility between connected devices to conform to different device types, and support for various data transfer implementations, including bulk data transfers in systems in which data is transported in a serialized format.

In view of the foregoing, there is a continuing need in the art for improved digital data communication systems and methods.

Disclosure of Invention

The present disclosure provides systems and methods that address the need in the art for improved digital data communication between physically connected devices. In various embodiments, a data bus system and method includes a device controller coupled to a first interface for digital audio data communication according to a first communication protocol. The device controller comprises a master bus controller for controlling a multi-drop bus according to a second communication protocol. A first slave device is coupled to the multi-drop bus and is configured to transmit and receive digital audio data communications with the device controller according to a second communication protocol. Each transmission line is terminated with a device attached at one end of the transmission line and by another device attached at the other end, and reflections due to impedance mismatches through inclusion of an intermediate signaling node are controlled to allow multi-drop device support and high speed signaling. The second communication protocol may use a fixed frame format to support multiple audio data rates.

In some embodiments, the first slave device and the second slave device connected to the bus are timed such that the transmitted messages are sent as a sequence of forward traveling waves or backward traveling waves, thereby enabling multi-branch high speed bidirectional communication using the terminated transmission lines. In one embodiment, differential signaling is used for communication and one line is terminated at logic high and one line is terminated at logic low to reduce common mode interference. In one embodiment, differential signaling is used to reduce EMI and when data is not being transmitted, the termination of each transmission line is handled by setting the output driver to one of a high level and a low level according to the termination level and the bus is idle, thereby enabling lower power consumption by the transmission endpoints.

In some embodiments, the intermediate node on the transmission line is connected to the transmission line with a short break to the traveling wave, and the stub and/or break of the transmission line is required to be significantly shorter than the shortest wavelength used for signaling (e.g., 1/50 which is less than the shortest wavelength). Power consumption can be reduced by using a signaling rate that is greater than the minimum required signaling rate and idling the bus for a portion of each clock cycle or each frame, thereby reducing power consumption in the terminal as long as the output terminal level is equal to the final output state level (idle level). The power required for signaling can be obtained by a capacitive or inductive buck regulator, thereby minimizing power loss in the regulator. By reducing the transmission voltage on the bus, power consumption can be further limited and differential signaling can be employed to achieve low voltage signaling while the system is robust to external noise and EMI.

In some embodiments, the delay between components is measured by charging the bus to a known value, disabling the driver at the beginning and end of the transmission line to ensure that the bus is floating and unterminated during the measurement, waiting for the device to change the level on the bus and measuring the transition delay. The drivers at each end of the transmission line may be disabled during the counting (enumeration) of the components attached to the bus by allowing multiple drivers to change the current bus state. The current bus state may be set by the controller and one or more devices may change the transmission line to the opposite value within a given time window that allows the devices to count. The device controller may also include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL) that provides a first clock signal for synchronizing communications according to a first communication protocol, a second clock signal for synchronizing communications according to a second communication protocol, and a third clock signal for use in audio data processing.

In various embodiments, the second communication protocol supports different communication bandwidths that use a fixed frame structure. In some embodiments, the data port or data following each synchronization signal is modulated by a high frequency carrier or pseudo-random generator, thereby reducing current modulation in the audio frequency band for lower interference in the audio system. The device controller, the first slave device, and the second slave device may comprise an audio headset or other audio listening device. In some embodiments, the termination at the end of the transmission line is temporarily disabled during activation of the transmitter to reduce power consumption.

In various embodiments, a method includes using a first slave device coupled to a multi-drop bus, receiving and transmitting digital audio data across a first interface according to a first communication protocol, controlling the multi-drop bus with a device controller according to a second communication protocol, receiving and transmitting digital audio data with the device controller according to the second communication protocol, and setting a transmitter in each end of a transmission line to a known state to enable termination of any signals. In some embodiments, the second communication protocol may support multiple audio data rates using a fixed frame format.

The method may further include using a phase locked loop or a delay locked loop to generate a first clock signal for synchronizing communications according to the first communication protocol, a second clock signal for synchronizing communications according to the second communication protocol, and a third clock signal for use in audio data processing. In some embodiments, the second communication protocol supports different communication bandwidths using a fixed frame structure. Jitter may be added to the PLL or DLL for reducing the emitted EMI by spectral spreading. Data transmitted on the bus may be scrambled at transmission and descrambled at reception to reduce spectral content in the audio band.

The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings which will first be described briefly.

Drawings

FIG. 1A is an exemplary bus interface system in accordance with one or more embodiments.

Fig. 1B and 1C illustrate an exemplary headset in accordance with one or more embodiments.

FIG. 2A is an example of a bus interface system in accordance with one or more embodiments.

Fig. 2B illustrates an exemplary headset in accordance with one or more embodiments.

FIG. 3 illustrates an exemplary timing sequence in accordance with one or more embodiments.

Fig. 4 illustrates an exemplary time-gated phase-locked loop (PLL) in accordance with one or more embodiments.

Fig. 5A and 5B illustrate an exemplary clock solution in accordance with one or more embodiments.

Fig. 6A and 6B illustrate an exemplary clock solution in accordance with one or more embodiments.

FIG. 7 illustrates an exemplary clock solution in accordance with one or more embodiments.

Fig. 8A and 8B illustrate an exemplary clock solution in accordance with one or more embodiments.

FIGS. 9A-F illustrate example frame structures in accordance with one or more embodiments.

Fig. 10A illustrates a method for delay measurement of an attached device in accordance with one or more embodiments.

Fig. 10B illustrates a method for counting of attached devices in accordance with one or more embodiments.

Fig. 11A illustrates an exemplary duplex (duplex) communication arrangement in accordance with one or more embodiments.

Fig. 11B illustrates an example of differential signaling, synchronization, and digital data communication in accordance with one or more embodiments.

Fig. 11C illustrates an example of a differential signaling system in accordance with one or more embodiments.

Fig. 11D illustrates another example of a differential signaling system in accordance with one or more embodiments.

Fig. 12 illustrates an example PLL locking sequence in accordance with one or more embodiments.

Fig. 13 is an exemplary PLL synchronization enabling circuit in accordance with one or more embodiments.

Fig. 14 illustrates exemplary synchronization signaling in accordance with one or more embodiments.

FIG. 15 illustrates exemplary operation of a digital data communication system in accordance with one or more embodiments.

16A, 16B, and 16C illustrate example frame structures that can be used in accordance with one or more embodiments.

FIG. 17 illustrates an example frame in accordance with one or more embodiments.

18A, 18B, and 18C illustrate example frame configurations for read and write operations (including bulk transfers) in accordance with one or more embodiments.

FIG. 19 illustrates an example frame synchronization algorithm in accordance with one or more embodiments.

The included drawings are for illustrative purposes and are only intended to provide examples of possible systems and methods for providing the disclosed methods and systems for context-aware audio processing. These drawings are not intended to limit in any way any changes in form and detail that may be made to those disclosed by one skilled in the art without departing from the spirit and scope of the present disclosure.

Detailed Description

The present disclosure addresses a need in the art for improved digital data communication between electronic devices. In various embodiments, systems and methods are disclosed for providing low power, high bandwidth, multi-drop, and/or low latency communication between a master device and one or more slave devices connected by a physical data link. The present disclosure provides a number of advantages over conventional systems and methods, including lower power consumption, a combination of high bandwidth and long link length, low and well controlled latency, support for multi-drop topologies other than point-to-point connections, and simple synchronization between devices.

In various embodiments, even for a terminated device, low power is obtained by a process that includes sending bits quickly and then idling the bus for the remainder of the clock cycle or the remainder of the duration of the frame. Differential data buses terminated with opposite polarities facilitate low power operation and reduced electromagnetic interference (EMI). The present disclosure also facilitates low power consumption in configurations with unterminated terminals, where a high frequency clock or timing element is used to ensure that data can be received in one or more time units, thereby enabling selection between high signal-to-noise ratio (SNR) and high data rate without changing the physical system, e.g., multiple time slots can be used to define each symbol to enable a tradeoff between bandwidth and signal integrity.

The present disclosure also provides a multi-drop differential long length bus with multiple devices that use a side transmitter as the actual termination and opposite termination polarities to ensure reduced common signaling for low EMI. Algorithms for synchronization of connected devices include finding time slots that do not change according to the desired pattern and systematically eliminating all invalid locations for secure synchronization. In this way, certain implementations of the system may guarantee secure synchronization even with arbitrary random data. When a single synchronization candidate is left, the search will be completed first, and thus, any random data will not cause a false synchronization. Algorithms for bulk data transfer are also provided to facilitate transfers between memory modules independent of bus traffic. In some embodiments, lower EMI is achieved by adding jitter to the system clock. Interference in the audio band may be reduced by scrambling the data symbols prior to transmission and descrambling the values after reception (to obtain the original values). These and other features and advantages of the present disclosure will be understood with reference to the following disclosure.

Various embodiments are disclosed herein. In one embodiment, a system comprises: a master device coupled to a multi-drop bus for digital communication using a communication protocol comprising a plurality of time slots; and a first slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the master device according to a communication protocol. At least one of the time slots is used to define a communication configuration for the first slave device to dynamically optimize bandwidth and/or signal integrity. The multi-drop bus is a differential data bus that is terminated on two lines at different voltage levels, thereby facilitating low power operation and low electromagnetic interference. In one aspect, the multi-drop bus is a multi-drop differential long length bus configured to receive a plurality of slave devices using a side transmitter. Power consumption is reduced by operating at a signaling rate greater than the required signaling rate and leaving the multi-drop bus free for a portion of each cycle.

In one embodiment, the system is further configured to synchronize two or more connected devices, including identifying time slots that do not change according to a desired fixed pattern, and eliminating invalid locations for secure synchronization. The system is also configured to facilitate bulk data transfer independent of multi-drop bus digital communication traffic. In another aspect, a first slave device and a second slave device connected to a bus are timed such that transmitted messages are sent as a sequence of forward or backward traveling waves, thereby enabling multi-branch high-speed bidirectional communication using a terminated transmission line. An intermediate node on the multi-drop bus is connected to the multi-drop bus with a short interruption to the travelling wave, and the physical length of the interruption to the transmission line generated by the intermediate node is shorter than the shortest wavelength used for signaling.

In some embodiments, the delay between devices is measured by: charging the bus to a known value, disabling drivers at the beginning and end of the bus so that the bus floats and is not terminated during a measurement, waiting for a device to change the level on the bus, and measuring transition delays. A PLL or DLL is used to obtain a lock between the master device and the first slave device. The system timing is obtained from a fractional PLL provided in the master device and/or the first slave device, and the PLL is dithered by adding an output from the pseudo-random generator to the fractional adder, thereby reducing EMI. In one embodiment, the pseudo-random generator is configured to scramble the output of one or more data ports, thereby enabling lower EMI by whitening (whiten) the output spectrum. The PLL and/or DLL may include time gates that are enabled during initial lock of the PLL and only later allow synchronization information to pass to avoid the PLL locking onto random bus traffic.

In various embodiments, a method comprises: providing a master device coupled to a multi-drop bus for digital communication using a communication protocol comprising a plurality of time slots; coupling a first slave device to the multi-drop bus and configuring the slave device to transmit and receive digital communications with the master device according to a communication protocol; and defining a communication configuration for the first slave device using at least one of the time slots to dynamically optimize bandwidth and/or signal integrity. The method may further include operating the multi-drop data bus as a differential data bus terminated with opposite polarities, thereby facilitating low power operation and low electromagnetic interference, and/or synchronizing two or more connected devices, including identifying time slots that do not change according to a desired fixed pattern, and eliminating invalid locations for secure synchronization. In some embodiments of the method, the first slave device and the second slave device connected to the bus are timed such that the transmitted messages are sent as a sequence of forward traveling waves or backward traveling waves, thereby enabling multi-branch high-speed bidirectional communication using the terminated transmission line.

Referring to fig. 1A, an exemplary audio system 100 will be described in accordance with one or more embodiments of the present disclosure. System 100 includes a host device 110 and at least one connected device 130. Host device 110 may be any electronic device configured to send or receive audio data to or from connected device 130, including, for example, a smartphone, tablet, laptop, automobile voice interface, voice conference system, audio playback system, or other electronic device. Connected device 130 may include one or more electronic devices configured to transmit, receive, and/or process audio data, and may include, for example, one or more microphones, speakers, or audio processing systems. While the present embodiments are discussed with reference to audio communications, it should be understood that the systems and methods described herein may be implemented with other electronic devices and data types in accordance with the present disclosure.

In the illustrated embodiment, host device 110 includes an application processor 112, an audio CODEC 114, and an interface component 116. The application processor 112 controls digital audio data communication between the host device 110 and the connected device 130. The audio CODEC 114 provides audio input and/or output processing according to the requirements of the host device 110. Interface component 116 facilitates a physical connection between host device 110 and connected device 130 via cable 120 and a compatible connector. In various embodiments, the interface component 116 may include a port for receiving a connector and a corresponding interface controller for implementing a communication protocol. In the embodiments described herein, Universal Serial Bus (USB) connectors and interfaces are described; however, it should be understood that other cables, connectors, and protocols may be used in accordance with embodiments described herein.

In one or more embodiments, the application processor 112 facilitates communication between the host device 110 and the connected device 130 using a multi-wire bus protocol that includes clock and data lines, such as those defined by the SoundWire specification or the USB specification. The application processor 112 may communicate with the audio CODEC 114 in a master-slave relationship using an audio interface, such as SoundWire or another digital interface. The audio CODEC 114 facilitates communication between the application processor 112 and the interface component 116, thereby converting audio data between the two interface protocols. Audio data is transmitted between the interface component 116 and the device controller 140, the device controller 140 being configured to handle data transmission across the cable 120. The device controller 140 is further adapted to operate as a master device for communicating with one or more slave devices (such as an audio component 142 and an audio component 144) across an interface bus of the connected device 130, and to facilitate other device functions, such as processing user inputs through a user interface component 146. In one embodiment, the bus lines include a power bus (VBUS), differential pairs D + and D-for data transfer, ground, and device ID. Those skilled in the art will appreciate that other bus line configurations may be used in accordance with the teachings of the present disclosure. Communication between the various devices and components of system 100 may be facilitated in accordance with the digital data communication systems and methods disclosed herein.

Referring to fig. 1B, the exemplary connected device 130 of fig. 1A may be implemented as a USB headset 150 that includes a USB connector 152 for connecting to the interface component 116 of the host device 110, a device controller housed in the connector 152, a user interface 157 (such as buttons), and a wired data 158 bus that connects the device controller 152 with the

audio components

160 and 170. In one embodiment, headset 150 is an Adaptive Noise Cancellation (ANC) headset. Referring to fig. 1C, an exemplary embodiment of

audio components

160 and 170 for use in an ANC headset is illustrated. The audio component 160/170 is implemented as a slave device on the data bus 158 of the headset 150. Each of the audio components 160/170 includes an audio output circuit 182 for receiving audio data from the slave component and driving one or more speakers 186 to play the audio data for the user, and an audio input circuit 180 for receiving sensor data from one or more microphones 184, digitizing the received data, and providing the digitized audio data to a slave (slave) for transmission across the data bus 158 to a master (master).

Another embodiment of a connected device is illustrated in fig. 2A. Connected device 230 includes connector 216, cable 220, device controller 240, user interface 246, and

audio components

242 and 244. The connector 216 is adapted to couple with an interface component of a host device, such as interface component 116 of fig. 1A. The cable 220 couples the connector 216 to a device controller 240, the device controller 240 providing an interface between a communication protocol for communicating with a host device and a bus protocol of the connected device 230. The device controller 240 serves as the master of a communication bus that couples one or more slave devices, such as an audio component 242 and an audio component 244. The user interface 246 is coupled to the device controller 240 to provide user control (such as volume control or muting on a set of headphones).

Referring to fig. 2B, the exemplary connected device 230 of fig. 2A may be implemented as a USB headset 250 (e.g., a USB headset) that includes a USB connector 252 for connecting to the interface component 116 of the host device 110, a USB cable 254, a device controller 256, a user interface 257 (such as buttons), and a wired data bus 258 that connects the

audio components

260 and 270 to the device controller 256.

The system and method of the present disclosure supports long wired links, low power implementations, and high bandwidth communications. In various embodiments, a low duty cycle is used for the signal, which reduces the static power consumption associated with the terminated link. In various aspects of the disclosure, a low duty cycle is achieved on a per symbol basis (e.g., by using short symbols) and/or by transmitting data packets quickly and then leaving the bus idle for a short period of time. One advantage of these methods is that low latency links are supported because data packets can be transmitted quickly, after which the bus goes idle and consumes little or no power. In one or more embodiments, higher data rates are supported by incorporating an internal Phase Locked Loop (PLL) or DLL (delay locked loop) in each receiving device to generate a higher speed internal clock based on periodically transmitted synchronization symbols. One advantage of using a symbol with a low duty cycle is that it allows low power consumption at moderate transmission rates, since the static power consumption due to the use of the terminated link is reduced due to the low duty cycle. In other words, a high-bit-rate link that can use a terminated transmission line can be utilized to obtain low power consumption for medium to low speed signaling because the power consumption of the various embodiments disclosed herein scales linearly with the bandwidth used (since the power consumption of the PLL receiving the data for reception will be constant, but can be made a fraction of the total power budget). Thus, the data link implementations disclosed herein can have low power consumption when waiting to low bandwidth in use, and still be able to transmit large amounts of data with slightly higher power consumption. In both cases, the PLL clock frequency or DLL delay may be constant or vary according to system needs.

The present disclosure also supports a multi-drop bus topology by providing control at the intermediate nodes, thereby allowing high quality signals to be obtained even when there is an impedance mismatch at the intermediate nodes that would result in poor signal integrity in conventional systems. In many conventional systems this is addressed by avoiding termination at the end of the transmission line rather than slew-rate of the control signal, however, this results in a slower system due to the limitation of maximum slew rate that may avoid reflections. The various systems and methods disclosed herein are not plagued by such limitations.

Embodiments disclosed herein provide a robust and reliable data link with minimal degradation of signal integrity. In some embodiments, the transmitter may disable its own parallel termination resistor when transmitting to further reduce power consumption. In some embodiments, the transmitters at each end of the bus transmission line may provide termination by setting the output level to a static value when not transmitting. By setting this voltage level to the static idle value of the system and matching the series output impedance to the bus impedance (i.e., the output transmitter at each end acts as a termination when it is not transmitting), low power consumption (e.g., no power consumption other than the running of the internal clock, etc.) will be achieved when there is no data to transmit). In conventional systems, a change in impedance in the transmission line will result in a reflection in the transmitted signal. This fact has led conventional systems to comply with design constraints based on the concept that multiple components cannot be easily placed on intermediate nodes on a transmission line without significantly distorting the transmitted signal.

However, in the present disclosure, it should be recognized that if the change in impedance occurs over a relatively short distance compared to the shortest wavelength involved, there will be little signal interference and a practical system may be realized. As an example, an experimental system using a 50 ohm transmission line includes a plurality of intermediate nodes, each involving a stub (1-2 cm in length), and this results in a change in slew rate from 4.7 ns to 4.8 ns (or an increase of about 100 ps) and an amplitude reduction of about 6% for each node. Therefore, even if the slew rate is slightly increased and the amplitude is slightly decreased, the change of the signal is minimal, a good eye diagram is obtained, and robust data transmission is achieved. Thus, even though conventional theory has led to systems requiring prevention of any change in impedance along the transmission line to avoid reflections, these reflections can be controlled to have such small amplitudes as to be detrimental to the actual functioning system, as long as the length of these disturbances is much shorter than the wavelength of the fastest signal concerned.

The experimental system has a 2 cm stub length, which is equal to a transit time in air of less than 0.1 ns, or much shorter than the rise time (5 ns). In this case, the factor between the rise time and the delay through the stub is greater than 50, and causes minimal delay and interference in the system. If the delay is already 5 ns (equivalent to 150 cm of cable without shielding), the system rise time and delay in the system will be comparable and the cable will appear to be expandable (open-ended). Thus, dimensioned as disclosed herein, one or more systems of the present disclosure will allow for the transmission of very fast signals that are properly terminated at the ends of the transmission lines, and at the same time allow for multiple components to reside on the same transmission line, thereby solving the problem of obtaining a multi-drop bus system that still allows for high transmission speeds. Furthermore, by timing the sequencing of the transmission of the signals so that the forward or backward wave is controlled, it is possible to avoid problems with active transmitters residing on intermediate nodes on the transmission line that interfere with the traveling wave.

An example of a timing sequence showing information traveling between a master device and 3 slave devices in accordance with one or more embodiments will now be described with reference to fig. 3. By optimizing the timing with respect to the direction of data transmission, a higher bandwidth can be obtained. In various embodiments, all packets will disappear once they reach the end of the line where they are absorbed. Assume that the master M1 is located at the end of a transmission line with multiple slaves (S1, S2, and S3) located on the same transmission line, where the slaves are labeled with the numbers one, two, three, etc., because each slave is farther away from the master.

When transmitting a autonomous forward traveling wave, the master M1 first transmits a message (time a), immediately follows the slave S1 when the forward wave has just passed the slave S1 (time C), and then the slave S2 transmits its forward traveling wave message when the end of the message from the slave S1 has completed (time E). When the message from the slave device S2 has been completed, the slave device S3 transmits a forward traveling wave message. When all forward traveling wave messages have been completed and absorbed by the terminal at the other end of the transmission line, the last device residing on the transmission line (e.g., slave device S3 at time F) begins transmitting a backward traveling wave toward the master M1. The backward traveling wave follows the transmission of the backward traveling wave from the second device to the last device (e.g., slave device S2 at time G) residing on the transmission line, just after the message from the last device has passed, and so on. When all backward traveling wave messages have been completed and absorbed by the terminal at the master device, the master M1 will again begin transmitting messages using the forward traveling wave as previously described.

In some embodiments, two devices may transmit messages simultaneously if the devices are located at opposite ends of a transmission line and the effect of their own transmitted waves is subtracted from the measured waves (superposition of forward and backward traveling waves). In some embodiments, this may also be performed even with devices located on the middle point of the transmission line, however, in some embodiments, devices located on the middle point should not generally transmit while receiving, as this may result in reflections of forward or backward traveling waves.

In various embodiments, a communication bus for use with an audio device, such as an audio headset, includes a multi-drop bus that enables high bandwidth and low power consumption using signaling of differential impedance matching. The bus has a high control and audio bandwidth and supports links up to more than 10 meters. In one or more embodiments, the total bus link length is two meters or less. Referring to FIG. 1A, the link length is two terminal endpoints Z_ENDAnd includes the length of the cable 120 from the device controller 140, which may be integrated into the connector, to the user interface component 146 (length a), the length of the wire from the user interface component 146 to the intermediate node (length B1 and length B2), and from the intermediate nodeThe length of the wire from the node to the terminal end (length C1 and length C2). In one embodiment, the link has a total length from 0-200 cm from the terminal end point, including the following ranges: length A, 0-80 cm; length B, 0-60 cm; and a length C of 0-60 cm. In one embodiment, stubs B2 and C2 should be kept as short as possible to minimize the impact on signal integrity.

Referring to FIG. 2A, in one embodiment, the length of the USB cable is from 0-200 cm, and the link length between each terminal endpoint and the device controller 240 is from 0-100 cm, respectively. In the illustrated embodiment, the link between the terminal end of the headset and the farthest speaker or microphone is less than 200 cm, although other distances may be used.

In various embodiments, the link supports standard clock rates, such as 12.288 MHz and 19.200 MHz, thereby providing compatibility with standard telecommunications and audio systems. In one embodiment, a 10 meter link distance is supported in the 12.288 MHz mode of operation by increasing the turnaround delay when switching the signaling direction.

In various embodiments, it is desirable that the locking range of the PLL be narrow and maintain a constant number of bits between each synchronization symbol. Furthermore, in various embodiments, it is desirable to maintain 48kHz compatibility with multiple clock systems. The present disclosure provides for initial synchronization between the slave and master devices that is simple and robust, and in various embodiments, uses a constant frame size. The use of a constant frame size is in contrast to SoundWire and similar protocols, which enable multiple frame sizes to ensure compatibility with multiple clock systems. In one or more embodiments, one or more beacon bits are represented within a frame to maintain synchronization between multiple sources (such as multiple audio ports utilizing different sampling frequencies).

In the following, an exemplary mode of operation according to one or more embodiments of the present disclosure is illustrated in the table:

the systems and methods disclosed herein provide additional advantages including energy efficient design, address some of the problems with sync symbol interference frame size, including an efficient bandwidth utilization scheme by merging sync columns with commands, having a simple clocking scheme, enabling fine tuning of delay for optimal signal integrity using a single clock source, supporting 12.288, 19.200, and 12.000 MHz systems, requiring no wideband PLL tracking (i.e., the PLL only needs to support a relatively narrow lock range), constant frame size can be used with varying data formats to support multiple clocking systems, and using microstepping of sample intervals to accurately measure slave delay for optimizing the eye diagram when receiving data. In various embodiments, a multi-drop bus may be used for multiple clock systems, such as telecommunications, USB, and audio modes of operation, for example, while maintaining a constant frame length. In some cases, a lower synchronization frequency, such as 768 kHz, may be used for a longer bus diameter.

The synchronization symbol may be combined with the signaling of the command by careful timing of the slave delay so that a slot after the master has completed the synchronization symbol (typically a 0-1 transition) may be used to signal the command or allow multiple devices to respond within the same slot by leaving the slot undriven and allowing the devices to change the current level, but not driving the current level (similar to wired or (wired-or) configurations).

Clock support

As previously discussed, one problem encountered with conventional bus topologies relates to the support of different clock frequencies, including multipliers or dividers needed to obtain a desired base frequency. As an example, 48kHz may be obtained by dividing 19.200 MHz by 400 (4 x5x 5) or 12.288 MHz by 256 (4 x4x 4). In various embodiments disclosed herein, the commands transmitted on the bus do not interfere with the audio stream. In one embodiment, the commands are issued at the same pace (or a sub-multiple thereof) as the audio data. In some embodiments, there is a constraint of PLL or DLL clock synchronization to embed the clock in the data lines and thereby save wiring and power consumption. By using differential signaling, electromagnetic interference (EMI) may be restricted.

In one embodiment, a solution is provided that includes adding extra bits to give room for synchronization and commands within a communication frame. The system can support various clock frequencies and can optimize the frame structure with respect to constrained bandwidth utilization for a given long bus diameter. The structure of this embodiment is deterministic and simple to decode and does not require complex analog circuitry to determine the exact clock frequency, e.g. the number of clock pulses between each synchronization symbol frame remains constant.

Existing systems (such as SoundWire) contain multiple defined frame formats-e.g., 8 column sizes and 19 possible row values for a total of 152 combinations. One challenge is to design a system that supports both 12.288 MHz and 19.200 MHz operation because each has a different multiplier (19200/48 = 400 and 12288/48 = 256) without the need for a special analog system. In various embodiments described herein, a single frame size may be used that allows support of both 12.288 MHz and 19.200 MHz and even 12.000 MHz systems.

The PLL and clock solutions disclosed herein address various problems associated with conventional systems. When there is an unterminated transmission line, there are reflections that may interfere with signal quality. One solution is to slow down the data transfer. However, for many systems, high speed transmission is desired, and therefore, it is preferable to terminate the wires for eliminating unwanted reflections. By using a high clock speed and a low duty cycle (either for each symbol or as free space at the end of each cycle/line) for the data, it is possible to reduce the static power consumption per transmitted bit and thus achieve lower power consumption for medium speed links.

When there are only two devices, the synchronization between the devices is simplified because there is no cross traffic. Furthermore, such a system may not require a termination at each end, as the two devices do not experience any half voltage when the devices are located at the ends of the transmission line. In the case of multiple devices, there is a possibility that the slave will lose the lock on the master. One solution is to restart the bus, but this is undesirable for many implementations because the system will lose audio for a period of time. Various embodiments of the present disclosure address the problem of slave devices that lose synchronization while other devices on the bus continue to operate by resolving clock synchronization.

Referring to fig. 4, an exemplary phase-locked loop (PLL) 300 will now be described, which may be included in the device controller 140 of fig. 1A and the device controller 240 of fig. 2A, as well as the

slave devices

142 and 144 of fig. 1A and the

slave devices

242 and 244 of fig. 2A. PLL 300 allows the circuit to remain locked even in the presence of signals from multiple slaves, which are time-multiplexed with the master synchronization signal.

The PLL 300 (or DLL) generates an output clock signal having a phase and frequency relative to the phase and frequency of an input reference clock. During operation, a reference clock signal passing through the time gate 302 and a feedback signal from the divider 310 are input into the phase detector 304. The phase detector 304 compares the phases and frequencies of the input reference clock signal and the feedback signal, and outputs a control signal to adjust the feedback signal accordingly to have a phase and frequency that is synchronized with the phase and frequency of the reference clock signal. Phase detector 304 aligns the phases of the rising (or falling) edges of the reference clock signal and the feedback signal. The output of the phase detector 304 is provided to a loop filter 306 to adjust the voltage and frequency of a Voltage Controlled Oscillator (VCO) 308. The signal output from VCO 308 passes through divider 310 to generate the feedback signal. The output clock signal is provided to various system components as described herein. In the illustrated embodiment, the divider is configured as a multiple of a frame size of 144 bits, but other integer values may be selected (e.g., M = 16, M = 42, M = 48, or M = 80). Either 4 slots are given directly using M = 4 or 8 slots are given using two phases of the clock for data capture of the bus signal. Using M = 8 gives directly 8 slots or two phases gives 16 slots, which provides a simple solution with high resolution.

In various embodiments, the time gate 302 is enabled at all times during initial startup, after which the time gate 302 is enabled only during receipt of the reference synchronization pulse from the master. This enables the circuit to be locked to the master even if multiple slaves are also signaling on the bus and these slaves are offset in time from the master. Furthermore, if the PLL/DLL loses lock with the master sync, the device will disable the output driver to avoid bus collision and re-enable the wide search for sync pulses. In some embodiments, the phase detector may be eliminated altogether by using a time gate as the phase detector (e.g., by using a sufficiently narrow time window). This can be used to reduce timing jitter (the time gate will still be controlled by the output from the VCO through the divider). In some embodiments, the phase detector will be of the phase-frequency type, so it is sensitive to both frequency and phase differences (type III-IV phase detector), thereby ensuring a secure initial acquisition of the correct state.

An exemplary clock division solution for use with embodiments of the present disclosure will now be described. In one embodiment illustrated in fig. 5A and 5B, the clocking solution is an implementation of a Frequency Locked Loop (FLL) 400 that generates three synchronous clock signals, an audio clock 402 for audio input and output processing, a USB clock 404 for USB communication between the host device and the connected device, and a data bus and DSP clock 406 for use in the low latency data bus of the present disclosure. The synchronization pulses present in the USB protocol may be used as a timing reference.

In the illustrated embodiment, the sync detector 410 is coupled to an input of the FLL 400. The sync detector 410 determines whether the clock signal is synchronized to the system clock (USB clock reference) to allow proper bus communication. If the synchronization symbols are not synchronized (positive out of sync), synchronization detector 410 will cause FLL 400 to modify the clock period to bring it into synchronization with the master clock. The FLL 400 may be implemented to illustratively include a digital filter and predictor 412, a digital-to-analog converter (DAC) 414, such as a delta-sigma DAC, a Voltage Controlled Oscillator (VCO) 417, a divider 424, a frequency counter 418, and a subtractor block 414 to compare the result to the reference frequency 408. Another aspect of the illustrated embodiment is the use of a reference frequency integer 48384 (see reference 408), which can be used to divide FLL 400 usingA divider 420, a divider 422, and a fractional divider 426 produce the desired divide frequency. An embodiment of a fractional divider 430, which may be used to divide a clock signal by a fractional value, is illustrated in fig. 5B. Fractional divider 430 is implemented using a phase adder 432 and a divider 434, where a particular phase value is added to the phase sum of each clock cycle, and when the current phase sum exceeds some maximum phase value, another phase value is subtracted from the current sum and the output is activated. If a two's complement (two-complement) adder is used, the phase value may be taken to be 2^NOne step size and no subtraction is required due to the automatic wrap-around (wrap-around) that occurs in the complement operation of binary. In some embodiments, the delta-sigma converter may perform integration rather than phase adders, thereby eliminating the trace (spur) resulting from the fractional division. This may be used to reduce the EMI of the output clock signal by spreading the output spectrum.

In the following, exemplary clock solutions for various embodiments of the present disclosure are illustrated in tables. As used herein, the term "EarLink" refers to the audio bus system and method of the present disclosure.

An exemplary embodiment of the second clock solution is illustrated in fig. 6A and 6B. The second clock solution is an implementation of a Frequency Locked Loop (FLL) 500 that generates three synchronized clock signals, an audio clock 502 for audio input and output processing, a USB clock 504 for USB communication between a host device and a connected device, and a data bus and DSP clock 506 for use in the low latency data bus of the present disclosure. FLL 500 includes a sync detector 510, a filter and predictor 512, a delta-sigma DAC 516, a VCO 517, a divider 524, a frequency counter 518, and a subtractor block 514, which may be implemented in a similar manner as the corresponding components of fig. 5A and 5B, except as described herein. The FLL 400 uses divider 520, divider 522, and PLL 540 to generate the desired divided frequency, PLL 540 outputting the frequency at 125/128 of the audio clock frequency. An embodiment of PLL 540 is illustrated in fig. 6B and includes 1/128 reference input from the output of divider 520, phase detector 544, loop filter 546,

VCO

548, and 1/125 divider 550.

An exemplary embodiment of the third clock solution is illustrated in fig. 7. The third clock solution is an implementation of a Frequency Locked Loop (FLL) 600 that generates three synchronized clock signals, an audio clock 602 for audio input and output processing, a USB clock 604 for USB communication between a host device and a connected device, and a data bus and DSP clock 606 for use in the low latency data bus of the present disclosure. The FLL 600 includes a sync detector 610, a filter and predictor 612, a delta-sigma DAC 616, a VCO 617, a divider 624, a frequency counter 618, and a subtractor block 614, which may be implemented in a similar manner to the corresponding components of fig. 5A and 5B and fig. 6, except as described herein. FLL 600 generates the desired crossover frequency using divider 620, divider 622, and PLL 630, with PLL 630 outputting a frequency at 21 times the audio clock frequency.

An exemplary embodiment of a fourth clock solution is illustrated in fig. 8A and 8B. The fourth clock solution is an implementation of a Frequency Locked Loop (FLL) 700 that generates three synchronized clock signals, an audio clock signal 702 at 12.288 MHz for audio input and output processing, a USB clock signal 704 at 12 MHz for USB communication between a host device and a connected device, and a data bus at 258.048 MHz and a DSP clock signal 706 for use in the low latency data bus of the present disclosure. FLL 700 includes a sync detector 710, a filter and predictor 712, a delta-sigma DAC 716, a VCO 717, a divider 724, a frequency counter 718, and a subtractor block 714, which may be implemented in a similar manner as the corresponding components of fig. 5-7, except as described herein. The FLL 700 generates the desired divide frequency using a fractional divider 720, a divider 722, and a fractional divider 730, the fractional divider 730 outputting a frequency of 21 times the audio clock signal 702. An embodiment of a fractional divider 720 is illustrated in fig. 8B, which may be used to generate the data bus and DSP clock signal 706. Fractional divider 720 is implemented using a phase adder 732 and a divider 734, where a particular phase value is added to the phase sum of each clock cycle, and when the current phase sum exceeds some maximum phase value, another phase value is subtracted from the phase sum and the output is activated. In some cases, jitter generator 736 provides jitter for the phase adder to not only divide the clock by a fractional value, but also add a jitter value to the intermediate phase value. This will increase the jitter of the clock but can be used to reduce the EMI of the system clock by controlling the amount of added jitter. Typically, the emitted EMI will be reduced by this action by 15-20 dB. Jitter generator 736 may be implemented using a digital pseudo-random generator or other digital circuitry that generates random numbers. If the pseudo-random generator adds an average to a sequence of phase adders other than zero, this should be taken into account when updating the phase adders.

Frame structure

According to various embodiments of the present disclosure, a single frame structure may be used across multiple supported frequencies. An exemplary frame structure for use with the disclosed embodiments will now be described.

Referring to the embodiment of fig. 9A, the frame structure includes frames having a constant size of 42 bits, in which the synchronization pattern is repeated at a frequency of once per frame. In one embodiment, the number of command bits per message is 32 bits, and the message synchronization bits are repeated every 48 kHz. Each frame may include one or more subframes, e.g., four subframes and each subframe has the same structure and looks the same in terms of synchronization. An exemplary organization of the command bits is illustrated below, where SCMD is the start of the command, S48 is a 48kHz beacon, RES is a reserved field, OP2-OP0 is a three-bit opcode, Dev3-0 is a 4-bit device number, DAT is the data to be transmitted as part of the command, PAR is the parity bits for security, and ACK is the acknowledgement bits:

。

for a time tick (time tick) of every 48kHz or every 64 frames or 256 subframes (for a time tick of every 24 kHz or 512 subframes for a 9.600 MHz system), bit S is equal to one bit at the beginning of the first subframe. The S bit can be used to find the start of a frame and synchronize multiple sound sources to 48kHz (e.g., the start of the first frame should be a sampling event).

Details of the data organization are further illustrated in FIG. 9A. The zero to one transition is used by the PLL in the slave to synchronize the internal timing with the master, followed by the command bits CMD. Next, 16 bits of audio may be transmitted from the master to the slave, followed by one or more time slot delays (to allow for a change in signal direction) during the switch from master to slave (including read, R, command). Next, 16-bit audio may be transmitted from the slave device to the master device, followed by one or more time slot delays.

Embodiments for 9.600 MHz, 12.000 MHz, and 16.000 MHz systems are illustrated in fig. 9B and 9C. These formats will enable the support of telecommunications clocks and may vary the bandwidth utilized between master and slave from about 1/3 to 2/3 of the bandwidth used by the master or by the slave. These formats have the following advantages: the number of bits per row is 10 or slightly more for more efficient transmission at a clock frequency associated with 19.200 MHz. This frequency or 38.40 MHz = 2 x 19.20 MHz is commonly used for use in telecommunication applications such as mobile phones and handheld devices.

Referring to fig. 9D and 9E, additional frame structures will be described. According to various embodiments, there is the same number of bits in each frame between each synchronization pulse. However, the number of bits may be varied, for example, by varying the amount of bandwidth used for the command. The frame structure may also vary in the number of rows and columns and still maintain the same number of bits. For example, both fig. 9D and 9E include the same number of bits per frame. By dividing each frame by a larger number of bits (e.g., 80 or 144 bits), which can be decomposed into various factors, the frame organization can be changed without changing the PLL multiplication factor, at the cost of higher jitter in the receive open eye (eye opening) due to higher bandwidth.

The organization of exemplary message fields is illustrated as follows:

it should be understood that while many commands may be conventional (do nothing, read and write registers), DELAY commands may be used to find the DELAY between devices attached to the transmission line for optimal timing. This can be achieved by the master first charging the line to a certain value, then holding that value with a bus keeper or with a floating bus, after which the master driver is released and after which any device attached to the bus can switch (toggle) that value. Locating the device closest to the master will first affect the switching of the bus lines, which can be reliably measured using a counter clocked at high speed to detect timing events or using a plurality of delay circuits. During the measurement the bus will not be terminated so as not to affect the timing. The measurements may be made internally in the master device (to optimize slave transmission timing) or internally in the slave device (to optimize slave-to-slave communication timing).

Fig. 9F illustrates an exemplary protocol symbol in accordance with various embodiments. Another exemplary command set is further illustrated in the following table:

an embodiment of a "register read operation" will now be described. To perform a register read operation, the following sequence of instructions may be executed: (i) write the correct address value using an address write operation, and (ii) perform a register read operation (the data field will contain the read value). If a range of registers needs to be read, this can be done without updating the address registers between each read operation. This is possible because the address counter can be incremented by one for each read operation.

An embodiment of a "register write operation" will now be described. To perform a register write operation, the following sequence of instructions may be executed: (i) write the correct address value using an address write operation, and (ii) perform a register write operation (the data field will contain the read value). If a range of registers is to be written, this can be done without updating the address registers between each write operation. This is possible because the address counter can be incremented by one for each write operation.

An embodiment of an "address register write operation" will now be described. Register access is controlled by an address register. Before performing a register operation, the value of the address register is first defined. This occurs in conjunction with an address register write operation. The address register points to the currently active register in the slave device being addressed. Subsequent accesses (read or write operations) may increment the address register. This enables faster access to multiple registers. In various embodiments, there is only a single register that controls both read and write operations, and any read or write operation may increment the value of the address register. This incrementing occurs after the value of the address register has been first used once in a read or write operation. The current value of the address register cannot be read back using the command shown in the table.

An embodiment of the "beacon" command will now be described. The command may be sent by a master device having a repetition period of 48 kHz. Which can be used by the slave device to synchronize the audio timing to the beginning of the frame so that all audio sources are synchronized.

An embodiment of the "device loop delay" command will now be described. The command measures the turnaround delay from the slave to the master by measuring the transition initiated by the slave and proceeding to the master. In the present embodiment, a mechanism for measuring two-path delay is provided. An embodiment of a method 800 for delay measurement will now be described with reference to fig. 10A. First, the master sends a command to the device to indicate that delay measurement is to begin (step 802). Next, the terminals are disabled at both ends (step 804), and the transmission line is charged with a known symbol (step 806). In step 808, the known apparatus responds by discharging the transmission line. In step 810, a delay is measured from a charging event to a discharging event. In step 812, if the system includes end terminations, the terminations are enabled at both ends of the transmission line.

In one implementation, the master sends out a device loop delay command followed by the device number to be queried. Next, the master sends out the device ID value in the data field. If the device ID is equal to the data field, the internal flag ("device _ update _ ready") will be set, and if the device ID is not equal to the data field, the internal flag will be reset. Next, the bus is brought to a known state by the master (i.e., the bus is initialized to a known logic value, zero). The master will maintain this state with a weak (weak) bus keeper or using a floating bus, and disable its transmitter after driving the bus to a known state and ensure that the terminations at both ends are disabled during the measurement. As an example, the master may use the 0-1 signal for synchronization and to place the bus in a "1" state.

The slave device may then drive the state to a different value using a strong internal driver internal to the slave device. In one embodiment, the following sequence is output from the device, where Z is the disabled driver, and 0 is driving a low signal-ZZZZ-00-ZZZZZZ-and a double zero will ensure a correct reading of zero under all delay conditions. When the master receiver receives a transition signal from one or more slaves, it will know the delay from the timing. The timing of this event will be used to find the two-way delay to the nearest device and optimize the receiver's eye diagram by controlling the transmit or receive timing delays. The delay value may be measured based on an internal oversampling clock internal to the master device or using a delay line or delay samples internal to the master device. In some cases, where there is a significant amount of noise or clock jitter on the bus, it may be necessary to repeat the procedure multiple times in order to obtain good delay readings. This may also involve reading the return values from multiple time slots and taking them at a fine resolution (e.g., 2 ns) and then averaging multiple read values (e.g., 64). If the return value can occur anywhere from 0-36 ns, we will need a total of 19 values, each accurately determining the delay in all cases based on multiple measurements returned from the slave, and in each case we may have to perform multiple(s) (ii) ((iii))E.g., 64) readings to allow a good average to be returned. By starting the search from the intermediate delay position, it is possible to significantly reduce the search time. Furthermore, it is also possible to reduce the search time by changing the search direction depending on what the last returned value is, as this gives an indication of whether the delay is too long or too short. With the constraint, we will measure about 50% of the zeros and ones from the return right at the transition. In addition to this, we will need to add¹/₂The data time slot to get the best sampling point.

In another implementation, the master may write back the value it has read from the slave and then self-adjust the internal delay for the slave. This can be used to optimize the slave-to-master communication, i.e. to reduce the required bandwidth for the adjustment. Similarly, one slave device can write the value it has read from another slave device and have this other device self-adjust its internal transmit timing.

When the master sets the bus to a known value, the charge left on the bus will be absorbed by the master and thereby clear any previously information transmission lines. If there are multiple slaves, they can be eliminated one at a time using their device IDs (16 bit constants). The slave closest to the master will correspond to the obtained delay value. In other words, during the measurement of device delay or the counting of devices attached to the bus, the first device (typically the master) attached to the transmission line and the last device (typically the slave) attached to the bus will both disable its driver during this procedure to enable the floating bus, which is maintained by the inherent charge inside the transmission line.

In various embodiments, only devices with a digital DEV and a device id equal to or higher than the data field value will activate the output. A binary search can then be used to find the device with the highest address current connected to the bus, which is eliminated from the search by assigning it a different device ID (typically 3 bits to save bandwidth and continue to find the address of the second highest device attached to the bus, etc.). In other words, an arbitration (arbitration) procedure must first be used, so that the MSB of the device ID is read first, and those with a low device IDAll slaves will back off. This procedure will continue until only a single device will respond (note that the procedure is similar to I)²C multi-master and SoundWire address arbitration).

In one embodiment, all devices will shut down normal data traffic in the last row of the frame when the delay command is used to ensure that it will not interfere with the measurement. In some embodiments, the slave device may be programmed to use a particular delay corresponding to a certain geometric configuration, thereby omitting the need to find a physical delay before interacting with the component and omitting the need for other means including non-volatile memory or communicating a delay value to internal circuitry.

Referring to FIG. 10B, a method 850 for counting attached devices that contain an internal device number instead of a device number appropriate for the bus is illustrated. In step 852, the master sends a command to indicate that counting is to begin. In step 854, terminations at both ends are disabled and in step 856, the master continues to charge the transmission line with known symbols. If the bit from the device number is high, the unknown device on the bus responds by discharging the transmission line (step 858). After the known delay, all devices with the lower bits of the device number for this position will abort (step 860). If more than one device is left (step 862), then the next device bit is checked and device arbitration continues in step 864. If only a single device is left, the device is assigned an address in step 866. If the master knows the long IDs of all attached devices in advance (e.g. 16 bits), it can simply address these devices at a time and immediately re-assign a new short ID (3 bits) to each device after booting without performing address arbitration.

An embodiment of the set device address command will now be described. After a power-on reset, the slave device is assigned a device address value of zero. When this command is executed, the addressed device will get a new address (0-7). The notification address 7 (111) is included for broadcasting. In one embodiment, only devices with device _ update _ ready settings will be updated.

Duplex operation

An embodiment of duplex operation will now be described with reference to fig. 11A. In various embodiments, bus 900 may operate in a simplex or duplex mode of operation. In this arrangement, the I/O port may be configured to transmit and receive both signals simultaneously through the design of the output driver, which may be used to enable bus lengths in excess of 25 meters, such as may be used for a home audio system.

In this embodiment, the transient response at the forward and backward traveling waves is used to evaluate what is happening when there are two simultaneous drivers. The voltage at any point is determined by the sum of the forward and backward traveling waves. Thus, we can measure the point at any node and subtract the effects from both drivers, rather than simply by considering the impedance of the output driver and the impedance of the transmission line.

For simplicity, let us first evaluate the case with only two

drivers

902 and 904 at each end of the transmission line. Let us also assume that

drivers

902 and 904 use a signal having an impedance Z equal to the transmission line impedance₀To terminate the link appropriately. This means that both the forward and backward traveling waves will be half the initial driver voltage. Since the voltage at any point can be found from the sum of the forward and backward traveling waves, we can find the correct received voltage by subtracting half of the driver voltage from the measured voltage. This can be done for the differential case by simply adding half the inverted transmit voltage to the received signal (e.g., by using capacitor swapping and adding half the differential transmit voltage). In this approach, a bi-directional delay during turnaround in the transmitter direction is not needed for many configurations and much longer links (e.g., 25 meters) are possible with continued operation, and no interruption in the data stream due to the absence of turnaround delay, and full duplex operation at very high speeds is possible (0.1-5 Gbps). Note that this configuration does not require any timing adjustments as long as operation is limited to one node at each end of the line and at least one node sends out synchronization pulses on a periodic basis.

Multiple slaves

Various embodiments of a plurality of slaves will now be described. While duplex operation is relatively simple when having a single master and a single slave, the situation becomes more complex for multiple slaves. One problem is that the intermediate node will reflect waves from either direction because it does not present a termination (in order to enable a multi-branch connection). Thus, conventional duplex operation may not be practical for certain implementations. However, it is possible to increase throughput with proper timing of the signals. In various embodiments, the signal will first go from the master to the slave. Other slave devices may need to wait until the forward wave from the master has passed through them before it can begin transmission. Thus, an exemplary timing diagram that handles this case and does not require any handover delays would be the following transmission sequence: { M, S1, S2, S3, S4, S5}, and then when changing direction, repeat the pattern in reverse { S5, S4, S3, S2, S1, M }, where M denotes master, and S1 is the slave closest to the master, and S5 is the slave furthest from the master. In other words, the devices attached to the bus will emit a sequence for forward or backward waves, and the approach avoids problems with reflections from intermediate points on the transmission line. Before attempting the scheme, the timing delays of the devices attached to the bus will be determined and corrected.

By ensuring that a differential signaling scheme is used for all communications, the transmitted and received EMI will be significantly reduced. Fig. 11B shows an example of differential signaling 920 starting with an idle period, followed by a synchronization signal, then data, and then becoming idle again. The idle periods should also be of a differential nature to avoid common mode noise, which means that the terminals on one line should end up with a high level and the other end should end up with a low level to avoid static power consumption during the idle periods and thus enable very low power consumption for moderate bandwidth requirements.

Fig. 11C shows an example of a differential signaling system 930, the differential signaling system 930 having terminations to high and low signaling voltages to ensure lowest possible EMI and lowest possible power consumption in idle mode. Fig. 11D shows a similar example of a differential signaling system 940, where the

transmitters

942, 944, 946, and 948 at each end are used as serial terminations of the bus, thereby reducing power consumption at the end nodes due to no termination load and simplifying implementation. When the bus driver at each end is not signaling data, it will enter an idle state, signaling the default termination voltage, thereby reducing power consumption in the idle state. In some embodiments, one of the two transmission lines may use a power line for shielding instead of ground, thereby also being able to transmit power. Some embodiments may use 4-stranded rather than shielded coaxial cables, including, for example, DATA +, DATA-, ground, and power in a four-stranded pair configuration for low EMI requirements. The ground and power lines will further reduce EMI. In other embodiments, a single shield would be used, and the power and differential data would be located in three wires inside the shield.

In some applications, it is important to minimize audio noise caused by random signaling that occurs on the bus. This can be done by changing the signaling levels of various sources on the bus, for example, by using pseudo-random generators at the transmitter and receiver of the data port, thereby randomizing the bus traffic and thereby reducing the spectral content in the audio band. In some cases, the randomization may be performed with spectral sharpening, so by multiplying the data signal with the high frequency content (e.g. by multiplying each row with some random or predefined value), the spectral content in the audio band is even lower. In some cases, randomization may be performed by simply multiplying the rows by a carrier outside the audible bandwidth. In some embodiments, each port includes an error tester (e.g., an 8-bit pseudo-random generator for verification and testing). The port tester may also be used to scramble and descramble audio data. The multiplication in the digital domain may be performed by XOR or XNOR gates. For example, nearly identical pseudo-random generators may be used to recover the original data sequence, see, e.g., the exemplary SoundWire specification for pseudo-random generators and receiver/testers. Similar techniques have been used earlier, for example in radio modems, to reduce or remove DC content from the transmitted data stream. The use of scrambling here is not as much as it would be the case to avoid the transmission of multiple symbols with the same value, which may lead to a loss of synchronization, but serves to reduce the low frequency content of the output spectrum in order to avoid any interference in the audio band.

In some cases, randomization may be performed using a delta-sigma modulator with a known pattern in order not only to randomize the outputs from the various transmitters and thereby reduce any audio interference, but even to noise shape the output spectrum of the noise by intentionally controlling the noise transfer function of the modulator.

Cable specification

Exemplary cable specifications according to various embodiments will now be described. For in-ear headsets, thin cables may be used to meet user requirements, such as configurations using shielding of thin AWG30 or AWG34 wires. For longer links or for large headsets and headphones, thicker cables may be used, which also reduces the attenuation of the bits, except that only 4, instead of 8, wires are needed, an example would be a twisted pair of cables similar to that required for CAT5 (wire type AWG 24). For example, a standard 100BASE-TX cable may be used. The attenuation of a 15 meter link would be 66 dB/100 m x 15 m = 9.9 dB or 3.1 times. Therefore, the difference between the transmit voltage and the maximum receiver lag should take this into account when designing the system.

Intermediate node

An exemplary embodiment having an intermediate node will now be described. In various embodiments, the end node has Z₀So as to match the transmission line, while the intermediate node will investigate¹/₂ Z₀Will essentially investigate two transmission lines, each having an impedance Z₀). It is generally desirable to provide the same performance for all nodes. In various embodiments, (i) each node has an output voltage of U0; and (ii) each end node has Z₀The output impedance of (1). If the traveling wave is active when it reaches the node, the impedance of the intermediate node will result in a reflected wave. This situation can be passed through the letterProper timing of the signals (i.e., each node first transmits a signal after the signal wave with previously transmitted information has passed) is avoided. The traveling wave will eventually be absorbed at the transmission line end. Exemplary transmission line impedances and signaling voltages may include Z₀ = 75 Ω，U₀= 250 mV, wherein differential signaling is used.

In addition, the intermediate node on the transmission line will face both line inputs and the output signaling voltage will be lower if its output impedance is the same as the node located at the far end of the transmission line. This can be corrected by using a lower output impedance for the intermediate node, by increasing the output drive voltage of the intermediate node, or by adjusting the receiver on the transmission line to a lower threshold voltage.

Start-up sequence

An exemplary startup sequence will now be described. In various embodiments, the conventional signaling is differential, two-level signaling. However, to obtain a unique pattern for start-up conditions and for resynchronization after a possible slave failure or after a power-down condition, the master may be configured to send out a third or different higher voltage level. This level will not be used for data transfer but only for a re-synchronization or start-up condition of the slave device (wake-up from low power standby). This will not affect the emitted EMI because this higher level is only used during the initial synchronization (e.g. the first 1 ms). In one embodiment, the start-up sequence consists of 12 bit slots with a voltage level twice the normal signaling level. In various embodiments, the start-up sequence will be immediately followed by a synchronization edge used by the PLL. No start-up sequence will be transmitted during normal operation to reduce EMI and increase available bandwidth. In the illustrated embodiment, during start-up or resynchronization, the master will have approximately 62.5% of the original bandwidth left (using a 12.288 MHz clock frequency) and 40% of the normal bandwidth left in the 9.60 MHz mode of operation. In a simplified implementation, a DC offset is added to a certain number (e.g., 12) of slots, and because the receiver is differential, the additional offset will not affect the data, but can be used to detect a power-up condition. In an even simpler implementation for only initial and start-up conditions, a logic voltage such as 1.0V may be used for wake-up detection, thereby eliminating the need for a differential receiver in a low power state.

In the following, exemplary differential signaling voltages are illustrated in the table.

In various embodiments, to ensure a secure boot mechanism for the slave device, a higher voltage level is used on the bus line when the slave device needs to return to synchronization again. This higher voltage will be used to distinguish between normal data traffic and reset conditions. It may also be used for power-up circuits that wake up (e.g., wake-up word) at low power when the bus is running. Higher bus voltages may occur for longer than normal data symbols to avoid random noise on the bus triggering the wake-up circuit and to reduce power consumption. In order to obtain reasonable tolerances, good noise immunity and low power consumption, it is suggested that the wake-up event will consist of a 12-bit-gap pointer (trail). This corresponds to a minimum time of occurrence of about 89 ns at the highest bit clock of 134.400 MHz.

Referring to FIG. 12, the system is powered up in step 1002 and the lock flag and driver are disabled (step 1004) and the phase detector is disabled (step 1006). In step 1008, a wide search is enabled to detect the device. If a special sequence for the device is detected in step 1010, a synchronization pulse is detected in step 1012. If no special sequence for the device is detected, the steps are repeated until the special sequence is detected. In step 1014, if the PLL is locked, the wide search is disabled (step 1016) and the driver is enabled (step 1018). When the time gate is opened (step 1020), the synchronization sequence is repeated (step 1012-1018). If the PLL is not locked (step 1014) and narrowband is enabled (step 1022), then the driver is disabled in step 1024 and control passes to step 1008 to repeat the wide search at high power.

The operation of the special start-up circuit 1100 will now be described with reference to fig. 13. During normal operation, there will be no start-up sequence and the output from the circuit will be zero. The output from this circuit is used until the PLL becomes locked. In operation, the circuit will filter the input from the bus and enable the PLL to see the next high-to-low transition if the bus has been above some high threshold for some time. When the bus level is low, the circuit will discharge any accumulated charge and start looking again for an uninterrupted sequence of high values.

The length of the series of logic ones will depend on the clock frequency and the length of the high value sync pulse. This can be used by analog circuitry to check for the start of synchronization under error conditions.

The output from the phase detector is enabled after 50 ns (up to 120 ns) or a logical one, followed by a logical zero. In the illustrated embodiment, this enables audio transmission even during a failure using up to 4 consecutive time slots. During a fault condition, the first 4 columns are reserved for audio transmission, while every other 5 columns are used to send a logic zero, followed by more audio, until the start of the sync pulse. After the 0-1 transition, the phase detector output is disabled again. In one embodiment, after the slave device has acquired a lock, it looks inside a narrow window for synchronous transitions determined by the current lock position and ignores all other bus traffic.

Lock detector

An exemplary signaling solution will now be described. In the first signaling sequence solution:

three-level signaling is used: { -1, 0, +1} as signaled by { low, zero, high } for reduced EMI, similar to CAT5 signaling.

Logic zero: the same level as before (four zeros may be followed by values from a reverse sequence, i.e. going in the opposite direction after a few zeros to ensure safe start detection).

Logic one: the next value (e.g., ones) in the sequence of ternary values will be signaled as the sequence zero, high, zero, low, zero, high, low, etc. Then, it is more likely than a legitimate data value that the synchronization value will use a different sequence (e.g., { high, low, high, low } or { zero, high, zero, high }) to distinguish between synchronization and data. In other words, ternary coding enables the receiver to reliably distinguish between synchronization and data, while enabling a reduction in EMI by reducing the generated harmonics.

In a second signaling sequence solution, two-level signaling is used. In one embodiment, no device other than the master may have more than 4 slots in a row, or zeros will be inserted between packets. If multiple devices send out data after each other, a gap is used between every 4 bits and zeros are inserted. If the analog delay circuit can be fabricated with a narrower tolerance than described above, more bits can be delivered in sequence. This is an example where bandwidth is compromised to enable special coding of synchronization symbols that differ from any legitimate data value. Other encoding schemes such as 8/10B encoding may be used to distinguish between synchronization and data.

In the third signaling sequence solution, the DC offset is applied to all signaling from the master, and thus DC offset will not be used. The differential signal is modulated by the master device with a common mode signal to indicate the start of a frame. While this will increase EMI to some extent, this will only occur for a short period of time during initial synchronization. Such a change in DC offset can be reliably detected by the slave device regardless of the current signaling mode on the bus and any previously encountered states inside any slave device, and thus synchronization can always be obtained. Fig. 14 (3) illustrates an example of this solution.

High speed transition

Referring to fig. 15, an embodiment of the operation of the present disclosure will be described. This solution allows to change the synchronization rate even while the audio is still running. In one embodiment, 250 mV signaling may be used for both slow mode and fast mode, and the synchronous edges of the received signal inside the gated time window are used for audio sampling. In the slow mode, if the time slot is not driven, there is no additional power consumption on the bus and there is less additional power consumption from the internal PLL running at a higher rate. Thus, the higher frequency of the slow mode can be selected, which is used as the low power mode. In the slow mode, the device can check for synchronization relatively easily (e.g., 2 out of 12 slots for synchronization). In one embodiment, all devices maintain synchronization at all times. In another embodiment, the device may enter a sleep mode and wait for a special VDD wake-up signal that will induce a delay (e.g., 1 ms) before it functions.

In one or more embodiments, the transition to the high speed begins in the slow mode with a slow sync (e.g., 768 kHz). Additional synchronization symbols are inserted to prepare for the high speed mode and make the slot shorter but maintain the original 768 kHz transition. Suppose a symbol is read in the middle of a transmission interval. The slow mode device does not see additional synchronization symbols. Each transmitter includes an internal clock that runs at least twice the original slot clock to insert shorter symbols. In the high speed mode, there are now more slots. In various embodiments, the slow device may read in the fast mode. This solution enables changes in bandwidth and synchronous repetition rate while keeping the audio running, while allowing both slow and fast devices to be attached to the bus at the same time. It basically inserts sub-intervals in the existing timing and uses these sub-intervals to add bandwidth to the existing transport protocol. This approach can be used for backwards compatibility with existing interfaces (such as SoundWire) and also enables higher bandwidth to be supported, but does not provide the original interface.

Frame synchronization and bulk transfer

Those of ordinary skill in the art will recognize many advantages of the systems and methods disclosed herein. In various embodiments, multiple upstream facing interface devices (slaves) may be attached to the bus at various points and may communicate with each other at full speed due in part to accurate timing measurements. Due to timing control and discrimination between forward and backward waves propagating through the transmission line, signaling from different devices can be stacked close together. This enables high bandwidth even with moderate slew rates of reduced EMI, which is beneficial for certification and compliance with EMI standards such as FCC class a and B devices (part 15).

The systems described herein may be used to facilitate low power data communication on two wires. The interface supports multi-drop operation with one master and one or more slaves and allows point-to-point communication between slaves at full speed and across longer distances than conventional time-division multiplexed low-latency systems. Lower electromagnetic interference (EMI) is achieved through differential low voltage operation and slew rate control. Each slave device includes a PLL/DLL and the system supports a terminated multi-drop, multi-device system arrangement.

The system and method include a simple frame structure and initial synchronization sequence that provide many advantages over conventional methods. In various embodiments, initial synchronization between the slave and master devices is simple, robust, and uses a constant frame size. While varying frame sizes have been used in prior systems to ensure compatibility with multiple clock systems, different approaches have been employed in this disclosure. The present disclosure takes advantage of the additional degrees of freedom provided by an oversampling clock system as disclosed herein to provide a flexible and efficient solution. In some embodiments, the actual clock frequency may be inferred from the beacon signal forming part of the frame.

In some embodiments, a row of data includes 80 slots regardless of the clock frequency and the mode of operation. The interpretation of these slots may depend on the chosen configuration, although the various fields will be located in the same sequence. At start-up, the default data format is set for the longest bus diameter (slowest speed). Referring to fig. 16A, different fields in each row of data are illustrated. By varying the interpretation of the individual time slots it is possible to choose various tradeoffs between baud rate and bus diameter. The synchronization pattern repeats at a frequency of once per row of data (e.g., as shown in the figure, the synchronization rate is 3.072 MHz). Each row starts with a zero to one transition. This transition is used as a sampling event for the internal delta-sigma converter and to lock the PLL/DLL onto the bus so that bits can be received. FIG. 16A illustrates a synchronization pattern and a simplified line description. One advantage of using a zero-to-event as a sampling event for a delta-sigma converter is that it only contains jitter from the master clock and does not contain the additional jitter associated with clock recovery of the slave device. Thus, due to the requirement of low current consumption of the PLL/DLL, the solution enables low jitter of the audio samples even if there is a higher jitter inside the clock recovery unit in the slave device.

Each row consists of: synchronization field (frame starts with logic one and ends with logic zero), command field (C is a command from the master), field for transmitting audio in the forward direction (typically from master to slave), bi-directional delay "turnaround" to enable the signaling direction (T)₁) A response field "R" from the slave (used only when read from the slave), a field for transmitting audio in the backward direction (typically from slave to master) and possibly a gap field and ends with the start of the sync mode. The row may also include a forward command (master to slave) and frame (beacon) field (F) and a data field D₀-D₄. The number of time slots allocated to each of these fields may vary with the application, but the total number of time slots within a row is a fixed number, e.g., 80. To change the number of columns in a row, the technique of FIG. 15 may be used (e.g., changing at a synchronous rate from 768 to 3072 kHz). Fig. 16 shows the default configuration at startup, where the index shown below is the number of slots at the beginning of each field.

The transmission of data will take place over a transmission line. To avoid collisions between data packets from multiple devices, we will distinguish between forward and backward waves. The forward wave starts at the main and is directed away from the main. Backward or backward waves are data that has been sent out of the slave and travels in a direction toward the master. During the turnaround period, no devices will transmit any information and their drivers are disabled (except for the possibility of active termination for such a system).

Audio data may travel in both directions on the link, i.e., in the forward direction from the master device to the slave device and in the backward direction from the slave device to the master device. If a slave device wants to transfer data to another slave device located further away from the master than the slave device itself, it will send the data in the forward direction, i.e. at the label D₀-D₇As shown in fig. 16B. In various embodiments, the system may accommodate control data (register reads and writes), isochronous audio (PDM and PCM), asynchronous audio (PCM), and bulk transfer operations.

The table below lists registers that allow fine tuning of the interface to accommodate various bandwidth requirements versus signal integrity decisions. In some embodiments, the interface will start with a default value after a reset has been applied. In this embodiment, the Tx delay is stored as a binary complement signed value to ensure compatibility with the multi-branch configuration, and the Rx delay is stored as a binary complement signed value. There may be a negative offset due to hysteresis in the PLL/DLL. If the value of register F is equal to the value of register G, block data will not be transmitted. If the value of register j is equal to the value of register k, block data will not be transmitted. In this embodiment, all register values are counted in half clock increments and are positive (one byte) except for the TX and RX delay registers.

Referring to the table below, the Tx delay is stored as a binary complement signed value to ensure compatibility with multi-branch configurations. The Rx delay is stored as a binary complement signed value and there may be a negative offset due to hysteresis in the PLL. If the value of register F is equal to the value of register G, block data will not be transmitted. If the value of register j is equal to the value of register k, block data will not be transmitted. All register values are counted in half clock increments. All register values are positive (one byte) except for the TX and RX delay registers.

The outline of the frame is illustrated in fig. 17. The boxes in the first and last columns are driven synchronously by the master at a rate of 3.072 MHz. Some boxes in the next two rows (e.g., OP, ID, # #, C, FA, SA) represent command fields driven by the master. The box labeled M represents master-to-slave audio data, and the box labeled S may include slave-to-master audio data or responses. The boxes in the second column labeled 1 may comprise a turnaround delay or a logical one, and the box labeled T is a turnaround delay from master to slave. In the illustrated embodiment, one column (arbitration/count) is allocated for multi-branch, multi-write applications. Most columns are dedicated to a single device, but can be shared with careful timing control as described herein.

To save bandwidth, register read and write operations are performed by first updating the address register internal to the slave, after which the actual read or write operation occurs. In this manner, repeated read and write operations will not require the address to be transferred in every command.

The commands are encoded using redundancy such that at least two errors are required to generate an operation different from that expected, but more errors are typically required before this condition even occurs. These operations have been designed to allow for conservative operations-any single error will result in no operation, rather than attempting to occur before a possible erroneous operation. The commands are built on the following symbols { A, B, C, D }. The symbols are defined as follows:

A = {D2，D1，D0} = {1，0，0}

B = {D2，D1，D0} = {0，1，0}

C = {D2，D1，D0} = {0，0，1}

D = {D2，D1，D0} = {1，1，1}。

these commands have a hamming distance of two between them, i.e., they require two errors to map one correct symbol to another. The following values are considered as faulty or illegal symbols:

F1 = {D2，D1，D0} = {0，1，1}

F2 = {D2，D1，D0} = {1，0，1}

F3 = {D2，D1，D0} = {1，1，0}

F4 = {D2，D1，D0} = {0，0，0}。

if any of the illegal symbols are encountered in the command, such command can be ignored and the intended receiver can respond to the request attention at the end of such frame. Any ongoing block operations should be suspended and only non-block operations will continue.

The command is defined by the OPCODE field. This field may consist of 3 or 6 bits. Reading only 24 bits from memory will use a shortened form of OPCODE. In other words, when a specific OPCODE for "read 24 bits" is encountered, the frame should be immediately recognized as a read frame even before all 6 OPCODE bits are read.

Block operations are suitable for large-scale transfers of data to and from registers. These transmissions have been protected from interfering with any audio transmission by dedicating specific fields within a row to these types of transmissions. Thus, audio transmissions cannot interfere with block transmissions, and vice versa. This is handled by the lowest hardware layer. This ensures that a simple programming error does not crash the bus. It is possible to reduce the time slots allocated for block operations to zero. This will ensure that block operations will not occur even if several errors should occur in the frame.

In one embodiment, all block operations start with the symbol a, followed by one of these values for the second symbol: (i) "A" (stop block operation) -the block will be the second to last block of a series of block operations, and the next frame will be the last frame containing block data, i.e., the one for which block transfer will stop delaying; (ii) "B" (defining the starting address of the successive write operation) — data will be stored in memory, starting at the defined starting address, and each next data word will store the contents in the next memory cell, and the third frame from the current frame will use block transfer, i.e. block transfer will start two delayed frames; (iii) "C" (defines the starting address of the successive read operations) -the data will be stored in memory starting at the defined starting address, and each next data word will store the contents in the next memory cell, and the third frame from the current frame will use block transfer, i.e. block transfer will start two delayed frames.

In an alternative embodiment, instead of using a "stop block operation," the number of elements to be copied during bulk transfer will first be defined along with the start address. After the bulk operation has started, the addressed device will perform all operations by itself, and at the end of the bulk transfer, will generate an IRQ ("request attention") to let the master know that the transfer has completed. The master may then be able to access the status of the slave to see if the bulk transfer was successful and to check if the CRC value is correct.

A single read and write operation works by first defining the starting address of the register operation, after which any later operation will perform an I/O operation using the previously defined address values. The definition of the address for the subsequent register operation is defined by signaling the symbol D followed by the symbol B.

Read and write operations work by first defining the starting address of a register operation to increment by address, after which any later operation will perform an I/O operation using the previously defined address values. When this operation is used, subsequent read or write operations will increment the address value internal to the device after each read or write operation has been completed. The definition of the address for the subsequent register operation with address increment is defined by signaling the symbol d followed by the symbol C.

A single write operation is performed by signaling the symbol d followed by the symbol a. The address used must be defined before the operation is used.

When a single read operation is performed, the read operation will block all bits of the second symbol due to the complex timing details of the bus. Thus, the read operation is defined entirely by the first symbol, while the second symbol is ignored (in which case the master will not drive the bus). Furthermore, the reading operation should start immediately after the first symbol (first three rows in the frame) has been read and interpreted. The read operation is defined by the symbol C.

If the device ID number is 7, this will perform a status read operation, where all devices attached to the bus (except the master) will return their status. The three bits returned from each device are as follows (MSB returns first, LSB last):

devices 0-6 may respond in the corresponding a-G field with associated device status data (attached to bus, IRQ level). Due to the previous value of one on the bus, negative logic (valid event zero) would have to be used to represent any change. Only the last 21 bits of the possible 24 are used for this operation. The device may use dynamic address allocation to obtain this 3-bit address or a fixed device address (e.g., pin programming). If dynamic address allocation is used, the device may use address zero as an initial value. If the master sets the ID to zero during the read, it will indicate that the 24-bit CRC value was read from the last accessed bulk transfer port. This means that if the device state is being read, the first opcode will be "C" and the second opcode is not driven.

Various status flags are provided to return status from all devices attached to the bus, including acknowledge flags and attention flags. The validation flag validates a successful transaction (e.g., a read or write validated by a three bit CRC value). To avoid possible bus collisions, this has been defined as an active logic low signal in the case where multiple devices attempt to drive the bus at different values. If a device requests attention, it should drive the slot low, otherwise it should not drive any value during the slot. Since this is a shared bit, all devices can respond to the slot. An attention tag (e.g., AT) issues a request for attention from any device attached to the bus. To avoid possible bus collisions, this has been defined as an active logic low signal in the case where multiple devices attempt to drive the bus at different values. If a device requests attention, it should drive the slot low, otherwise it should not drive any value during the slot.

In order to avoid that a single error results in a block transfer operation, the block transfer will be fully defined in the previous frame. By changing the number of command bits per line, it is possible to transfer large amounts of data to and from registers very quickly, e.g., for DSP program uploads. The block transfer will only occur if a column is allocated for this operation, which occurs by writing a register that defines the start of the block transfer. If the block transfer register is equal to or greater than the turnaround register after it in timing, block data will not be transferred even if a block transfer command is issued. This ensures that the block data does not accidentally overwrite the audio data. An example command table with encoding of commands is set forth below:

with reference to fig. 18A, 18B, and 18C, the block transfer operation will now be described in further detail. A 32-bit address is assigned to the slave (not incremented on subsequent operations), as illustrated in frame 1802. Due to the compact timing, the device ID and initial values in column two may be buffered because the command is completed first after these values have been sent. Next, as illustrated in frame 1804, a 32-bit address is assigned to the slave (incremented on subsequent operations). As illustrated in frame 1806, the reading of 24 bits using the previously assigned address (if ID = address 7, an exception in the command) is obtained. As illustrated in frame 1808, the read status of all attached devices (ID = 7, exception in arrival command). The first three bits of the 24-bit returned data are unused and may be overwritten by the last used bulk transfer port. Frame 1810 illustrates the read status (exception in read command, ID = 0) from the last bulk transfer operation-e.g., reading a 24-bit CRC value from the last used bulk transfer port. Frame 1812 illustrates writing 32 bits using the previously allocated address. The slave device will not know that this is a write command up to line 6, which means that it will need to buffer the register data in

lines

4, 5 and 6 in order to be ready for a possible write command.

Frame 1814 in FIG. 18B illustrates the initiation of a 32-bit block write transfer operation. The writing of data will start first in the next two frames (i.e. not in this frame nor in the next frame). The frame layout will be the same until the third frame begins. Frame 1816 illustrates the transfer (continuation) of the write batch. Frame 1818 illustrates the initiation of a 32-bit bulk read transfer operation. The reading of the register data will start first in the third frame. Until the third frame begins, the frame layout will be the same as in the previous frame (i.e., bulk transfer has not yet begun). D0-D23 are mapped to devices 0-7. Each device may have up to three bulk transfer ports. A value of 0 indicates that the port is to be activated in two frames. Each device is assigned three bits (e.g., device 1 is assigned bits D3-D5, each bit corresponding to an internal bulk transfer port). Frame 1820 illustrates the transfer (continuation) of the read batch of data.

Frame synchronization algorithm

The master assumes that the slave will have acquired synchronization (PLL/DLL lock) after a certain period of time. The slave devices may attach to the bus at any supported speed and provide feedback on their capabilities. Embodiments are provided for checking whether a slave device has obtained message synchronization before starting communication. In some embodiments, a single frame message is used. Beacons may be used to indicate the start of a frame and may be used for synchronization.

Referring to fig. 19, an embodiment of a frame synchronization algorithm 1900 will now be described. In step 1902, the process waits for the PLL or DLL to lock with the master. Ffff, step 1904, sets the SHIFT register (SHIFT 1) to 0xffff. In step 1906, the first value from the first row is read into the second shift register. The process repeats over 32 lines to initialize the search registers. In some embodiments, each row repeats at 3.072 MHz, which may provide sample points for PDM and high quality audio. Each frame is repeated over 32 lines, giving a frame repetition frequency of 96 kHz. In some embodiments, the beacon indicates the end of a frame and is transmitted every third frame (at a 48kHz repetition rate).

The next steps are then repeated over 64 frames. In step 1908, the value is read from the shift register 2, which should be the opposite of the new read value (the comparison made in step 1910). If not, the bit in the first SHIFT register is reset in step 1920, otherwise the process proceeds to step 1912 to update the second SHIFT register, SHIFT 2. Step 1908 shifts both registers and continues to complete 32 rows. The process is then repeated over 64 frames. By checking the alternating pattern, frame synchronization can be achieved after 64 frames. In other words, instead of checking the actual synchronization position, this algorithm clears all invalid positions until only a single valid position is left. This method ensures that the slave will always lock regardless of any random data present in the command column. If the 32-bit register contains more than a single bit that is still set after 64 frames, the method is repeated until the invalid locations have been cleared.

In the illustrated embodiment, the only bit of one in the first shift register represents the frame sync position. In some embodiments, if there is more than one bit in the first shift register with a value of one, then an error has occurred and the algorithm should be restarted. This is not expected to occur under normal conditions (for random data this occurs with a probability of 2^-64 < 10^-20）。

In one implementation, all fields are oversampled using a master clock. The data row is divided into 80 slots and a plurality of slots are used to define the data on the bus. All fields may be oversampled using the master clock. In this embodiment, the default clock frequency is set to 245.76 MHz, but other frequencies may be used. The initial PLL synchronization frequency is set to 3.072 MHz for the slave and master, but other frequencies may be used as described herein.

The interpretation of these slots will depend on the chosen configuration, although the various fields will be in the same sequence. At start-up, the default data format is set for the longest bus diameter (slowest speed). Referring to fig. 16c, an example frame structure is illustrated showing different fields in each row of data. By varying the interpretation of the individual time slots it is possible to choose various tradeoffs between baud rate and bus diameter. The synchronization pattern repeats at a frequency of one per row of data. The synchronization pattern is a zero to one transition.

In the illustrated embodiment, the rows include a synchronization field (0-1), a turnaround period T₁(in which period neither the master nor any slave is active to allow a change of direction, the slot also including a forward command (master control) and frame information F), a command field (CMD or acknowledge R), a field for the delivery of audio in the forward direction (typically from master to slave), a field for the delivery of audio from master to slave B₁Field of bulk register data, turnaround period T for enabling a change of signalling direction₂Fields for delivery of audio in the backward direction (typically slave to master), fields for slave to master B₂And a null field for data alignment before the next line begins.

When a master issues a command in the command field, it will also drive the adjacent T with the same value₁Fields to ensure better timing margin. However, when the master expects a reply from the slave, it will not drive T₁And a Cmd field. T is₂The fields are not driven by any device and are allocated for data turnaround. When a slave responds within the command field, it will drive only the "Cmd" field, and the adjacent T' s₁The field is to be de-activated and used forAnd (4) signal turnover. The actual distance from the slave device to the master device may be unknown. Thus, a command will be issued that will measure the actual delay from the slave to the master. The actual delay will be used to optimize the timing, e.g. to optimize the receive eye pattern.

The number of time slots allocated to each of these fields may vary by application, but in the illustrated embodiment, the total number of time slots within a row is 80. The default configuration at startup indicates the number of slots at the beginning of each field. No time slots are allocated for bulk transmission at start-up.

Marked as T_NIs used for turnaround delay. The actual data values inside these slots are undefined. Turnaround delay T₁-T₂Are assigned to allow the data to change direction (i.e., from forward to backward waves, and vice versa). The number of bits transmitted from the master and slave devices may vary and should be programmed before any transmission begins. In the example shown above, the master transmits 6 bits to the slave in each row and the slave transmits 4 bits to the master in each row. This example shows a default configuration, and the bandwidth allocated to the master and slave may be programmed to other configurations. The synchronization pattern remains fixed regardless of the data configuration. It is possible to significantly increase bandwidth, typically at the expense of higher jitter requirements and shorter maximum bus diameters, by programming the number of time slots allocated per data bit and for command turnaround, etc. This programmability allows system designers to trade-off bandwidth for higher signal integrity by deciding how much bandwidth is available in each direction for synchronization, commands, and data. Furthermore, by programming the slew rate and output transmission voltage, signal integrity can be optimized while enabling the system to pass EMI requirements.

When a master issues a command in the command field, it will also drive the adjacent T with the same value₁And T₂Fields to ensure better timing margin. However, when the master expects a reply from the slave, it will not drive T₁CMD and T₂A field. When a slave device issues a response within the command field, it will only drive the "Cmd" field,and adjacent T₁And T₂The field will be de-driven and used for turnaround of the signal. The actual distance from the slave device to the master device may be unknown. Thus, a command will be issued that will measure the actual delay from the slave to the master. The actual delay will be used to optimize the timing, e.g. to optimize the receive eye pattern. The master will delay the slave before normal sampling¹/₂The data cells are sampled, i.e. at the edges between two data values for delay optimization, while the value for high data integrity will be in the middle of each data cell.

Two oversampling can be achieved by using two edges of the clock. When a master issues a command in a command field, it will drive the adjacent "T" field with the same value. When a slave device issues a response within the command field, it will only drive the "R" field, and the adjacent "T" field will be de-driven and used for turnaround of the signal. If the bus diameter is short and the bus frequency is low, the leakage current may change the bus value before a delay measurement can be made. In this case, it is preferable to include a bus keeper in the system to ensure that the leakage current will not affect any delay measurement. The output impedance of such a bus keeper will typically be in the range of 1-2 k omega.

Once the slave locks, the slave should respond by informing the device status. The slave PLL circuit should be able to obtain a lock with the master within 1 ms and be able to output a "PLL locked" signal to be used by other control circuits. In addition, the PLL should expect a logic signal from the slave command controller ("message sync" signal). When the "message sync" signal is high and the slave PLL has determined that it is locked, it should change to narrow bandwidth mode. In the narrow bandwidth mode, the time gate will only allow the output from the phase detector to be in a narrow time window around the synchronization edge. If either of these signals is not active (high), the PLL should change to wideband phase detection and the slave should not be able to write to the bus (this is done so it cannot overwrite the other device).

Audio data may travel in both directions on the link, i.e., in the forward direction from the master device to the slave device and in the backward direction from the slave device to the master device. If a slave device wants to transmit data to another slave device that is located farther from the master than the slave device itself, it will send the data in the forward direction (i.e., in the field labeled "master audio").

Port programming

In various embodiments, data transfer is handled through port programming. To enable data to be transmitted from any transmit port to any receive port, the data may be processed like a mono channel. Using this approach, stereo channels and multi-channel systems will use longer programming sequences than if the channels can be treated as packets. However, this approach is simpler and gives more flexibility with respect to arbitrary data transmission.

All registers associated with a port will have bank (shadow) registers. The selection of the primary and shadow registers is accomplished by writing to the bank select register. This register has been additionally protected in order to avoid catastrophic changes to the behavior of the bus due to changes in the values of one or more erroneous bank registers. In other words, to change a bank value, it is necessary to write a specific 8-bit value to a specific register to select bank number one and to write a different 8-bit value with a long hamming distance between the two words to select bank number 0. The bank registers are used to change seamlessly between two or more playback modes without encountering any glitches or distortions when changing from one scene to another. Note that in order to avoid any audio glitches, it may also be necessary to take care of the packet delay when changing the filter configuration by appropriate buffering.

To be able to freely transmit any data from any transmit port to any receive port, both transmit and receive ports are free to program the location of the data within the frame. For example, a row variable may allow the selection of the first row of data to be written, and a row increment may be used to select the interval to the next active row. A column variable may be used to select the first column to be written, and a "last column" variable may be used to select the last column in which data is being written to or read from. The length of data from a given data port may also be programmed (e.g., data word length). In some embodiments, the data values may extend over more than one frame, and the synchronization of the streams may be programmed. This is typically achieved by using beacon bits to achieve this synchronization.

Bulk transfers may require defining row start, row increment, column start and column stop registers before bulk transfers are to be enabled. The bulk control bit may be used to enable and disable bulk transfer commands. Ports that support bulk transfers only will use this bit, otherwise the value is ignored. The bulk transfer may have an additional register containing a 24-bit CRC check value in all bits transferred during the last bulk operation performed by the port. Each device may have only a single bulk transfer port operating simultaneously, and will typically never have more than one bulk transfer port. The bulk control registers may include a start register (e.g., 32-bit address), an end register (e.g., 32-bit address), or a length register (e.g., 32-bits), a flag indicating single or sequential transfers, and a read/write direction flag. Note that the port must first be enabled to react to the start of the bulk transfer command. The ports enabled during port transfer are given by the 24-bit word by master write. During the start of the bulk transfer operation, a 24-bit word is written by the master. Each device internally assigns these bits to bulk transfer ports (if any one is implemented).

Power consumption

For short systems with modest bandwidth requirements, it is possible to significantly reduce power consumption by avoiding termination of the link. Instead, the transmitter will be terminated in series with the line impedance. To avoid any reflections from the transmitter side, the transmitter output impedance should also be relatively stable during changing output levels. This can be achieved by having a plurality of drivers that are activated consecutively one at a time, so that there will be no time zone where the output impedance will suddenly be very high. Furthermore, if there are only two devices located at each end of the transmission line, the problem in reflection will disappear and high speed and low power can be achieved with the unterminated ends of the link and the serially terminated transmitters.

By avoiding parallel termination, power consumption will be reduced to 2 x 125 μ W = 250 μ W only by capacitive charging (based on 250 mV signaling, 50 pF load and 40 Mbit signaling). In practice, we would need to add the power consumption of the receiving PLL (e.g. 250 μ W) and some extra bandwidth for control overhead, but a power budget below 1 mW is not practical.

In various embodiments, the master should be able to wake up the slave, and the slave should be able to wake up the master. The simplest zero power wake-up (< 1 μ Α) mode will utilize a higher signaling voltage (≈ 1V) to ensure good signal integrity and power down of all other circuits. More complex solutions may maintain the same signaling voltage in all modes, but this would require more complex circuitry and receiver circuitry that is always turned on (100 μ Α). The master will write to all slaves and tell the bus stop to start in the next frame. For a multi-drop bus, this would require the endpoint node to disable its termination at the end of the frame. In the next frame, the master will drive D + to Vdd using a weak driver (≈ 5 k Ω). The high impedance may be used to reduce any EMI during the transition. As long as D + is VDD, it is an indication that the low power state is still active. The D + line is pulled down from the available medium strength driver (≈ 600 Ω) to signal a wake-up event. This will ensure a transition of at least 7 ns (15 pF load or more). This line would have to be pulled low for at least 50 mus to ensure that the master has registered for the event (even if a standard 32.768 kHz low power wake-up clock is used in the master). After at most 100 mus, the slave will disable the pull-down event, and the master will start driving the bus for at least 100 mus after the event has been registered, after which the bus will restart.

Synchronization

When the system is powered up, the slave will need to establish synchronization with the master. This is achieved in the following way: (i) the master will send out a fixed sync pattern (zero to one transition) in each row; (ii) the master will define all bits in the frame except the time slots allocated for command acknowledgement and turnaround; (iii) when the slave PLL/DLL is in lock with the master, it responds with an activate "in lock slave" bit (see earlink, command section); and (iv) the master device can now program the slave device.

In one embodiment, a row includes 80 slots regardless of clock frequency and power mode. The synchronization pattern repeats at a frequency of one per row. The synchronization pattern is a zero to one transition. Only the first zero-to-one transition in a row/cycle is used by the slave PLL/DLL. Since the command slot immediately follows the synchronization slot, this means that there is initially only a single zero-to-transition in a row, and therefore the synchronization event of the PLL will be uniquely defined. The slave PLL/DLL circuit should be able to obtain a lock with the master within 1 ms as long as the rising clock edge is used for synchronization, and be able to output an internal "PLL/DLL in lock" signal to be used by other control circuits. Further, the PLL/DLL should expect a logic signal from the command controller ("message sync" signal). When the "message sync" signal is high and the slave PLL/DLL has determined that it is in lock, it should change to narrow bandwidth mode. In the narrow bandwidth mode, the time gate will only allow the output from the phase detector to be in a narrow time window around the synchronization edge. If either of these signals is not active (high), the PLL/DLL should change to wideband phase detection (i.e., disable the phase/delay detector window gating logic and disable the slave output transmitter to avoid bus collision). The master should read the device status and thereby detect when the slave has acquired a lock. Further, this message may be used to optimize the delay timing of the slave and should be completed before starting the port transfer.

After synchronization has been acquired, a window around the transition (e.g., +/-3 slots, half of the synchronization slot consisting of six slots) will be open to the PLL/DLL. The reason for using a narrow time window for the PLL is that the output from the phase detector that will be integrated by the PLL should not be confused by any data communication on the bus. Therefore, it is necessary to start the PLL with a wide receiver bandwidth, i.e. wide in the time domain, and to later gate the input time to the PLL integrated unit. Width of time door and windowThe degree depends on the width of the time slot, one of which is determined by one clock period of the slave PLL. With an internal clock frequency of about 294.912 MHz (3.072 MHz x 96), this translates to about +/-10.2 ns for a system that uses 6 slots to send one sync bit. This configuration will accept up to about 727_PSRMSFor a peak jitter of about 14 times this value (for 10)^-12Error rate).

Where applicable, the various embodiments provided by the present disclosure can be implemented using hardware, software, or a combination of hardware and software. Further, where applicable, the various hardware components and/or software components set forth herein may be combined into composite components comprising software, hardware, and/or both without departing from the spirit of the present disclosure. Where applicable, the various hardware components and/or software components set forth herein may be separated into sub-components comprising software, hardware, or both without departing from the scope of the present disclosure. Further, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

The foregoing disclosure is not intended to limit the disclosure to the precise forms or particular fields of use disclosed. Thus, it is contemplated that various alternative embodiments and/or modifications to the present disclosure, whether explicitly described or implied herein, are possible in light of the present disclosure. Having thus described embodiments of the present disclosure, persons of ordinary skill in the art will recognize that changes may be made in form and detail without departing from the scope of the disclosure. Accordingly, the disclosure is limited only by the claims.

Claims

1. A system, comprising:

a master device coupled to the multi-drop bus for digital communication using a communication protocol comprising a plurality of time slots; and

a first slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the master device in accordance with the communication protocol;

wherein at least one of the time slots is used to define a communication configuration for the first slave device to dynamically optimize bandwidth and/or signal integrity.

2. The system of claim 1, wherein the multi-drop bus is a differential data bus terminated at different voltage levels on the two lines, thereby facilitating low power operation and low electromagnetic interference.

3. The system of claim 2, wherein power consumption is reduced by operating at a signaling rate greater than a required signaling rate and idling the multi-drop bus for a portion of each cycle.

4. The system of claim 1, wherein the multi-drop bus is a multi-drop differential long length bus configured to receive a plurality of slave devices using a side transmitter.

5. The system of claim 1, wherein the multi-drop bus is further configured to synchronize two or more connected devices, including identifying time slots that do not change according to a desired fixed pattern and eliminating invalid locations for secure synchronization.

6. The system of claim 1, wherein the system is further configured to facilitate bulk data transfer independent of multi-drop bus digital communication traffic.

7. The system of claim 1, wherein the first and second slave devices connected to the bus are timed such that transmitted messages are sent as a sequence of forward or backward traveling waves, thereby enabling multi-branch high-speed bidirectional communication using terminated transmission lines.

8. The system of claim 1, wherein an intermediate node on the multi-drop bus is connected to the multi-drop bus with a short interrupt to a traveling wave; and is

Wherein the physical length of the interruption to the transmission line generated by the intermediate node is shorter than the shortest wavelength used for signaling.

9. The system of claim 1, wherein the delay between devices is measured by: charging the bus to a known value, disabling drivers at the beginning and end of the bus so that the bus floats and is not terminated during a measurement, waiting for the device to change the level on the bus, and measuring a transition delay.

10. The system of claim 1, wherein the system timing is obtained from a fractional PLL provided in the master device and/or the first slave device, and the PLL is dithered by adding an output from a pseudo-random generator to a fractional adder, thereby reducing EMI.

11. The system of claim 1, wherein the pseudo-random generator is configured to scramble the output of the one or more data ports, thereby achieving lower EMI by whitening the output spectrum.

12. The system of claim 1, wherein the PLL is configured to obtain a lock between the master device and the first slave device.

13. The system of claim 12, wherein the PLL includes a time gate that is enabled during initial lock of the PLL and later allows only synchronization information to pass to avoid the PLL locking onto random bus traffic.

14. The system of claim 1, wherein the DLL is to obtain a lock between the master device and one or more slave devices.

15. The system of claim 14 wherein the DLL includes a time gate that is enabled during an initial lock of the DLL and later allows only synchronization information to pass through to avoid the DLL locking onto random bus traffic.

16. A method, comprising:

providing a master device coupled to a multi-drop bus for digital communication using a communication protocol comprising a plurality of time slots;

coupling a first slave device to the multi-drop bus and configuring the slave device to transmit and receive digital communications with the master device according to the communication protocol; and

defining a communication configuration for the first slave device using at least one of the time slots to dynamically optimize bandwidth and/or signal integrity.

17. The method of claim 16, further comprising operating the multi-drop data bus as a differential data bus terminated with opposite polarities, thereby facilitating low power operation and low electromagnetic interference.

18. The method of claim 16, further comprising synchronizing two or more connected devices, including identifying time slots that do not change according to a desired fixed pattern and eliminating invalid locations for secure synchronization.

19. The method of claim 16, wherein the first and second slave devices connected to the bus are timed such that transmitted messages are sent as a sequence of forward or backward traveling waves, thereby enabling multi-branch high-speed bidirectional communication using terminated transmission lines.