CN112151594B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112151594B CN112151594B CN201910577014.2A CN201910577014A CN112151594B CN 112151594 B CN112151594 B CN 112151594B CN 201910577014 A CN201910577014 A CN 201910577014A CN 112151594 B CN112151594 B CN 112151594B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
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- 230000001105 regulatory effect Effects 0.000 claims abstract description 14
- 238000002513 implantation Methods 0.000 claims description 77
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- 229910052787 antimony Inorganic materials 0.000 claims description 14
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 14
- 229910052785 arsenic Inorganic materials 0.000 claims description 14
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 14
- 229910052698 phosphorus Inorganic materials 0.000 claims description 14
- 239000011574 phosphorus Substances 0.000 claims description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 11
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 11
- 229910052733 gallium Inorganic materials 0.000 claims description 11
- 229910052738 indium Inorganic materials 0.000 claims description 11
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 4
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- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229910052732 germanium Inorganic materials 0.000 description 6
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
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- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a well region is formed in the substrate, and first type ions are arranged in the well region; forming an inversion doped region and a threshold voltage regulating region in the fin part, wherein the threshold voltage regulating region is positioned at one side of the top of the fin part, the inversion doped region is positioned below the threshold voltage regulating region, the threshold voltage regulating region is internally provided with first type ions, and the inversion doped region is internally provided with second type ions; and forming an isolation structure on the substrate exposed by the fin part, wherein the isolation structure exposes the inverse doped region and the threshold voltage adjusting region. The threshold voltage adjusting region is formed on one side of the top of the fin portion, so that the current density of the top of the fin portion is reduced, and the channel of the device is far away from the surface of the fin portion through the inversion doping region, so that the problem of flicker noise is solved, and the starting voltage of the device meets the performance requirement; in conclusion, the performance of the device is improved through the inversion doped region and the threshold voltage adjusting region.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend toward very large scale integrated circuits, the feature size of integrated circuits continues to decrease. To accommodate the reduction in feature size, the channel length of the MOSFET is also correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely so-called short-channel effects (SCE), is more likely to occur.
Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of devices.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a well region is formed in the substrate, and first type ions are arranged in the well region; forming an inversion doping region and a threshold voltage adjusting region in the fin part, wherein the threshold voltage adjusting region is positioned at one side of the top of the fin part, the inversion doping region is positioned below the threshold voltage adjusting region, the threshold voltage adjusting region is internally provided with the first type of ions, and the inversion doping region is internally provided with the second type of ions, and the second type of ions is different from the first type of ions in conductivity type; and forming an isolation structure on the substrate exposed by the fin part, wherein the isolation structure exposes the inversion doping region and the threshold voltage adjusting region.
Optionally, the threshold voltage adjustment region is formed after the formation of the inversion doped region.
Optionally, before forming the inversion doped region, the method further includes: forming an isolation material layer on the substrate exposed by the fin part, wherein the isolation material layer covers the side wall of the fin part; the step of forming the inversion doped region includes: and performing inversion ion implantation on the isolation material layer and the top of the fin part.
Optionally, after forming the inversion doped region, before forming the threshold voltage adjusting region, the method further includes: removing part of the isolating material layer to form an initial isolating layer exposing the side wall of the fin part; the step of forming the threshold voltage adjustment region includes: and carrying out threshold voltage injection on the side wall of the fin part exposed from the initial isolation layer.
Optionally, the step of forming the isolation structure includes: and after the threshold voltage adjusting region is formed, removing part of the initial isolation layer with the thickness, and reserving the rest initial isolation layer as the isolation structure.
Optionally, before forming the inversion doped region, the method further includes: performing channel stop implantation on the isolation material layer and the top of the fin, and forming an anti-pass-through region in the fin, wherein the anti-pass-through region is internally provided with first type ions; in the step of forming the inversion doped region, the inversion doped region is located above the anti-punch-through region; in the step of forming the isolation structure, the isolation structure covers the side wall of the anti-penetration region.
Optionally, performing inversion ion implantation on the fin portion by using an ion implantation process to form the inversion doped region.
Optionally, performing threshold voltage implantation on the fin portion by using an ion implantation process to form the threshold voltage adjusting region.
Optionally, performing channel stop implantation on the fin portion by using an ion implantation process to form the anti-punch-through region.
Optionally, the implantation angle of the ion implantation process is 0 to 7 degrees.
Optionally, the implantation angle of the ion implantation process is 15 degrees to 20 degrees.
Optionally, the process parameters of the inversion ion implantation include: the second type of ion comprises one or more of boron, gallium and indium, the implantation energy is 6KeV to 30KeV, and the implantation dosage is 2E13 atoms/cm 2 To 1E15atom/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the Alternatively, the second type of ions comprises one or more of phosphorus, arsenic and antimony, the implantation energy is 15KeV to 50KeV, and the implantation dose is 2E13 atoms/cm 2 To 1E15atom/cm 2 。
Optionally, the threshold voltage injection process parameterThe number includes: the first type of ion comprises one or more of phosphorus, arsenic and antimony, the implantation energy is 7KeV to 25KeV, and the implantation dosage is 1E13atom/cm 2 To 5E14atom/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the Alternatively, the first type of ions comprises one or more of boron, gallium and indium, the implantation energy is 3KeV to 15KeV, and the implantation dose is 1E13atom/cm 2 To 5E14atom/cm 2 。
Optionally, in the step of forming the threshold voltage adjusting region, the threshold voltage adjusting region has a preset thickness; in the step of forming the isolation structure, the height of the fin portion exposed by the isolation structure is a preset height; the preset thickness is 1/5 to 1/3 of the preset height.
Optionally, after the isolation structure is formed, a distance from the top surface of the isolation structure to the bottom surface of the inversion doped region is 0nm to 30nm.
Optionally, in the step of providing a substrate, a fin mask layer is formed on top of the fin; in the step of forming the isolation material layer, the isolation material layer exposes the top of the fin mask layer; after forming the threshold voltage adjustment region, the method further comprises: and removing the fin part mask layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate, wherein a well region is formed in the substrate, and the well region is internally provided with first type ions; a fin protruding from the substrate; a threshold voltage adjustment region in the fin, the threshold voltage adjustment region being on a top side of the fin, the threshold voltage adjustment region having the first type of ions therein; an inversion doped region in the fin, the inversion doped region being located below the threshold voltage adjustment region, the inversion doped region having a second type of ion therein, the second type of ion being of a different conductivity type than the first type of ion; and the isolation structure is positioned on the substrate exposed by the fin part, and the isolation structure exposes the inversion doping region and the threshold voltage adjusting region.
Optionally, the semiconductor structure further includes: an anti-punch-through region in the fin below the anti-punch-through region, the anti-punch-through region having a first type of ion therein; the isolation structure covers the side wall of the anti-penetration region.
Optionally, the threshold voltage adjusting region has a preset thickness, the height of the fin portion exposed by the isolation structure is a preset height, and the preset thickness is 1/5 to 1/3 of the preset height.
Optionally, a distance from the top surface of the isolation structure to the bottom surface of the inversion doped region is 0nm to 30nm.
Optionally, the first type of ions comprises one or more of phosphorus, arsenic and antimony, and the doping concentration of the threshold voltage adjusting region is 1E18atom/cm 3 To 3E19atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the Alternatively, the first type of ions comprises one or more of boron, gallium and indium, and the threshold voltage adjusting region has a doping concentration of 1E18atom/cm 3 To 3E19atom/cm 3 。
Optionally, the second type of ions comprises one or more of phosphorus, arsenic and antimony, and the doping concentration of the inversion doped region is 2E18 atoms/cm 3 To 5E19atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the Alternatively, the second type of ions includes one or more of boron, gallium and indium, and the doping concentration of the inversely doped region is 2E18 atoms/cm 3 To 5E19atom/cm 3 。
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the inversion doped region and the threshold voltage regulating region are formed in the fin part, the threshold voltage regulating region is positioned at one side of the top of the fin part, the inversion doped region is positioned below the threshold voltage regulating region, and the threshold voltage regulating region is formed at one side of the top of the fin part so as to increase the starting voltage of the top position of the low fin part, thereby reducing the current density of the top position of the fin part and further improving the reliability of a device; in addition, by forming the inversion doping region, a device channel is far away from the surface of the fin part, so that the problem of flicker noise (noise) is solved, and the starting voltage at the position corresponding to the inversion doping region is reduced, so that the starting voltage of the device meets the performance requirement; in summary, through the inversion doped region and the threshold voltage adjusting region, the reliability and the flicker noise low-frequency noise performance of the device are improved, namely, the performance of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 8 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
At present, the performance of the device is still to be improved. The reason why the performance of the device is still to be improved in combination with a semiconductor structure analysis is now.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.
The semiconductor structure includes: a substrate 10; a fin 11 protruding from the substrate 10; a threshold voltage adjustment region 22 located in the fin 11; an anti-punch-through region 21 located in the fin 11 below the threshold voltage adjustment region 22; and the isolation structure 12 is positioned on the substrate 10 exposed by the fin part 11, and the threshold voltage adjusting region 22 is exposed by the isolation structure 12.
The fin 11 exposed by the isolation structure 12 serves as an effective fin for providing a channel of the formed fin field effect transistor, and the threshold voltage adjusting region 22 is mainly located in the middle of the effective fin, so that the doping concentration of the threshold voltage adjusting region 22 is lower near the top of the fin 11 (as shown by the dotted line circle a in fig. 1). However, near the top of the fin 11, the electric field strength in the channel is high, and accordingly, the on-current is high at this position, and particularly, the on-current is high at the top corner of the fin 11, which tends to lower the reliability of the device and also to deteriorate the low-frequency noise.
Further, since the fin 11 is liable to have a problem of surface defects, a reaction occurs between the device channel and the surface of the fin 11, thereby generating flicker noise.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a well region is formed in the substrate, and first type ions are arranged in the well region; forming an inversion doping region and a threshold voltage adjusting region in the fin part, wherein the threshold voltage adjusting region is positioned at one side of the top of the fin part, the inversion doping region is positioned below the threshold voltage adjusting region, the threshold voltage adjusting region is internally provided with the first type of ions, and the inversion doping region is internally provided with the second type of ions, and the second type of ions is different from the first type of ions in conductivity type; and forming an isolation structure on the substrate exposed by the fin part, wherein the isolation structure exposes the inversion doping region and the threshold voltage adjusting region.
According to the embodiment of the invention, the inversion doped region and the threshold voltage regulating region are formed in the fin part, the threshold voltage regulating region is positioned at one side of the top of the fin part, the inversion doped region is positioned below the threshold voltage regulating region, and the threshold voltage regulating region is formed at one side of the top of the fin part so as to increase the starting voltage of the top position of the fin part, thereby reducing the current density of the top position of the fin part and further improving the reliability of a device; in addition, the inversion doping region is formed, so that a device channel is far away from the surface of the fin part, the problem of flicker noise is solved, and the starting voltage at the position corresponding to the inversion doping region is reduced, so that the starting voltage of the device meets the performance requirement; in summary, through the inversion doped region and the threshold voltage adjusting region, the reliability and flicker noise performance of the device are improved, i.e. the performance of the device is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 to 8 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a base is provided, including a substrate 100 and a fin 110 protruding from the substrate 100, wherein a well region 105 is formed in the substrate 100, and the well region 105 has first type ions therein.
The substrate 100 is used to provide a process platform for the subsequent formation of fin field effect transistors.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
The fin 110 is used to provide a channel for the formed fin field effect transistor.
In this embodiment, the fin 110 and the substrate 100 are integrally formed. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
For this reason, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
In this embodiment, a well region 105 is formed in the fin 110 and the substrate 100, and the well region 105 has first type ions therein.
Wherein when the semiconductor structure is a PMOS transistor, the first type of ions is an N-type ion comprising one or more of phosphorus, arsenic, and antimony; when the semiconductor structure is an NMOS transistor, the first type of ions is P-type ions, which include one or more of boron, gallium, and indium.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the first type of ions are P-type ions.
It should be noted that, a fin mask layer 150 is further formed on top of the fin 110, and the fin mask layer 150 is used as an etching mask for forming the substrate 100 and the fin 110.
In this embodiment, the fin mask layer 150 is made of silicon nitride.
Referring to fig. 3 to 7 in combination, an inversion doped region 320 (as shown in fig. 5) and a threshold voltage adjustment region 330 (as shown in fig. 5) are formed in the fin 110, the threshold voltage adjustment region 330 is located at a top side of the fin 110, the inversion doped region 320 is located below the threshold voltage adjustment region 330, the threshold voltage adjustment region 330 has the first type of ions therein, and the inversion doped region 320 has the second type of ions therein, which are different from the first type of ions in conductivity type.
The subsequent process further comprises: an isolation structure is formed on the substrate, the isolation structure exposes the counter doped region 320 and the threshold voltage adjustment region 330, and the fin 110 exposed by the isolation structure is used as an effective fin. In the embodiment, the inversion doped region 320 and the threshold voltage adjusting region 330 are formed in the effective fin portion, and the threshold voltage adjusting region 330 is formed on one side of the top of the fin portion 110 to increase the turn-on voltage at the top of the fin portion 110, so as to reduce the current density at the top of the fin portion 110, and further improve the reliability of the device; moreover, by forming the inversion doped region 320, the device channel is far away from the surface of the fin portion 110, so as to improve the problem of flicker noise, and simultaneously, the turn-on voltage at the position corresponding to the inversion doped region 320 is reduced, so that the turn-on voltage of the device meets the performance requirement; for this reason, the reliability and flicker noise performance of the device, i.e., the performance of the device, are improved by the inversion doped region 320 and the threshold voltage adjusting region 330.
In this embodiment, the threshold voltage adjusting region 330 is formed after the formation of the inversion doped region 320. The inversion doped region 320 is located below the threshold voltage adjusting region 330, which is advantageous to simplify the process complexity and to improve the formation quality of the inversion doped region 320 and the threshold voltage adjusting region 330 by forming the inversion doped region 320 first.
As shown in fig. 3, before forming the inversion doped region 320, the method further includes: an isolation material layer 200 is formed on the substrate 100 exposed by the fin 110, and the isolation material layer 200 covers the sidewalls of the fin 110.
The isolation material layer 200 can protect the substrate 100, and is beneficial to reducing the probability of doping ions into the substrate 100 during the process of forming the inversion doped region 320, thereby reducing the influence on the normal performance of the device.
Furthermore, the isolation material layer 200 is used to provide for the subsequent formation of isolation structures.
Therefore, by adopting the isolation material layer 200, an additional step of forming a protective layer for protecting the substrate 100 is omitted, modification of the existing process is small, process compatibility is high, and process cost and process time are saved.
Correspondingly, the material of the isolation material layer 200 is a dielectric material.
In this embodiment, the material of the isolation material layer 200 is silicon oxide. In other embodiments, the material of the isolation layer may also be silicon nitride or other dielectric materials such as silicon oxynitride.
Specifically, the step of forming the isolation material layer 200 includes: forming an initial isolation material layer (not shown) on the substrate 100 exposed by the fin 110 through a deposition process, wherein the initial isolation material layer covers the top of the fin mask layer 150; and flattening the initial isolation material layer, removing the initial isolation material layer higher than the top of the fin mask layer 150, and taking the rest of the initial isolation material layer as the isolation material layer 200. That is, after the isolation material layer 200 is formed, the isolation material layer 200 exposes the top of the fin mask layer 150.
In this embodiment, the deposition step employs an FCVD (flowable chemical vapor deposition ) process. The FCVD process has a good filling capability, which is beneficial to reducing the probability of forming defects such as voids in the isolation material layer 200, and is correspondingly beneficial to improving the isolation effect of the isolation material layer 200.
In this embodiment, the planarization process is performed by using a chemical mechanical polishing process. In the chemical mechanical polishing process, the top surface of the fin mask layer 150 is used as a stop position, so that the isolation material layer 200 has a higher top surface flatness.
As shown in fig. 4, in this embodiment, after the isolation material layer 200 is formed, before the forming of the inversion doped region 320, the method further includes: a channel stop implant (channel stop implant) 315 is performed on top of the isolation material layer 200 and the fin 110, and an anti-punch-through region 310 is formed in the fin 110, the anti-punch-through region 310 having ions of a first type therein.
The subsequent process further comprises: forming a gate structure across the fin 110; and forming source-drain doped regions on two sides of the gate structure. The anti-punch-through region 310 is used to prevent punch-through between the source region and the drain region in the source-drain doped region.
Therefore, the doping ion type of the anti-punch-through region 310 is different from the doping ion type of the source/drain doping region, that is, the doping ion type of the anti-punch-through region 310 is the same as the doping ion type of the well region 105, and the anti-punch-through region 310 has the first type of ions therein.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the first type of ions is P-type ions, i.e. the doping ion type of the anti-punch-through region 310 is P-type ions.
In this embodiment, an ion implantation process is used to perform a channel stop implantation 315 on top of the isolation material layer 200 and the fin 110, so as to form the anti-punch-through region 310.
Because the width of fin 210 is smaller, isolation material layer 200 is also doped during channel stop implant 315, and after channel stop implant 315, the dopant ions in isolation material layer 200 can diffuse into fin 110 along a direction perpendicular to the sidewall of fin 110, which is advantageous for improving the uniformity of the dopant concentration of anti-punch-through region 310 in the width direction of fin 210.
Moreover, the ion implantation process is simple, and the doping concentration of the anti-punch-through region 310 can be easily made to meet the process requirement by adjusting the implantation dosage.
The implantation angle of the ion implantation process is not preferably too large. If the implantation angle is too large, the implantation depth of the channel stop implant 315 is too small, which may cause difficulty in forming the anti-punch-through region 310 at the target location, which may not only reduce the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source-drain doped region, but also easily cause the anti-punch-through region 310 to occupy the position of other doped regions in the fin 110, and further easily cause too close a distance between the anti-punch-through region 310 and the transistor channel, and the dopant ions of the anti-punch-through region 310 may affect mobility of carriers in the channel, thereby affecting normal performance of the transistor. For this reason, in the present embodiment, the implantation angle of the ion implantation process is 0 to 7 degrees during the channel stop implantation 315. Wherein the implantation angle is an angle between an implantation direction and a surface normal of the substrate 100. For example: the implantation angle of the ion implantation process is 0 degrees.
The implantation energy of the ion implantation process is not too small nor too large. If the implantation energy is too small, it may easily cause the implantation depth of the channel stop implant 315 to be too small, i.e., it may easily cause the anti-punch-through region 310 to be difficult to form at the target location, which may not only reduce the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source-drain doped region, but also easily cause the anti-punch-through region 310 to occupy the position of other doped regions in the fin 110, and further easily cause the distance between the anti-punch-through region 310 and the transistor channel to be too close, where the dopant ions of the anti-punch-through region 310 may affect the mobility of carriers in the channel, thereby affecting the performance of the device transistor; if the implant energy is too high, it can easily result in an excessive depth of the channel stop implant 315, which can also easily result in the anti-punch-through region 310 not being formed at the target location, thereby affecting the function of the anti-punch-through region 310 and the device performance. For this reason, in the present embodiment, when the doping ion type of the anti-punch-through region 310 is P-type ion, the implantation energy is 12KeV to 45KeV.
The implantation dose of the ion implantation process is not too small or too large. If the implantation dose is too small, the doping concentration of the anti-punch-through region 310 is too low, so that the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source-drain doped region is easily reduced; doped ion capacity in the anti-punch-through region 310 if the implant dose is too large Diffusion is likely to occur toward the top of the fin 110, thereby easily affecting the normal performance of the device. For this reason, in the present embodiment, when the doping ion type of the anti-punch-through region 310 is P-type ion, the implantation dose is 1E14atom/cm 2 To 1E15atom/cm 2 。
In other embodiments, when the semiconductor structure is a PMOS transistor, the first type ion is an N type ion, and the process parameters of the channel stop implant correspondingly include: the first type of ion comprises one or more of phosphorus, arsenic and antimony, the implantation energy is 25KeV to 65KeV, and the implantation dosage is 5E13 atoms/cm 2 To 1E15atom/cm 2 。
It should be noted that, in the process of performing the channel stop implantation 315 by using the ion implantation process, the fin mask layer 150 is formed on the top of the fin 110, and the fin mask layer 150 can protect the top of the fin 110, so as to reduce the damage of the ion implantation process to the top of the fin 110.
Referring to fig. 5, an inversion ion implantation 325 is performed on top of the isolation material layer 200 and the fin 110 to form an inversion doped region 320, where the inversion doped region 320 is located above the anti-punch-through region 310.
The counter doped region 320 has a second type of ion therein, and the doped ion type of the counter doped region 320 is different from the doped ion type of the well region 105. Through the inversion doped region 320, the device channel is made to be far away from the surface of the fin 110 when the device is in operation, thereby improving the problem of flicker noise and reducing the turn-on voltage at the position of the inversion doped region 320.
In this embodiment, since the dopant ions diffuse in the fin 110 in a direction perpendicular to the surface of the substrate 100, the bottom surface of the anti-punch-through region 310 is flush with the top surface of the anti-punch-through region 320. In other embodiments, the top surface of the inversely doped region may also be higher than the top surface of the anti-punch-through region.
In this embodiment, after the anti-punch-through region 310 is formed, the inversion doped region 320 is formed, so as to avoid the process of forming the anti-punch-through region 310 from affecting the doping concentration and the doping ion distribution of the inversion doped region 320.
The counter doped region 320 has a second type of ion therein, and the doped ion type of the counter doped region 320 is different from the doped ion type of the well region 105.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the doping ion type of the inversion doped region 320 is N-type ion, and the second type ion includes one or more of phosphorus, arsenic and antimony.
In this embodiment, an ion implantation process is used to perform an inversion ion implantation 325 on the isolation material layer 200 and the top of the fin 110, so as to form the inversion doped region 320.
The implantation angle of the ion implantation process is not preferably too large. If the implantation angle is too large, the implantation depth of the channel stop implant 315 is easily caused to be too small, thereby affecting the formation position and thickness of the inversion doped region 320, and also easily causing the inversion doped region 320 to occupy the position of other doped regions in the fin 110, which is disadvantageous for improving the performance of the device. For this reason, in the present embodiment, the implantation angle of the ion implantation process is 0 to 7 degrees during the inversion ion implantation 325. Wherein the implantation angle is an angle between an implantation direction and a surface normal of the substrate 100. For example: the implantation angle of the ion implantation process is 0 degrees.
The implantation energy of the ion implantation process is not too small nor too large. If the implantation energy is too small, the depth of the bottom surface of the inversion doped region 320 in the fin portion 110 is easily caused to be too small, so that the formation position and thickness of the inversion doped region 320 are affected, and the inversion doped region 320 occupies the positions of other doped regions in the fin portion 110, which is not beneficial to improving the problem of flicker noise and the overall performance of the device; if the implant energy is too high, it is also likely to cause the counter doped region 320 to fail to form at the target location, thereby affecting the function of the counter doped region 3200 and the performance of the device. For this reason, in the present embodiment, when the doping ion type of the inversion doped region 320 is N-type ion, the implantation energy is 15KeV to 50KeV.
The implantation dose of the ion implantation process is not too small or too large. If the implant dose is too small, the doping concentration of the inversion doped region 320 is too low, thereby reducing the effect of the inversion doped region 320 for improving the flicker noise problem; if the implant dose is too large, dopant ions in the counter doped region 320 tend to diffuse into the channel, resulting in a device with too high an on-voltage. For this reason, in the present embodiment, when the doping ion type of the inversion doped region 320 is N-type ion, the implantation dose is 2E13 atoms/cm 2 To 1E15atom/cm 2 。
In other embodiments, when the semiconductor structure is a PMOS transistor, the second type of ions are P-type ions, and the process parameters of the inversion ion implantation include: the second type of ion comprises one or more of boron, gallium and indium, the implantation energy is 6KeV to 30KeV, and the implantation dosage is 2E13 atoms/cm 2 To 1E15atom/cm 2 。
Referring to fig. 6 and 7 in combination, a threshold voltage adjustment region 330 is formed in the fin 110 (as shown in fig. 7), wherein the threshold voltage adjustment region 330 is located above the inversion doped region 320.
The threshold voltage adjustment region 330 is used to adjust the threshold voltage of the transistor.
Since the electric field intensity in the channel is larger near the top of the fin 110, the current density is larger at this position, especially at the top corner of the fin 110, which tends to lower the reliability of the device and also to deteriorate the flicker noise performance. Therefore, by forming the threshold voltage adjusting region 330 on the top side of the fin 110, the turn-on voltage of the top position of the fin 110 is increased, thereby reducing the current density of the top position of the fin 110 and further improving the reliability of the device.
Wherein, the turn-on voltage at the position of the inversion doped region 320 is reduced by the inversion doped region 320, so that the turn-on voltage of the device can meet the performance requirement.
In this embodiment, the threshold voltage adjusting region 330 is located above the inversion doped region 320, so that the threshold voltage adjusting region 330 is formed after the inversion doped region 320 is formed, thereby avoiding the process of forming the inversion doped region 320 and the anti-punch-through region 310 from affecting the doping concentration and the distribution of the doping ions of the threshold voltage adjusting region 330.
The threshold voltage adjusting region 330 has the first type of ions therein, and the doping ion type of the threshold voltage adjusting region 330 is the same as the doping ion type of the well region 105.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the doping ion type of the threshold voltage adjusting region 330 is P-type ion correspondingly.
In this embodiment, an ion implantation process is used to perform threshold voltage implantation 335 on the fin 110, so as to form the threshold voltage adjusting region 330.
As shown in fig. 6, since the isolation material layer 200 is formed on the substrate 100 (as shown in fig. 5), after the formation of the inversion doped region 320, before the formation of the threshold voltage adjusting region 330, the method further comprises: and removing part of the thickness of the isolation material layer 200 to form an initial isolation layer 210 exposing part of the side wall of the fin 110.
The initial isolation layer 210 exposes a portion of the sidewalls of the fin 110 to define an area of the fin 110 for forming the threshold voltage adjustment region 330, thereby providing for a subsequent formation of the threshold voltage adjustment region 330.
In this embodiment, a dry etching process is used to etch a portion of the thickness of the isolation material layer 200 to form the initial isolation layer 210. The dry etching process has anisotropic etching characteristics, which is advantageous in controlling the removal amount of the isolation material layer 200 and in improving the surface flatness of the initial isolation layer 210.
When the fin 110 is subjected to the subsequent threshold voltage implantation, the dopant ions longitudinally diffuse along the direction from the top of the fin 110 to the bottom of the fin 110, so that the threshold voltage adjusting region 330 is formed in the fin 110. To reduce the impact on the counter doped region 320, the initial isolation structure 210 covers at least the sidewalls of the counter doped region 320, i.e., the initial isolation structure 210 top surface is flush with the counter doped region 320 top surface, or the initial isolation structure 210 top surface is higher than the counter doped region 320 top surface.
Moreover, the subsequent steps further comprise: and forming an isolation structure on the substrate 100 exposed by the fin portion 110, wherein the isolation structure covers part of the side wall of the fin portion 110. In the step of forming the isolation structure, the height of the fin portion 110 exposed by the isolation structure is a preset height, and in the step of forming the threshold voltage adjusting region 330, the threshold voltage adjusting region 330 has a preset thickness, and the ratio of the preset thickness to the preset height is not too small, but not too large. If the ratio is too small, the effect of the threshold voltage adjustment region 330 for reducing the current density at the top of the fin 110 is easily reduced; if the ratio is too large, the formation location of the inversely doped region 320 in the fin 110 is easily affected, thereby affecting the effect of the inversely doped region 320. For this purpose, in this embodiment, the preset thickness is 1/5 to 1/3 of the preset height.
Correspondingly, the height of the fin portion 110 exposed by the initial isolation structure 210 is reasonably set according to the ratio of the preset thickness to the preset height.
As shown in fig. 7, the step of forming the threshold voltage adjusting region 330 includes: and carrying out threshold voltage injection 335 on the side wall of the fin portion 110 exposed by the initial isolation layer 210.
By performing the threshold voltage implant 335 on the fin 110 sidewall, the formation position of the threshold voltage adjustment region 330 is convenient to control, and the diffusion uniformity of the dopant ions of the threshold voltage adjustment region 330 in the fin 110 is improved.
In this embodiment, an ion implantation process is used to perform threshold voltage implantation 335 on the fin 110 sidewall, and an implantation direction of the ion implantation process forms an included angle with a normal direction of the substrate 100, where the included angle is an acute angle, so that threshold voltage implantation 335 is performed on the fin 110 sidewall.
The implantation angle of the ion implantation process is not too small or too large. If the implantation angle is too small, ions are easily implanted into the inversion doped region 320, which not only affects the quality of the formation of the threshold voltage adjustment region 330 in the fin 110, but also affects the function of the inversion doped region 320; if the implantation angle is too large, it may easily result in too small an implantation depth of the threshold voltage implant 335, which may be detrimental to reducing the current density at the top of the fin 110. For this reason, in the present embodiment, the implantation angle of the ion implantation process is 15 degrees to 20 degrees.
The implantation energy of the ion implantation process is not too small nor too large. If the implantation energy is too small, the formation position and thickness of the threshold voltage adjusting region 330 are easily affected, which is not beneficial to reducing the current density at the top of the fin 110; if the implantation energy is too large, it is easy to cause the threshold voltage adjusting region 330 not to be formed at the target location, and it is also easy to cause the threshold voltage adjusting region 330 to occupy the position of other doped regions in the fin 110, thereby adversely affecting the performance of the device. For this reason, in the present embodiment, when the doping ion type of the threshold voltage adjusting region 330 is P-type ion, the implantation energy is 3KeV to 15KeV.
The implantation dose of the ion implantation process is not too small or too large. If the implant dose is too small, the doping concentration of the threshold voltage adjustment region 330 is too low, which is detrimental to reducing the current density at the top of the fin 110; if the implant dose is too large, it is likely that the turn-on voltage of the device will not meet the performance requirements. For this reason, in the present embodiment, when the doping ion type of the threshold voltage adjusting region 330 is P-type ion, the implantation dose is 1E13atom/cm 2 To 5E14atom/cm 2 。
In other embodiments, when the semiconductor structure is a PMOS transistor, the process parameters of the threshold voltage implant include: the implantation ions comprise one or more of phosphorus, arsenic and antimony, the implantation energy is 7KeV to 25KeV, and the implantation dosage is 1E13atom/cm 2 To 5E14atom/cm 2 。
Referring to fig. 8, an isolation structure 220 is formed on the substrate 100 exposed by the fin 110, and the isolation structure 220 exposes the inversion doped region 320 and the threshold voltage adjusting region 330.
The isolation structures 220 act as Shallow Trench Isolation (STI) structures to isolate adjacent devices. In this embodiment, the material of the isolation structure 220 is silicon oxide. In other embodiments, the material of the isolation structure 220 may be silicon nitride or silicon oxynitride, or other insulating materials.
In this embodiment, the step of forming the isolation structure 220 includes: after the threshold voltage adjusting region 330 is formed, an etching back (etching back) process is performed on the initial isolation layer 210, a portion of the initial isolation layer 210 (as shown in fig. 7) is removed, and the remaining initial isolation layer 210 remains as the isolation structure 220.
In this embodiment, after the isolation structure 220 is formed, the isolation structure 220 covers the anti-punch-through region 310 to prevent the doped ions in the anti-punch-through region 310 from diffusing into the channel toward the top of the fin 110. For example: the top surface of the isolation structure 220 is flush with the top surface of the anti-punch-through region 310, or the top surface of the isolation structure 220 is higher than the top surface of the anti-punch-through region 310.
However, when the top of the isolation structure 220 is higher than the top of the anti-punch-through region 310, the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch-through region 310 is not too large. If the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch-through region 310 is too large, the distance between the anti-punch-through region 310 and the channel is too large, and the anti-punch-through region 310 is used for preventing the punch-through between the source region and the drain region in the source-drain doped region from being correspondingly deteriorated, which adversely affects the performance of the device.
For this purpose, in this embodiment, the distance from the top surface of the isolation structure 220 to the top of the anti-punch-through region 310 is 0nm to 10nm.
In this embodiment, after the isolation structure 220 is formed, the top surface of the isolation structure 220 is flush with the bottom surface of the counter doped region 320, or the top surface of the isolation structure 220 is lower than the bottom surface of the counter doped region 320.
However, when the top surface of the isolation structure 220 is lower than the bottom surface of the counter doped region 320, the distance from the top surface of the isolation structure 220 to the bottom surface of the counter doped region 320 should not be too large. If the distance from the top surface of the isolation structure 220 to the bottom surface of the counter doped region 320 is too small, the thickness of the counter doped region 320 is too small, which tends to make the counter doped region 320 play an insignificant role.
For this purpose, in this embodiment, the distance from the top surface of the isolation structure 220 to the bottom surface of the inversion doped region 320 is 0nm to 30nm.
In this embodiment, a fin mask layer 150 (as shown in fig. 7) is further formed on top of the fin 110, so before performing the etching back process on the initial isolation layer 210, the method further includes: the fin mask layer 150 is removed. In other embodiments, the fin mask layer may also be removed after the isolation structure is formed.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 8, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100, wherein a well region 105 is formed in the substrate 100, and the well region 105 has first type ions therein; a fin 110 protruding from the substrate 100; a threshold voltage adjustment region 330 in the fin 110, the threshold voltage adjustment region 330 being located on a top side of the fin 110, the threshold voltage adjustment region 330 having the first type of ions therein; an inversion doped region 320 in the fin 110, the inversion doped region 320 being located below the threshold voltage adjustment region 330, the inversion doped region 320 having a second type of ion therein, the second type of ion being of a different conductivity type than the first type of ion; and the isolation structure 220 is positioned on the substrate 100 exposed by the fin portion 110, and the isolation structure 220 exposes the inversion doped region 320 and the threshold voltage adjusting region 330.
The semiconductor structure is a finfet, and the substrate 100 is used to provide a process platform for the finfet.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
The fin 110 is used to provide a channel for the formed fin field effect transistor.
In this embodiment, the fin 110 and the substrate 100 are integrally formed. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
For this reason, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
In this embodiment, a well region 105 is formed in the fin 110 and the substrate 100, and the well region 105 has first type ions therein.
Wherein when the semiconductor structure is a PMOS transistor, the first type of ions is an N-type ion comprising one or more of phosphorus, arsenic, and antimony; when the semiconductor structure is an NMOS transistor, the first type of ions is P-type ions, which include one or more of boron, gallium, and indium.
In this embodiment, taking the semiconductor structure as an NMOS transistor as an example, the first type of ions is P-type ions.
The isolation structure 220 serves as a shallow trench isolation structure for isolating adjacent devices. In this embodiment, the material of the isolation structure 220 is silicon oxide. In other embodiments, the material of the isolation structure 220 may be silicon nitride or silicon oxynitride, or other insulating materials.
The threshold voltage adjustment region 330 is used to adjust the threshold voltage of the transistor.
Since the electric field intensity in the channel is larger near the top of the fin 110, the current density is larger at this position, especially at the top corner of the fin 110, which tends to lower the reliability of the device and also to deteriorate the flicker noise. Therefore, by forming the threshold voltage adjusting region 330 on the top side of the fin 110, the turn-on voltage of the top position of the fin 110 is increased, thereby reducing the current density of the top position of the fin 110 and further improving the reliability of the device.
The threshold voltage adjusting region 330 has the first type of ions therein, and the doping ion type of the threshold voltage adjusting region 330 is the same as the doping ion type of the well region 105.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the doping ion type of the threshold voltage adjusting region 330 is P-type ion, that is, the first type ion includes one or more of boron, gallium and indium.
The doping concentration of the threshold voltage adjusting region 330 is not too small or too large. If the doping concentration of the threshold voltage adjustment region 330 is too small, this is detrimental to reducing the current density at the top of the fin 110; if the doping concentration of the threshold voltage adjusting region 330 is too high, the device turn-on voltage is liable to fail to meet the performance requirement. For this reason, in the present embodiment, when the doping ion type of the threshold voltage adjusting region 330 is P-type ion, the doping concentration of the threshold voltage adjusting region 330 is 1E18atom/cm 3 To 3E19atom/cm 3 。
In other embodiments, when the semiconductor structure is a PMOS transistor, the first type of ions includes one or more of phosphorus, arsenic, and antimony, and the threshold voltage adjustment region has a doping concentration of 1E18 atoms/cm 3 To 3E19atom/cm 3 。
The threshold voltage adjusting region 330 has a predetermined thickness, the exposed fin portion 110 of the isolation structure has a predetermined height, and the ratio of the predetermined thickness to the predetermined height is not too small or too large. If the ratio is too small, the effect of the threshold voltage adjustment region 330 for reducing the current density at the top of the fin 110 is easily reduced; if the ratio is too large, it is easy to affect the inversely doped region 320, thereby affecting the function of the inversely doped region 320. For this purpose, in this embodiment, the preset thickness is 1/5 to 1/3 of the preset height.
The inversion doped region 320 is located below the threshold voltage adjustment region 330.
The counter doped region 320 has a second type of ion therein, and the doped ion type of the counter doped region 320 is different from the doped ion type of the well region 105. Through the inversion doped region 320, the device channel is made to be far away from the surface of the fin 110 when the device is operated, thereby improving the problem of flicker noise.
In addition, since the threshold voltage adjusting region 330 is formed on the top side of the fin 110, the turn-on voltage of the top position of the fin 110 is increased, and the turn-on voltage of the position of the inversion doped region 320 is reduced by the inversion doped region 320, the turn-on voltage of the device can meet the performance requirement through the inversion doped region 320.
In this embodiment, taking the semiconductor structure as an NMOS transistor as an example, the doping ion type of the inversion doped region 320 is N-type ion, that is, the second type ion includes one or more of phosphorus, arsenic and antimony.
The doping concentration of the counter doped region 320 is not too small nor too large. If the doping concentration of the inversion doping region 320 is too small, the effect of the inversion doping region 320 for improving the flicker noise problem is easily reduced; if the doping concentration of the counter doped region 320 is too high, dopant ions in the counter doped region 320 are easily caused to diffuse into the channel, resulting in an excessively high turn-on voltage of the device. For this reason, in the present embodiment, when the doping ion type of the counter doping region 320 is N-type, the doping concentration of the counter doping region 320 is 2E18 atoms/cm 3 To 5E19atom/cm 3 。
In other embodiments, when the semiconductor structure is a PMOS transistor, the second type of ions is P-type ions, the second type of ions includes one or more of boron, gallium and indium, and the doping concentration of the inversion doped region is 2E18 atoms/cm 3 To 5E19atom/cm 3 。
In this embodiment, the semiconductor structure further includes: an anti-punch-through region 310 is located in the fin 110 below the anti-punch-through region 320, the anti-punch-through region 310 having ions of a first type therein.
The semiconductor structure typically further comprises: a gate structure crossing the fin 110 and covering a portion of the top and a portion of the sidewall of the fin 110; and the source-drain doped region is positioned in the fin parts at two sides of the grid electrode structure. The anti-punch-through region 310 is used to prevent punch-through between the source region and the drain region in the source-drain doped region.
Therefore, the doping ion type of the anti-punch-through region 310 is different from the doping ion type of the source/drain doping region, that is, the doping ion type of the anti-punch-through region 310 is the same as the doping ion type of the well region 105, and the anti-punch-through region 310 has the first type of ions therein.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the first type of ions is P-type ions, i.e. the doping ion type of the anti-punch-through region 310 is P-type ions.
The doping concentration of the anti-punch-through region 310 is not too small or too large. If the doping concentration of the anti-punch-through region 310 is too small, the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source-drain doped region is easily reduced; if the doping concentration of the anti-punch-through region 310 is too high, the dopant ions in the anti-punch-through region 310 are easy to diffuse toward the top of the fin 110, so that the normal performance of the device is easy to be affected. For this reason, in the present embodiment, when the doping ion type of the anti-punch-through region 310 is P-type, the doping concentration of the anti-punch-through region 310 is 3E18 atoms/cm 3 To 3E19atom/cm 3 。
In other embodiments, when the semiconductor structure is a PMOS transistor, the first type of ions is N-type ions, the first type of ions includes one or more of phosphorus, arsenic and antimony, and the anti-punch-through region has a doping concentration of 3E18 atoms/cm 3 To 3E19atom/cm 3 。
In this embodiment, the isolation structure 220 covers the anti-punch-through region 310 to prevent the dopant ions in the anti-punch-through region 310 from diffusing into the channel toward the top of the fin 110. For example: the top surface of the isolation structure 220 is flush with the top surface of the anti-punch-through region 310, or the top surface of the isolation structure 220 is higher than the top surface of the anti-punch-through region 310.
However, when the top of the isolation structure 220 is higher than the top of the anti-punch-through region 310, the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch-through region 310 is not too large. If the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch-through region 310 is too large, the distance between the anti-punch-through region 310 and the channel is too large, and the anti-punch-through region 310 is used for preventing the punch-through between the source region and the drain region in the source-drain doped region from being correspondingly deteriorated, which adversely affects the performance of the device.
For this reason, in the present embodiment, the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch-through region 310 is 0nm to 10nm.
In this embodiment, the top surface of the isolation structure 220 is flush with the bottom surface of the counter doped region 320, or the top surface of the isolation structure 220 is lower than the bottom surface of the counter doped region 320.
However, when the top surface of the isolation structure 220 is lower than the bottom surface of the counter doped region 320, the distance from the top surface of the isolation structure 220 to the bottom surface of the counter doped region 320 should not be too large. If the distance from the top surface of the isolation structure 220 to the bottom surface of the counter doped region 320 is too small, the thickness of the counter doped region 320 is too small, which tends to make the counter doped region 320 play an insignificant role.
For this purpose, in this embodiment, the distance from the top surface of the isolation structure 220 to the bottom surface of the inversion doped region 320 is 0nm to 30nm.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (12)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a well region is formed in the substrate, and first type ions are arranged in the well region;
forming an isolation material layer on the substrate exposed by the fin part, wherein the isolation material layer covers the whole side wall of the fin part;
after the isolation material layer is formed, an inversion doping region and a threshold voltage adjusting region are formed in the fin portion, the threshold voltage adjusting region is located at one side of the top of the fin portion, the inversion doping region is located below the threshold voltage adjusting region, the threshold voltage adjusting region is internally provided with the first type ions, the inversion doping region is internally provided with the second type ions, and the second type ions are different from the first type ions in conductivity type;
the step of forming the inversion doped region includes: performing inversion ion implantation on the isolation material layer and the top of the fin part;
after forming the inversion doped region, before forming the threshold voltage adjusting region, the method further comprises: removing part of the isolating material layer to form an initial isolating layer exposing the side wall of the fin part;
The step of forming the threshold voltage adjustment region includes: threshold voltage injection is conducted on the side wall of the fin portion exposed out of the initial isolation layer;
and after the threshold voltage regulating region is formed, removing part of the initial isolation layer with the thickness, and reserving the rest initial isolation layer as an isolation structure, wherein the isolation structure exposes the inversion doping region and the threshold voltage regulating region.
2. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the inversion doped region: performing channel stop implantation on the isolation material layer and the top of the fin, and forming an anti-pass-through region in the fin, wherein the anti-pass-through region is internally provided with first type ions;
in the step of forming the inversion doped region, the inversion doped region is located above the anti-punch-through region; in the step of forming the isolation structure, the isolation structure covers the side wall of the anti-penetration region.
3. The method of claim 1, wherein the fin is subjected to an inversion ion implantation process to form the inversion doped region.
4. The method of claim 1, wherein the threshold voltage adjustment region is formed by performing a threshold voltage implant on the fin using an ion implantation process.
5. The method of claim 2, wherein the fin is subjected to a channel stop implant by an ion implantation process to form the anti-punch-through region.
6. The method of forming a semiconductor structure according to claim 3 or 5, wherein an implantation angle of the ion implantation process is 0 degrees to 7 degrees.
7. The method of forming a semiconductor structure of claim 4, wherein an implantation angle of the ion implantation process is 15 degrees to 20 degrees.
8. The method of forming a semiconductor structure of claim 3, wherein the process parameters of the inversion ion implantation comprise: the second type of ion comprises one or more of boron, gallium and indium, the implantation energy is 6KeV to 30KeV, and the implantation dosage is 2E13 atoms/cm 2 To 1E15atom/cm 2 ；
Or alternativelyThe second type of ion comprises one or more of phosphorus, arsenic and antimony, the implantation energy is 15KeV to 50KeV, and the implantation dosage is 2E13atom/cm 2 To 1E15atom/cm 2 。
9. The method of forming a semiconductor structure of claim 4, wherein the threshold voltage implant process parameters comprise: the first type of ion comprises one or more of phosphorus, arsenic and antimony, the implantation energy is 7KeV to 25KeV, and the implantation dosage is 1E13atom/cm 2 To 5E14atom/cm 2 ；
Alternatively, the first type of ions comprises one or more of boron, gallium and indium, the implantation energy is 3KeV to 15KeV, and the implantation dose is 1E13atom/cm 2 To 5E14atom/cm 2 。
10. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the threshold voltage adjustment region, the threshold voltage adjustment region has a predetermined thickness;
in the step of forming the isolation structure, the height of the fin portion exposed by the isolation structure is a preset height;
the preset thickness is 1/5 to 1/3 of the preset height.
11. The method of forming a semiconductor structure of claim 1, wherein a distance from a top surface of said isolation structure to a bottom surface of said inversion doped region is 0nm to 30nm after forming said isolation structure.
12. The method of claim 1, wherein in the step of providing a substrate, a fin mask layer is formed on top of the fin;
in the step of forming the isolation material layer, the isolation material layer exposes the top of the fin mask layer;
after forming the threshold voltage adjustment region, the method further comprises: and removing the fin part mask layer.
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| US8610201B1 (en) * | 2012-08-16 | 2013-12-17 | Kabushiki Kaisha Toshiba | FinFET comprising a punch-through stopper |
| US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
| CN106611710A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | A formation method of a semiconductor structure |
| CN107785424A (en) * | 2016-08-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN107785425A (en) * | 2016-08-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| US8610201B1 (en) * | 2012-08-16 | 2013-12-17 | Kabushiki Kaisha Toshiba | FinFET comprising a punch-through stopper |
| US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
| CN106611710A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | A formation method of a semiconductor structure |
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