CN112148649B - eMMC HS400 transmission mode realization method and device under u-boot system - Google Patents
eMMC HS400 transmission mode realization method and device under u-boot system Download PDFInfo
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Abstract
The application provides a method and a device for realizing an eMMC HS400 transmission mode under a u-boot system, wherein the total number of clock phases which can be tuned is determined from a host; an SDR _ tuning module and a DDR _ tuning module in an eMMC host drive control method are assigned according to each tunable clock Phase to form a CLK400_ Phase variable table; if the available clock phases exist in the CLK400_ Phase variable table, calling a Phase _ select module to screen out the optimal clock Phase from a plurality of clock phases in the CLK400_ Phase variable table; if there is no available clock phase, then clock phase adaptation is performed by the HS400_ tuning module; if a plurality of clock phases supporting data transmission of the eMMC in the HS400 transmission mode exist, calling the Phase _ select module again to screen the plurality of clock phases, and endowing the optimal clock Phase to a DIVRATIO variable to form a first DIVRATIO variable; and after the first DIVRATIO variable is assigned, calling an eMMC _ IO _ switch module to switch eMMC bus bit width and clock frequency, and selecting to enter an HS400 transmission mode according to the value of the first DIVRATIO variable.
Description
Technical Field
The present application relates to the field of memory device technologies, and in particular, to a method and an apparatus for implementing an eMMCHS400 transmission mode in a u-boot system.
Background
An embedded multimedia card (eMMC) is a storage technology, which is established by the MMC association. The architecture standard places MMC components (flash memory plus controller) in a small ball grid array package (BGA), an embedded non-volatile memory system used primarily for printed circuit boards. The eMMC has 100, 153, 169 contacts, and is mainly composed of a controller, a flash memory (nand flash), and a static random-access memory (SRAM).
The HS400 is an eMMC HS400 data transmission mode, and is a data transmission mode of an eMMC data bus working in a double-side sampling (DDR) mode, 1.8V/1.2V signal voltage is supported, the bus width supports an 8bit mode, and the maximum frequency supports 200 Mhz.
The DasU-Boot, called U-Boot for short (Universal BootLoader, Embedded System bootloader), can support various system structures, including PPC, ARM, AVR32, MIPS, x86, 68k, Nios, and MicroBlaze. And is also a free software release under the GNU universal public license. In embedded linux system, U-Boot
The general function is for system boot, that is, a kernel is read from a storage medium and loaded into an SDRAM (synchronous dynamic random-access memory) for operation.
Because the operating systems used by the end users all run on the kernel (a kernel, also called a core, a program for managing data input and output requirements sent by software), the emmhs 400 transmission mode is generally implemented only in the eMMC driver of the kernel, and the eMMC driver in the U-Boot only supports the high speed mode (eMMC high speed data transmission mode, maximum clock frequency 50Mhz, bus bit width 8bit, double speed bus). However, for the eMMC chip developer, many eMMC test tools and chip test scripts need to run the U-Boot as the emmhost, and perform a large amount of data read/write operations under the U-Boot, and only using the Highspeed transmission mode may reduce the efficiency of test development, and thus, improvement is needed.
Disclosure of Invention
The application provides a method and a device for realizing an eMMC HS400 transmission mode under a u-boot system, wherein the u-boot is used as an eMMC host of an eMMC test tool and a chip to operate, so that the eMMC test tool and the chip adopt the HS400 transmission mode to perform data transmission, and the transmission efficiency is improved.
The application adopts the following technical means for solving the technical problems:
the application provides an eMMC HS400 transmission mode realization method under a u-boot system, which comprises the following steps:
s1, determining the total number n of the tunable clock phases from the host, wherein n is more than or equal to 0;
s2, assigning values according to the tunable clock phases by adopting an SDR _ tuning module and a DDR _ tuning module in an eMMC host drive control method to form a CLK400_ Phase variable table, wherein the CLK400_ Phase variable table records the clock phases which are tuned and verified through the 200MHz double-rate bus clock phases;
s3, if there is no available clock Phase in the CLK400_ Phase variable table, performing clock Phase adaptation through the HS400_ tuning module in the emmhost drive control method to determine whether there is at least one set of clock phases in the CLK400_ Phase variable table to support eMMC data transmission in the HS400 transmission mode according to the CLK _ check variable;
s4, if a plurality of clock phases supporting the eMMC to perform data transmission in the HS400 transmission mode exist, calling the Phase _ select module again to perform a plurality of clock Phase screening, and endowing the optimal clock Phase to a DIVRATIO variable to form a first DIVRATIO variable;
and S5, after the first DIVRATIO variable is assigned, calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch eMMC bus bit width and clock frequency, and selecting to enter an HS400 transmission mode according to the value of the first DIVRATIO variable.
Further, after the step of assigning values by the SDR _ tuning module and the DDR _ tuning module in the emmghost drive control method according to the tunable clock phases to form the CLK400_ Phase variable table, the method further includes:
if at least one group of available clock phases exist in the CLK400_ Phase variable table, calling a Phase _ select module in the eMMC host drive control method to screen out an optimal clock Phase from a plurality of clock phases in the CLK400_ Phase variable table, and endowing the optimal clock Phase with a DIVRATIO variable to form a second DIVRATIO variable;
and after the second DIVRATIO variable is assigned, calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch eMMC bus bit width and clock frequency, and selecting to enter an HS400 transmission mode according to the value of the second DIVRATIO variable.
Further, before the step of determining the total number of tunable clock phases from the master, the method further includes:
calling an eMMC _ power _ cycle module by adopting an eMMC _ init module in the eMMC host drive control method to restart an eMMC power supply;
and calling an eMMC _ IO _ switch module in the eMMC host drive control method to set eMMC bus bit width and clock frequency as default values so as to enable the eMMC to enter a data transmission mode, wherein the default values are eMMC single-rate, 1bit of bus bit width and 400KHz of clock frequency.
Further, after the step of determining whether the CLK400_ Phase variable table has at least one group of clock phases supporting eMMC to perform data transmission in the HS400 transmission mode by using the CLK _ check variable, the method includes:
if the clock phase supporting the eMMC to perform data transmission in the HS400 transmission mode does not exist, giving the value of the default clock phase to a DIVRATIO variable to form a third DIVRATIO variable;
after the third divrvatio variable is completed, the eMMC still performs data transmission via the high transmitted mode.
Further, the step of performing clock Phase adaptation by the HS400_ tuning module in the emmhost drive control method to determine whether at least one set of clock phases exist in the CLK400_ Phase variable table by the CLK _ check variable to support eMMC for data transmission in the HS400 transmission mode includes:
calling the SDR _ tuning module to carry out single-rate bus clock phase tuning by adopting the HS400_ tuning module;
and recording, by the SDR _ tuning module, a clock phase tuned by a single rate;
continuously calling the DDR _ tuning module to carry out double-rate bus clock phase tuning on the clock phase passing through tuning;
the clock phase tuned by double rate is recorded by the DDR _ tuning module.
Further, the step of calling the SDR _ tuning module with the HS400_ tuning module to perform single-rate bus clock phase tuning comprises:
the SDR _ tuning module calls an eMMC _ IO _ switch module, and sets the eMMC into a single-rate bus mode, 8 bits of bit width and 200MHz of clock frequency;
then calling a Phase _ shift module to perform clock Phase shift;
after the offset, calling a Read _ tuning _ block module to enable the host to send an eMMC command standard CMD21, informing the eMMC to transmit 128 bytes of default tuning block data to the host, checking the tuning block data by the host, and if the data passes the check, recording the current clock Phase as passing by the SDR _ tuning module by using a CLK400_ Phase variable; if the check is not passed, calling a Phase _ shift module to perform clock Phase shift until all available clock phases are subjected to one tuning block check.
Further, the step of calling the DDR _ tuning module to perform double-rate bus clock phase tuning on the tuned clock phase includes:
the DDR _ tuning module calls an eMMC _ IO _ switch module, and sets the eMMC to be a double-rate bus, the bit width of the eMMC is 8 bits, and the clock frequency of the eMMC is 200 MHz;
the DDR _ tuning module determines the clock Phase to be custom tuned from the CLK400_ Phase variable, where the custom tuned clock Phase is the clock Phase that the SDR _ tuning module tunes through and is recorded in the CLK400_ Phase variable.
Calling a Phase _ shift module to perform clock Phase shift;
calling a Send _ RDtuning _ block module to enable the host to Send an eMMC standard command CMD25, and transmitting a self-defined tuning block of 1024 bytes to the host by the eMMC;
calling a Read _ RDtuning _ block module to enable a host to send an eMMC standard command CMD18, informing the eMMC to transmit a self-defined tuning block of 1024 bytes to the host, checking the tuning block data by the host, and if the tuning block data passes the check, recording the current clock Phase as passing by using a CLK400_ Phase variable by using a DDR _ tuning module; if the check is not passed, the Phase _ shift module is called to carry out clock Phase shift until all the usable clock phases are checked by the custom tuning block once.
Further, the method for screening the clock Phase by the Phase _ select module includes:
when multiple sets of clock phases exist, the Phase _ select module determines the optimal clock Phase using a preferred algorithm.
This application still provides an eMMC CHS400 transmission mode under u-boot system and realizes the device, the device includes:
the clock phase number determining unit is used for determining the total number n of the tunable clock phases from the host, wherein n is more than or equal to 0;
an assigning unit, configured to assign values according to the tunable clock phases by using an SDR _ tuning module and a DDR _ tuning module in an emmghost drive control method to form a CLK400_ Phase variable table, where the CLK400_ Phase variable table records clock phases tuned and verified by 200MHz double-rate bus clock phases;
an adapting unit, configured to, if the clock Phase does not exist in the CLK400_ Phase variable table, perform clock Phase adaptation through the HS400_ tuning module in the emmhost drive control method, to determine, through the CLK _ check variable, whether at least one group of clock phases exist in the CLK400_ Phase variable table to support eMMC for data transmission in the HS400 transmission mode;
the screening unit is used for calling the Phase _ select module again to screen a plurality of clock phases if the clock phases supporting the eMMC to transmit data in the HS400 transmission mode exist, and endowing the optimal clock Phase to a DIVRATIO variable to form a first DIVRATIO variable;
and the mode switching unit is used for calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch eMMC bus bit width and clock frequency after the first DIVRATIO variable is assigned, and selecting to enter an HS400 transmission mode according to the value of the first DIVRATIO variable.
The application provides an eMMC HS400 transmission mode realization method and device under a u-boot system, and the method and device have the following beneficial effects:
(1) the eMMC can normally operate in an HS400 data transmission mode under the uboot environment, and the transmission rate is improved.
(2) The Phase _ select optimization algorithm is added to select the most stable clock Phase from the plurality of already adapted clock phases, so as to improve the reliability and compatibility of the HS400 data transmission mode.
(3) By adapting the successful CLK400_ Phase variable and DIVRATIO variable, the system boot time can be shortened as a reference parameter for booting the current environment system, so as to improve the boot speed of the embedded linux system.
Drawings
Fig. 1 is a flowchart of a first embodiment of an eMMCHS400 transmission mode implementation method in a u-boot system of the present application;
fig. 2 is a flowchart of a second embodiment of a method for implementing an eMMCHS400 transmission mode in a u-boot system according to the present application;
fig. 3 is a flowchart of a third embodiment of a method for implementing an eMMCHS400 transmission mode in a u-boot system according to the present application;
fig. 4 is a flowchart of a fourth embodiment of a method for implementing an eMMCHS400 transmission mode in a u-boot system according to the present application.
The implementation, functional features and advantages of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that the terms "comprises," "comprising," and "having" and any variations thereof in the description and claims of this application and the drawings described above are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. In the claims, the description and the drawings of the specification of the present application, relational terms such as "first" and "second", and the like, may be used solely to distinguish one entity/action/object from another entity/action/object without necessarily requiring or implying any actual such relationship or order between such entities/actions/objects.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, a schematic flow chart of an implementation method of an eMMCHS400 transmission mode in a u-boot system in an embodiment of the present application is shown;
an implementation method of an eMMC HS400 transmission mode under a u-boot system comprises the following steps:
s1, determining the total number n of the tunable clock phases from the host, wherein n is more than or equal to 0;
s2, assigning values according to the tunable clock phases by adopting an SDR _ tuning module and a DDR _ tuning module in an eMMC host drive control method to form a CLK400_ Phase variable table, wherein the CLK400_ Phase variable table records the clock phases which are tuned and verified through the 200MHz double-rate bus clock phases;
s3, if there is no available clock Phase in the CLK400_ Phase variable table, performing clock Phase adaptation through the HS400_ tuning module in the emmhost drive control method to determine whether there is at least one set of clock phases in the CLK400_ Phase variable table to support eMMC data transmission in the HS400 transmission mode according to the CLK _ check variable;
s4, if a plurality of clock phases supporting the eMMC to perform data transmission in the HS400 transmission mode exist, calling a Phase _ select module in the eMMC host drive control method again to perform a plurality of clock Phase screens, and endowing the optimal clock Phase to a DIVRATIO variable to form a first DIVRATIO variable;
and S5, after the first DIVRATIO variable is assigned, calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch the eMMC bus bit width and the clock frequency, and selecting to enter the HS400 transmission mode according to the value of the first DIVRATIO variable.
In particular, the method comprises the following steps of,
the modules in the eMMC that perform the method are as follows:
HS400_ Host _ setting module, eMMC _ init module, Phase _ select module, HS400_ tuning module, eMMC _ IO _ switch module, eMMC _ power _ cycle module, SDR _ tuning module, DDR _ tuning module, Phase _ shift module, Read _ tuning _ block module, Send _ RDtuning _ block module, and Read _ RDtuning _ block module.
The following three variables exist:
CLK400_ Phase variable, CLK _ check variable, divrvatio variable.
In the process of implementing the method:
the method for determining the total number of tunable clock phases from the host by the eMMC includes: from a database (datasheet) or a document related to register descriptions of hosts, it is known that different hosts have different corresponding register addresses and the number of clock phases (e.g., 4 sets of offsets, 8 sets of offsets, 16 sets of offsets …, etc.) that they can tune.
In the step S2, the SDR _ tuning module and the DDR _ tuning module in the emmghost drive control method are assigned according to the tunable clock phases, and a process of forming the CLK400_ Phase variable table includes: the tuning of the single-rate bus clock of the SDR _ tuning module and the tuning of the double-rate bus clock of the DDR _ tuning module through the process that the respective clock phases after tuning are assigned on the CLK400_ Phase variable table will be described in detail below, and will not be described in detail herein.
Calling a Phase _ select module in an eMMC host drive control method to screen an optimal clock Phase in a CLK400_ Phase variable table, wherein the Phase _ select module is screened in the following mode: the Phase _ select module determines the optimal clock Phase by using a preferred algorithm, the preferred algorithm is to perform weight operation according to a plurality of groups of clock phases obtained by the tuning, and finally a group of clock phases which are most suitable for the host can be selected, but the group is not required to be used, but the reliability of the group of clock phases obtained by the algorithm is considered to be the highest, for example, 8 groups of clock phases are available for tuning by the host, 3 groups of clock phases are passed after the tuning is finished (the three groups can make the host run in the HS400mode), then the Phase _ select module is used for calculating to obtain the group of clock phases which are most stable theoretically, and then the host runs in the HS400 data transmission mode by using the group of clock phases.
In another embodiment, after the step S2 of forming the CLK400_ Phase variable table by assigning values to the SDR _ tuning module and the DDR _ tuning module in the emmghost drive control method according to respective tunable clock phases, the method further includes:
s21, if at least one group of available clock phases exists in the CLK400_ Phase variable table, calling a Phase _ select module in the eMMC host drive control method to screen out an optimal clock Phase from a plurality of clock phases in the CLK400_ Phase variable table, and endowing the optimal clock Phase to a DIVRATIO variable to form a second DIVRATIO variable;
and S22, after the second DIVRATIO variable is assigned, calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch the eMMC bus bit width and the clock frequency, and selecting to enter the HS400 transmission mode according to the value of the second DIVRATIO variable.
In another embodiment, after the step S3 of performing clock Phase adaptation by the HS400_ tuning module in the emmhost driving control method to determine whether at least one set of clock phases exist in the CLK400_ Phase variable table according to the CLK _ check variable, wherein the set of clock phases support eMMC data transmission in the HS400 transmission mode, the method includes:
s31, if there is no clock phase supporting eMMC to transmit data in HS400 transmission mode, the value of default clock phase is given to DIVRATIO variable to form a third DIVRATIO variable;
s32, after the third divrvatio variable is completed, the eMMC still performs data transmission via the high speed transmission mode.
In one embodiment, the step of determining the total number of clock phases available for tuning from the host further comprises:
calling an eMMC _ power _ cycle module by adopting an eMMC _ init module in an eMMC host drive control method to restart a power supply of the eMMC;
an eMMC _ IO _ switch module in the eMMC host drive control method is called to set eMMC bus bit width and clock frequency as default values so that the eMMC enters a data transmission mode, wherein the default values are eMMC single-rate, 1bit of bus bit width and 400KHz of clock frequency.
As can be seen from the above, the SDR _ tuning module and the DDR _ tuning module are used to assign values according to the respective tunable clock phases to form the CLK400_ Phase variable table, wherein the tuning process is as follows:
in one embodiment, the step of performing clock Phase adaptation by the HS400_ tuning module in the eMMC to determine whether at least one set of clock phases exists in the CLK400_ Phase variable table to support the eMMC to perform data transmission in the HS400 transmission mode includes:
calling the SDR _ tuning module to carry out single-rate bus clock phase tuning by adopting an HS400_ tuning module;
recording the clock phase tuned by the single rate by the SDR _ tuning module;
continuously calling the DDR _ tuning module to carry out double-rate bus clock phase tuning on the clock phase passing through tuning;
the clock phase tuned by the double rate is recorded by the DDR _ tuning module.
Further, the step of using the HS400_ tuning module to call the SDR _ tuning module for single-rate bus clock phase tuning comprises:
the SDR _ tuning module calls an eMMC _ IO _ switch module, and sets the eMMC into a single-rate bus mode, 8 bits of bit width and 200MHz of clock frequency;
then calling a Phase _ shift module to perform clock Phase shift;
after the offset, calling a Read _ tuning _ block module to enable the host to send an eMMC command standard CMD21, informing the eMMC to transmit 128 bytes of default tuner block data to the host, checking the tuner block data by the host, and if the data passes the check, recording the current clock Phase as passing by the SDR _ tuning module by using a CLK400_ Phase variable; if the check is not passed, calling a Phase _ shift module to perform clock Phase shift until all available clock phases are subjected to one tuning block check.
Further, the step of calling the DDR _ tuning module to perform double-rate bus clock phase tuning on the tuned clock phase includes:
the DDR _ tuning module calls an eMMC _ IO _ switch module, and sets the eMMC to be a double-rate bus, 8 bits of bit width and 200MHz of clock frequency;
the DDR _ tuning module determines the clock Phase to be custom tuned from the CLK400_ Phase variable, the custom tuned clock Phase being the clock Phase that the SDR _ tuning module tunes through and records in the CLK400_ Phase variable.
Calling a Phase _ shift module to perform clock Phase shift;
calling a Send _ RDtuning _ block module to enable the host to Send an eMMC standard command CMD25, and transmitting a self-defined tuning block of 1024 bytes to the host by the eMMC;
calling a Read _ RDtuning _ block module to enable a host to send an eMMC standard command CMD18, informing the eMMC to transmit a self-defined tuning block of 1024 bytes to the host, checking the tuning block data by the host, and if the tuning block data passes the check, recording the current clock Phase as passing by using a CLK400_ Phase variable by using a DDR _ tuning module; if the check is not passed, the Phase _ shift module is called to carry out clock Phase shift until all the usable clock phases are subjected to one time of custom tuning block check.
The specific checking method of the host is as follows: when the CMD21 is used by the host for SDR _ tuning, the 128-byte data transmitted by the eMMC to the host is specified by the protocol, i.e., the host knows what data the eMMC will transmit, if it is the data expected by the host, the check is passed, and if it is not, the check is not passed. At the time of DDR _ tuning, the host machine uses the standard read-write CMD to perform read-write operation on the eMMC, whether the data written in and read out are the same or not is verified, if yes, the verification is passed, and if not, the verification is not passed.
As described above, the clock Phase screening determination of the CLK400_ Phase variable table in step S2 is realized, and when the optimum clock Phase does not exist in the CLK400_ Phase variable table, the other clock phases that match the execution of the HS400 data transfer mode are screened.
It should be noted that: the shift of "calling Phase _ shift module to perform clock Phase shift" mentioned above can be understood as switching, and a general host only needs to a, close the host clock, b, fill the corresponding register address with the value to be shifted, and c, open the clock, and then complete the Phase shift (switching).
In one embodiment, a method for screening clock phases by a Phase _ select module includes:
when a plurality of groups of clock phases exist, the Phase _ select module determines the optimal clock Phase by adopting a preferred algorithm; or in another embodiment, the Phase _ select module uses a preferred algorithm to determine the process of "Phase _ select module performs several clock phases" screening in step S5.
The application also provides an eMMC CHS400 transmission mode implementation device under the u-boot system, and the device comprises:
the clock phase number determining unit is used for determining the total number n of the tunable clock phases from the host, wherein n is more than or equal to 0;
an assigning unit, configured to assign values according to the tunable clock phases by using an SDR _ tuning module and a DDR _ tuning module in an emmghost drive control method to form a CLK400_ Phase variable table, where the CLK400_ Phase variable table records clock phases tuned and verified by 200MHz double-rate bus clock phases;
an adapting unit, configured to, if the clock Phase does not exist in the CLK400_ Phase variable table, perform clock Phase adaptation through an HS400_ tuning module in the emmhost drive control method, so as to determine whether at least one group of clock phases exists in the CLK400_ Phase variable table by using the CLK _ check variable, so as to support eMMC to perform data transmission in the HS400 transmission mode;
the screening unit is used for calling the Phase _ select module again to screen a plurality of clock phases if the clock phases supporting the eMMC to transmit data in the HS400 transmission mode exist, and endowing the optimal clock Phase to a DIVRATIO variable to form a first DIVRATIO variable;
and the mode switching unit is used for calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch eMMC bus bit width and clock frequency after the first DIVRATIO variable is assigned, and selecting to enter an HS400 transmission mode according to the value of the first DIVRATIO variable.
Although embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the application, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. An implementation method of an eMMC HS400 transmission mode under a u-boot system is characterized by comprising the following steps:
s1, determining the total number n of the tunable clock phases from the host, wherein n is more than or equal to 0;
s2, assigning values by an SDR _ tuning module and a DDR _ tuning module in an eMMC host drive control method according to the tunable clock phases to form a CLK400_ Phase variable table, wherein the CLK400_ Phase variable table records the clock phases which are tuned and verified through the 200MHz double-rate bus clock Phase;
s3, if there is no available clock Phase in the CLK400_ Phase variable table, performing clock Phase adaptation through the HS400_ tuning module in the emmhost drive control method to determine whether there is at least one set of clock phases in the CLK400_ Phase variable table to support eMMC data transmission in the HS400 transmission mode according to the CLK _ check variable;
s4, if a plurality of clock phases supporting the eMMC to perform data transmission in the HS400 transmission mode exist, calling the Phase _ select module again to perform a plurality of clock Phase screening, and endowing the optimal clock Phase to a DIVRATIO variable to form a first DIVRATIO variable;
and S5, after the first DIVRATIO variable is assigned, calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch eMMC bus bit width and clock frequency, and selecting to enter an HS400 transmission mode according to the value of the first DIVRATIO variable.
2. The method for implementing the eMMCHS400 transmission mode under the u-boot system according to claim 1, wherein the step of assigning values to the SDR _ tuning module and the DDR _ tuning module in the eMMChost drive control method according to the tunable clock phases to form the CLK400_ Phase variable table further comprises:
if at least one group of available clock phases exist in the CLK400_ Phase variable table, calling a Phase _ select module in the eMMC host drive control method to screen out an optimal clock Phase from a plurality of clock phases in the CLK400_ Phase variable table, and endowing the optimal clock Phase with a DIVRATIO variable to form a second DIVRATIO variable;
and after the second DIVRATIO variable is assigned, calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch the eMMC bus bit width and the clock frequency, and selecting to enter an HS400 transmission mode according to the value of the second DIVRATIO variable.
3. The method for implementing eMMCHS400 transmission mode under the u-boot system according to claim 1, wherein the step of determining the total number of tunable clock phases from the host further comprises:
calling an eMMC _ power _ cycle module by adopting an eMMC _ init module in the eMMC host drive control method to restart an eMMC power supply;
calling an eMMC _ IO _ switch module in the eMMC host drive control method to set eMMC bus bit width and clock frequency as default values so as to enable the eMMC to enter a data transmission mode, wherein the default values are eMMC single-time rate, bus bit width of 1bit and clock frequency of 400 KHz.
4. The method for implementing the eMMCHS400 transmission mode under the u-boot system according to claim 1, wherein after the step of determining whether at least one group of clock phases exist in the CLK400_ Phase variable table by using the CLK _ check variable to support the emmcs to perform data transmission in the HS400 transmission mode, the method comprises:
if the clock phase supporting the eMMC to perform data transmission in the HS400 transmission mode does not exist, giving the value of the default clock phase to a DIVRATIO variable to form a third DIVRATIO variable;
after the third divrvatio variable is completed, the eMMC still performs data transmission via the high transmitted mode.
5. The method for implementing the eMMCHS400 transmission mode under the u-boot system of claim 1, wherein the step of performing clock Phase adaptation through an HS400_ tuning module in the eMMChost drive control method to determine whether at least one set of clock phases exist in the CLK400_ Phase variable table according to the CLK _ check variable to support the emmcs for data transmission in the HS400 transmission mode comprises:
calling the SDR _ tuning module to carry out single-rate bus clock phase tuning by adopting the HS400_ tuning module;
and recording, by the SDR _ tuning module, a clock phase tuned by a single rate;
continuously calling the DDR _ tuning module to carry out double-rate bus clock phase tuning on the clock phase passing through tuning;
the clock phase tuned by double rate is recorded by the DDR _ tuning module.
6. The method of claim 5, wherein the step of invoking the HS400_ tuning module to call the SDR _ tuning module to perform single rate bus clock phase tuning comprises:
the SDR _ tuning module calls an eMMC _ IO _ switch module, and sets the eMMC into a single-rate bus mode, 8 bits of bit width and 200MHz of clock frequency;
then calling a Phase _ shift module to perform clock Phase shift;
after the offset, calling a Read _ tuning _ block module to enable the host to send an eMMC command standard CMD21, informing the eMMC to transmit 128 bytes of default tuning block data to the host, checking the tuning block data by the host, and if the data passes the check, recording the current clock Phase as passing by the SDR _ tuning module by using a CLK400_ Phase variable; if the check is not passed, calling a Phase _ shift module to perform clock Phase shift until all available clock phases are subjected to one tuning block check.
7. The method for implementing the EMMCHS400 transmission mode under the u-boot system according to claim 6, wherein the step of invoking the DDR _ tuning module to double-rate bus clock phase tuning the tuned clock phase comprises:
the DDR _ tuning module calls an eMMC _ IO _ switch module, and sets the eMMC to be a double-rate bus, the bit width of the eMMC is 8 bits, and the clock frequency of the eMMC is 200 MHz;
the DDR _ tuning module determines a clock Phase needing to be subjected to custom tuning from a CLK400_ Phase variable, wherein the clock Phase needing to be subjected to custom tuning is the clock Phase which is recorded in the CLK400_ Phase variable after the SDR _ tuning module is tuned;
calling a Phase _ shift module to perform clock Phase shift;
calling a Send _ RDtuning _ block module to enable the host to Send an eMMC standard command CMD25, and transmitting a self-defined tuning block of 1024 bytes to the host by the eMMC;
calling a Read _ RDtuning _ block module to enable a host to send an eMMC standard command CMD18, informing the eMMC to transmit a self-defined tuning block of 1024 bytes to the host, checking the tuning block data by the host, and if the tuning block data passes the checking, recording the current clock Phase as passing by using a CLK400_ Phase variable by using the DDR _ tuning module; if the check is not passed, the Phase _ shift module is called to carry out clock Phase shift until all the usable clock phases are subjected to one time of custom tuning block check.
8. The method for implementing the eMMCHS400 transmission mode under the u-boot system of claim 1, wherein the Phase _ select module is used for screening the clock Phase, and the method comprises the following steps:
when multiple sets of clock phases exist, the Phase _ select module determines the optimal clock Phase using a preferred algorithm.
9. An apparatus for implementing an eMMCHS400 transmission mode under a u-boot system, the apparatus comprising:
the clock phase number determining unit is used for determining the total number n of the tunable clock phases from the host, wherein n is more than or equal to 0;
an assigning unit, configured to assign values according to the tunable clock phases by using an SDR _ tuning module and a DDR _ tuning module in an emmghost drive control method to form a CLK400_ Phase variable table, where the CLK400_ Phase variable table records clock phases tuned and verified by 200MHz double-rate bus clock phases;
an adapting unit, configured to, if the clock Phase does not exist in the CLK400_ Phase variable table, perform clock Phase adaptation through an HS400_ tuning module in the emmhost drive control method, so as to determine whether at least one group of clock phases exists in the CLK400_ Phase variable table by using the CLK _ check variable, so as to support eMMC to perform data transmission in the HS400 transmission mode;
the screening unit is used for calling the Phase _ select module again to screen a plurality of clock phases if the clock phases supporting the eMMC to transmit data in the HS400 transmission mode exist, and endowing the optimal clock Phase to a DIVRATIO variable to form a first DIVRATIO variable;
and the mode switching unit is used for calling an eMMC _ IO _ switch module in the eMMC host drive control method to switch eMMC bus bit width and clock frequency after the first DIVRATIO variable is assigned, and selecting to enter an HS400 transmission mode according to the value of the first DIVRATIO variable.
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