CN112134557A - Wide voltage self-adaptive adjusting system and method based on pulse latch time sequence monitoring - Google Patents
Wide voltage self-adaptive adjusting system and method based on pulse latch time sequence monitoring Download PDFInfo
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Abstract
The invention discloses a wide voltage self-adaptive adjusting system and method based on pulse latch time sequence monitoring, and discloses a pulse latch clustering method applied to a self-adaptive voltage adjusting system. By comprehensively considering the load requirement of the pulse generator and the distance between the pulse generator and the time sequence monitoring module, the time sequence monitoring unit modules are reasonably clustered and inserted into the pulse generator by applying a linear programming method, so that one pulse generator can simultaneously provide clock pulse signals for a plurality of time sequence monitoring units, the number of the pulse generators is reduced, the short-path repair cost of an online monitoring system is effectively reduced, and the area and power consumption cost of a circuit are greatly reduced under the condition of meeting the design requirement.
Description
Technical Field
The invention relates to the technical field of low power consumption of digital integrated circuits, in particular to a self-adaptive voltage frequency adjusting technology based on online time sequence monitoring.
Background
With the continuous increase of the scale and the computing power of the integrated circuit and the increasingly higher requirements of application scenarios such as the internet of things, embedded devices, mobile terminals, supercomputers, and data centers on the energy consumption of devices, the development of the high-energy-efficiency integrated circuit is an important means for solving the problem of energy consumption of a computing system, and the reduction of the working voltage of the chip can greatly reduce the power consumption of the chip, so that how to further reduce the working voltage of the chip to realize the energy efficiency crossover-type promotion becomes one of the problems which need to be solved urgently. Near-threshold integrated circuit designs are considered one of the most promising techniques for improving computational performance in the future by reducing the supply voltage of the chip or circuit to a level close to the threshold voltage of the transistor.
The near-threshold technique also presents a challenge to designers while bringing a large increase in chip energy efficiency. In the application of the near-threshold technology, the performance of the integrated circuit is affected by Process (Process), Voltage (Voltage), and Temperature (Temperature) deviations, i.e., PVT deviations, so that the delay distribution of the circuit is large, and further, the deviation of the path delay is multiplied. To ensure that a chip can operate stably under various conditions, conventional designers often need to reserve a large amount of timing margin to meet worst-case timing constraints. Meanwhile, in order to prevent the influence of circuit aging, random noise, 1/f noise, and the like, the designer also needs to leave some margin in the design process. This results in significant waste of performance and power consumption, greatly impairing the energy efficiency improvement brought by near-threshold design.
In order to reduce the excessive design margin of the circuit, better release the potential of wide Voltage design, overcome the problem of severe PVT deviation under low Voltage, and produce Adaptive Voltage Frequency Scaling (AVFS) technology. In the actual operation condition of the chip, the probability of extreme environments is extremely low, and the self-adaptive voltage frequency adjusting scheme can self-adaptively adjust the working voltage and frequency of the chip according to different working environments, so that the correctness of the functions of the chip can be ensured, the reserved design margin of the chip can be reduced as much as possible, and the purpose of saving power consumption is achieved.
The current adaptive voltage frequency regulation technology is based on a direct monitoring method, wherein the most typical representative method is a Razor series researched by michigan university, however, the method usually replaces a critical path end trigger with a latch, and is easy to generate the problem of short path. That is, a path that is too short (a path with a delay less than a half cycle) may arrive at the latch during the high level of the clock and be transmitted to the next stage circuit, which may cause the latch type monitoring unit that replaces the end register to generate an erroneous alarm message, and thus, the short path must be completely restored after the falling edge of the clock.
Short path repair is the same problem as hold time repair, but since the short path needs to be repaired for a longer time, a large number of buffers need to be added to the circuit, which greatly increases the area cost. When a Pulse latch (Pulse latch) is used for monitoring, the high-level duration time is a short Pulse, so that the cost of short-path repair is greatly reduced, but a plurality of local Pulse generators need to be additionally provided in the method, and an optimization means needs to be provided to reduce the area and power consumption overhead brought by the method.
The linear programming is one of important branches of operation research, and solves the problem of solving the optimal solution under certain constraint conditions. In general, the problem of finding the maximum or minimum of a linear objective function under linear constraints is collectively called linear programming. The solution of the linear constraint is called a feasible solution, and the set of all feasible solutions is called a feasible domain.
Disclosure of Invention
Object of the Invention
Aiming at the problem that the traditional adaptive voltage frequency regulation technology replaces a key path end trigger by a latch with a time sequence monitoring function so as to cause serious short path repair cost, the invention provides a scheme of combining a Pulse latch (Pulse latch) technology and an adaptive voltage technology, provides an adaptive voltage frequency regulation system based on the Pulse latch, optimizes a Pulse Generator (PG) and a time sequence monitoring module connection scheme, and provides a method for dividing a time sequence monitoring unit into a proper cluster in the adaptive voltage frequency regulation system and reducing the quantity of inserted PGs, thereby reducing the area and power consumption cost of a circuit.
Technical scheme
The design idea of the adaptive voltage system of the basic pulse latch of the invention is as follows: and replacing a trigger at the tail end of the critical path with a time sequence monitoring unit module based on a latch structure, generating a pulse clock by using a pulse generator to serve as a clock signal of the time sequence monitoring unit module, judging the time sequence condition in the chip according to a monitoring result, and adjusting the working voltage or frequency of the chip in real time. In the invention, the duration of the high level of the pulse width is very short, so that the cost of short-path repair is greatly reduced. Here, the timing monitoring unit requires a pulse generator to provide it with clock pulses. The connection between the PG and the time sequence monitoring unit module is solved, the most traditional method adopts a one-to-one correspondence relationship, but the method has higher cost on area and power consumption. Therefore, the invention further clusters the time sequence monitoring units and inserts the pulse generators, which can effectively reduce the number of the inserted pulse generators and further reduce the area and power consumption overhead of the circuit.
In order to achieve the purpose, the invention specifically adopts the following technical scheme:
a wide voltage self-adaptive adjusting system based on pulse latch time sequence monitoring is characterized by comprising a plurality of time sequence monitoring unit modules and a plurality of pulse generators, wherein the time sequence monitoring unit modules are formed by connecting a monitoring circuit with a time sequence monitoring function with latches in parallel; the method comprises the steps of comprehensively considering the load requirement of a pulse generator and the distance between the pulse generator and a time sequence monitoring unit module, clustering the plurality of time sequence monitoring unit modules, solving the position coordinates of the pulse generator when the minimum value of a target function is met by using a linear programming method and the capacitance limit met by the coordinates of the pulse generator and the time sequence monitoring unit module as a constraint condition, and inserting one pulse generator into each cluster and providing clock pulse signals for the time sequence monitoring unit modules in the same cluster;
the capacitance limit satisfied by the coordinates of the pulse generator and timing monitoring unit modules is shown in equation (2):
the objective function is shown in equation (3):
where (x, y) are the coordinates of the pulse generator, (a)i，bi) Is related to pulse generationCoordinates of the ith time sequence monitoring unit module connected with the pulse generator, M represents the number of the time sequence monitoring unit modules connected with the pulse generator, CGeneral assemblyRepresenting the maximum load that the pulse generator can drive, CLatchRepresenting the gate capacitance of the MOS transistor in the latch, CTDRepresenting the gate capacitance, C, of the MOS transistor in the monitoring unitwrie1Representing the lateral track capacitance, Cwrie2Representing the vertical trace capacitance.
The pulse generator needs to work stably under wide voltage, and the generated pulse clock is used as a clock signal of the monitoring circuit and the latch, so that the normal operation of the time sequence monitoring unit module is ensured. The pulse clock width is in accordance with certain design constraints, so that the correctness of the chip function under different PVT conditions is ensured.
Generally, the connection between the PG and the timing monitoring unit modules is solved in the simplest way by adopting a one-to-one correspondence relationship. However, in practical situations, one pulse generator can provide clock signals for a plurality of timing monitoring circuits under the condition that the load requirement is met, so that this method causes a great deal of resource waste, and especially for large-scale integrated circuits, this method is expensive in terms of area and power consumption. Therefore, the invention solves the optimization scheme of the connection between the pulse generator and the time sequence monitoring module by using a linear programming method, and reduces the area and power consumption cost of the self-adaptive voltage system of the basic pulse latch. Linear programming is one of the important branches of operations research, and the problem of finding the maximum or minimum of a linear objective function under linear constraint conditions is collectively called linear programming. By the method, reasonable clusters are divided for the time sequence monitoring unit module, and then the pulse generators are inserted into reasonable positions, so that the number of the pulse generators can be effectively reduced, and the area cost is reduced.
Dividing the timing monitoring unit modules into clusters and inserting pulse generators in the appropriate locations follows three principles:
1) the utilization rate of the PG is maximized, the PG can drive as many sequential monitoring unit modules as possible, and therefore the design requirement can be met by the minimum quantity of the PG, and the area and power consumption cost are reduced.
2) The output load of the PG cannot exceed its maximum allowable load, thereby ensuring the correctness of the function. Once the maximum load of PG is exceeded, the clock pulse signal quality can become very poor, affecting the correctness of the function.
3) The distance between the PG and the timing monitor cell block is taken into full consideration by the principle of proximity, since as the distance increases, the line load and delay also increase accordingly.
In order to meet the three design principles, the invention introduces the wiring capacitor as a constraint condition, abstracts the load relationship between the pulse generator and the time sequence monitoring unit module connected with the pulse generator into a mathematical model as the constraint condition, takes the total capacitor as a target function, finally solves the position coordinate of the pulse generator when the target function takes the minimum value, and inserts the pulse generator according to the position coordinate and simultaneously provides a clock pulse signal for the time sequence monitoring unit modules in the same cluster.
The method for dividing the pulse latch into the clusters provided by the invention comprises several steps, wherein the description of the related parameters is shown in table 1, wherein the first column in the table indicates the names of the parameters, and the second column indicates the specific explanations of the parameters.
TABLE 1
1) Under the condition of not considering the wiring capacitance, determining the maximum load capacity of each pulse generator and the number of the maximum time sequence monitoring unit modules which can be connected with each pulse generator according to a formula (1); if the calculated N is an integer, the number of the actually selected time sequence monitoring unit modules is N-1, and if the calculated N is a decimal, the number of the actually selected time sequence monitoring unit modules is an integer part of the N.
2) Randomly selecting one from all deployed time sequence monitoring unit modules, selecting other time sequence monitoring unit modules adjacent to the selected time sequence monitoring unit module according to the number of the maximum time sequence monitoring unit modules which can be connected with each pulse generator and are determined in the step 1), and classifying the selected time sequence monitoring unit modules into the same cluster;
3) preliminarily determining the position of the pulse generator according to the positions of the time sequence monitoring unit modules contained in the clusters divided in the step 2);
4) the wiring capacitor is introduced as a constraint condition, and the pulse generator and the time sequence monitoring unit module connected with the pulse generator meet the load relation limitation as shown in a formula (2):
wherein, (x, y) is the coordinate of the pulse generator, (ai, bi) is the coordinate of the ith time sequence monitoring unit module connected with the pulse generator, M represents the number of the time sequence monitoring unit modules connected with the pulse generator, CGeneral assemblyRepresenting the maximum load that the pulse generator can drive, CLatchRepresenting the gate capacitance of the MOS transistor in the latch, CTDRepresenting the gate capacitance, C, of the MOS transistor in the monitoring unitwrie1Representing the lateral track capacitance, Cwrie2Representing the longitudinal wiring capacitance;
5) calculating the position coordinate of the pulse generator when the target function which meets the following formula (3) takes the minimum value by using a linear programming method and taking the load relation limit of the pulse generator and the time sequence monitoring unit module connected with the pulse generator in the step 4) as a constraint condition;
6) if the step 5) is successful, calculating the coordinates of the pulse generator, namely, using the coordinates as the insertion position of the pulse generator; if the load capacity of the pulse generator is not enough to drive all the time sequence monitoring unit modules connected with the pulse generator after the wiring capacitor is introduced, removing one time sequence monitoring unit module on the basis of the original cluster, and repeating the operations of the step 3), the step 4) and the step 5) until the time sequence monitoring unit module is classified into a proper cluster and the coordinate of the pulse generator is calculated.
Has the advantages that: the invention provides a wide voltage self-adaptive adjusting system applied to a direct time sequence monitoring scheme, which adopts a pulse latch to reduce the duration time of a high level of a clock, thereby effectively reducing the short path repairing cost of the direct online monitoring self-adaptive adjusting system. The invention utilizes a linear programming method, takes the capacitance limit met by the coordinates of the pulse generator and the time sequence monitoring unit module as a constraint condition, calculates the optimized value meeting the objective function, reasonably clusters the time sequence monitoring unit module, inserts the pulse generator in a proper position, and optimizes and solves the connection scheme of the pulse generator and the time sequence monitoring module. Compared with a simple one-to-one connection scheme of the time sequence monitoring unit module and the pulse generator, the pulse generator circuit has the advantages that the number of the pulse generators can be reduced to a great extent, and therefore the area and the power consumption cost of the circuit are effectively reduced.
Drawings
FIG. 1 is a block diagram of a system for adaptive voltage frequency regulation based on a pulse latch
FIG. 2 is a timing diagram of an adaptive voltage regulation system based on a pulse latch
FIG. 3 is a timing constraint for pulse width
FIG. 4 illustrates a Pulse generator insertion process
FIG. 5 is a flow chart of adaptive voltage frequency adjustment based on a pulse latch
FIG. 6 is a circuit diagram of a pulse generator
Fig. 7 is a case implementation diagram: distribution of pulse generator and time sequence monitoring unit module
FIG. 8 is a frequency gain for adaptive voltage frequency scaling using a pulse latch clustering method
Detailed Description
The invention is further illustrated with reference to the following figures and specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention.
The block diagram of the adaptive voltage frequency regulation system based on the pulse latch is shown in fig. 1 and mainly comprises four parts: a time sequence monitoring unit module, a pulse generator, a Dynamic Or (Dynamic Or-tree) circuit and a control module. The monitoring circuit and the latch form a time sequence monitoring unit module which is used for replacing a trigger at the tail end of the critical path. The latch completes the data storage function, and the monitoring circuit is used for monitoring whether the time sequence in the chip is violated, and can be a jump detector or a Razor type time sequence monitoring circuit; the monitoring circuit and the latch are connected in parallel, the input of the monitoring circuit and the latch are both the input of the original critical path tail end trigger, the output of the monitoring circuit is an early warning signal error, and the output of the latch is the output signal of the original critical path tail end trigger. The pulse generator consists of 3 NAND gates, one phase inverter and a configurable delay module, wherein the configurable delay module is used for configuring the delay size, thereby realizing the adjustment of the pulse width. The pulse generator generates a stable pulse clock, and provides the stable pulse clock to the timing monitoring unit module as a clock signal. The dynamic OR circuit is used for collecting the time sequence early warning signals error of each critical path sent by the time sequence monitoring unit module and transmitting the total time sequence early warning signals dyna _ error to the control module. Compared with a traditional OR gate, the transmission speed is higher. The control module comprises a voltage regulation control unit (AVS) and a rapid frequency regulation unit (AFS), and the control module adjusts the working voltage of the chip in a self-adaptive manner through the voltage regulation control unit and adjusts the working frequency of the chip in a self-adaptive manner through the rapid frequency regulation unit according to the total time sequence early warning signal.
Fig. 2 is a timing diagram for adaptive voltage frequency adjustment based on a pulse latch. In the first clock period, the data input end D is kept unchanged, no error early warning signal is generated at the moment, and the circuit works normally; in the second clock period, when the clock CLK is at a high level, the data D is turned over, which indicates that the time sequence of the critical path becomes tense, the error early warning signal error is pulled high and is transmitted to the control module through the dynamic or logic circuit, and the control module acquires a total error early warning signal; at the third clock cycle, the clock CLK is gated for one clock cycle, and because the flip-flop at the end of the monitoring path is replaced by the timing monitoring unit module, the characteristic of borrowing latch time can be utilized, so that the circuit does not generate real timing errors, but the circuit timing is tense. The clock CLK is pulled down all the time in the third clock period, at the moment, the data of the digital circuit register and the latch are kept unchanged, the circuit has no time sequence error, and then the clock gating module sends a reset signal reset to the dynamic state or the logic state to realize the reset of the total error early warning signal so as to enable the system to recover to be normal; in the fourth clock cycle, the clock CLK returns to normal and the circuit continues to operate normally.
An adaptive voltage frequency regulation system based on a pulse latch requires a pulse generation circuit to provide a clock pulse signal thereto, generated by a pulse generator. Since the clock is sensitive to the output load, the load of the pulse generator must be controlled to prevent potential pulse degradation phenomena from occurring. If one pulse generator is connected to a single timing monitoring unit module, the load of the pulse generator is small, but in such a manner, a plurality of pulse generators need to be inserted, resulting in additional consumption of high power. On the other hand, if fewer pulse generators are used to drive all of the timing monitor cell blocks, power consumption is less costly but the clock waveform is distorted due to excessive loading. Therefore, in order to reduce area overhead while ensuring functional accuracy, it is necessary to cluster the timing monitoring unit modules during the design process to minimize the number of pulse generators.
After a time sequence monitoring unit module consisting of a monitoring circuit and a latch is inserted at the end of the critical path, the position of the pulse generator needs to be optimized. When inserting the pulse generator, the following three issues need to be considered:
(1) maximizing the utilization rate of the pulse generator to drive as many sequential monitoring unit modules as possible;
(2) the output load of the pulse generator should be kept below the maximum allowable load;
(3) the proximity principle is used to take into account the distance between the pulse generator and the timing monitoring unit module group, since with increasing distance, the line load and the delay increase accordingly.
The description of the parameters of the pulse latch clustering algorithm is shown in table 1, wherein the first column in the table indicates the names of the parameters and the second column indicates the specific explanations of the parameters.
TABLE 1
In the design method provided by the invention, the maximum allowable load capacitance of the pulse generator is obtained firstly, and then the maximum number of the time sequence monitoring unit modules driven by the pulse generator is determined. Then, distances are first set for the timing monitoring unit modules classified into the same cluster. The distance between the timing monitoring unit module and the pulse generator represents the wire capacitance. To reduce the wire capacitance, the nearest timing monitor cell module is changed into a new cluster. As shown in fig. 4, in this clustering process, if all constraints are satisfied, the minimum distance and the closest two clusters are selected. In this process, the allowable load capacitance and maximum fanout constraints of the pulse generator must be checked. In each iteration, a pulse generator is inserted in the center of a cluster to determine that the above constraints are satisfied. After this process, a pulse generator is inserted into the circuit and the netlist is then updated. At this time, the insertion position and wiring manner of the PG are already determined, and the timing of the entire design is checked. Finally, one local pulse generator is shared by several sequential monitor cell modules in its vicinity.
The specific algorithm steps are as follows:
1) under the condition that wiring capacitance is not considered, the number of the maximum time sequence monitoring unit modules which can be connected with each PG is set to be N, the calculation of N is shown by the following formula, if the calculated N is an integer, the number of the actually selected time sequence monitoring unit modules is N-1, and if the calculated N is a decimal number, the number of the actually selected time sequence monitoring unit modules is an integer part of N:
the pulse generator as in the embodiment can provide a pulse clock to 6 timing monitoring units at maximum.
2) The number of the time sequence monitoring unit modules finally selected in the step 1) is M, the first monitoring module is randomly selected to be A1, M-1 time sequence monitoring unit modules closest to the horizontal and vertical coordinates of A1 are selected, and the M-1 time sequence monitoring unit modules are respectively A2-AM.
3) Assuming that the PG coordinates are (x, y), the coordinates of the M sequential monitor cell modules are a1(a1, b1), a2(a2, b2), A3(A3, b3), a.
4) The capacitance limits satisfied by the PG coordinates and the coordinates of the timing monitoring unit modules are as follows:
5) using a linear programming method, taking the above equation (2) as a constraint condition, obtaining the PG coordinate satisfying the objective function of the following equation (3) to obtain the minimum value:
6) if the coordinates of the PG can be found, the selected M time sequence monitoring modules and the coordinates of the PG meet the design requirements, if the formula (2) does not hold, the nearest M-1 time sequence monitoring unit modules are selected, and the calculation is carried out again from the step 3) until the proper time sequence monitoring unit modules and the coordinates of the PG are found.
Through the steps, the inserting position of the pulse generating module PG can be finally determined, and in the places where the time sequence monitoring units are densely distributed, each pulse generator can drive more time sequence monitoring unit modules due to the fact that the connecting line capacitance is small. In contrast, in the case of sparse pulse latch distribution, the number of timing monitoring unit modules that can be driven by each pulse generator will be smaller due to the larger wiring capacitance. Therefore, the distribution of the pulse generators is directly dependent on the location distribution of the timing monitoring unit modules.
Fig. 3 is a timing constraint for pulse width. The pulse width is selected to be reduced as much as possible on the premise of considering functional stability, so that the area cost caused by the insertion of a large number of buffers is saved. The pulse width must be set to ensure that the early warning signal ("error") and the correct data signal ("D") are transmitted correctly, and therefore the pulse width must satisfy the following two conditions: 1) allowing data "D" to pass through the latch correctly and be collected by the next stage; 2) the early warning signal 'error' can be collected dynamically or by a circuit.
When the PVT working condition is determined, the establishing time of the latch and the detection time of the monitoring circuit are fixed values, and at the moment, the pulse width mainly considers the size of a monitoring window. The larger the monitoring window is, the longer the latch can borrow time is, but the number of buffers needing to repair the short path is large; the smaller the monitoring window, the fewer the number of buffers needed to repair the short path, but the less time the latch can borrow. In the timing constraint of the pulse width of fig. 3, TW represents the pulse width, first represents the delay on the clock tree, second represents the error detection window, third represents the time required for passing correct data (including data "D" and error warning signal "error"), TD-DETECT represents the monitoring time of the error warning signal, TLatch _ setup represents the setup time of the latch, and the time of Tpass must be greater than the setup time of the latch (TLatch _ setup) and the detection time of the monitoring circuit (TD-DETECT). The pulse width must satisfy the requirement of the following formula:
TW≥TDW+max(TLatch_setup,TD-DETECT) (4)
FIG. 5 is a flow chart of the adaptive voltage frequency adjustment based on the pulse latch according to the present invention. Firstly, performing time sequence analysis on the netlist after layout and wiring to screen out an effective critical path. And then replacing the trigger at the tail end of the screened critical path with a time sequence monitoring unit module, then extracting the position information of the time sequence monitoring unit module, selecting a proper position to insert the PG unit by utilizing a pulse latch clustering algorithm, finally carrying out time sequence analysis on the netlist again, and searching a proper position again to insert the PG unit if the design requirement is not met until the design requirement is completely met.
The circuit diagram and timing diagram of the pulse generator are shown in fig. 6. The pulse generator consists of 3 NAND gates, one phase inverter and a configurable delay module, wherein the configurable delay module can complete the configuration of different delay sizes, thereby realizing the adjustment of pulse width. The basic principle of the pulse generator is as follows: when the clock signal CLK is low, both the nodes X and Qb are high, and the node Y remains low; when the CLK is changed from low to high level, firstly the node Qb is changed from high to low, so that the node Y is changed from low to high, and the node X is changed from high to low, at the moment, the node Qb is changed from low to high, and the time for completing the whole process is the pulse width generated by the pulse generator, so that the pulse width is determined by the configurable delay chain and the delays of the three NAND gates.
Example (b):
in a specific implementation case of the method for dividing the pulse latch into the clusters, the method is applied to an 8-bit AES (Advanced Encryption Standard) circuit of a wide voltage AVS technology. The adopted process is SMIC 28nm, under the process, the line capacitance corresponding to each layer of metal in unit length is simulated, and the specific parameters are shown in Table 2.
TABLE 2 line capacitance per unit length for each layer of metal (1 μm long, 0.05 μm wide)
The design of the pulse generator selected in this embodiment is shown in fig. 6. Under different PVT conditions, the pulse width has large variation. In order to ensure that the pulse width can meet the design requirements under various PVT environments, the pulse width can be realized by configuring a configurable delay module. When different configuration values are selected, the number of buffers through which the data Qb passes is different, and therefore, the delay time generated is also different. In a specific design, under 0.8V-1.1V, Select [1:0] is configured to be 01, and then passes through a first-level Buffer, under 0.6V-0.8V, Select [1:0] is configured to be 11, and passes through a third-level Buffer.
The gate capacitance of the timing monitor cell block is extracted to obtain gate capacitances 8.5679e-16F (CLatch + CTD). The maximum output load capacitance is 15 times of the minimum input capacitance generally, the minimum input capacitance of the SMIC 28nm technology is the inverter input capacitance driven at the minimum, the specific value is 3.5e-16F, and therefore, the maximum load capacitance value which can be driven by one PG is 5.2e-15F (C)General assembly) And the pulse clock can be provided for 6 timing monitoring unit modules at most. The whole design is based on the netlist after layout and routing, and firstly, the coordinates of the timing monitoring unit module are obtained by using a get _ location command of an IC Compiler tool. And then, using MATLAB language to realize the pulse latch clustering division algorithm. In the present design example, after the algorithm division, the 188 timing monitoring unit modules need 38 PGs, and the distribution of the PGs and the timing monitoring modules is shown in fig. 7. As can be seen, the timing monitor cell blocks are relatively evenly distributed around the PG. In the place where the time sequence monitoring units are densely distributed, each pulse generator can drive more time sequence monitoring unit modules due to the small wiring capacitance. In contrast, in the case of sparse pulse latch distribution, the number of timing monitoring unit modules that can be driven by each pulse generator will be smaller due to the larger wiring capacitance. Therefore, the distribution of the pulse generators is directly dependent on the location distribution of the timing monitoring unit modules. It should be noted that, in order to reduce the deviation of the pulse width generated by PG, PG is encapsulated into a macro-cell during specific design.
In this embodiment, it can be seen that 38 pulse generators need to be inserted into 188 timing monitoring unit modules, and compared with a design scheme in which one timing monitoring unit module corresponds to one PG in a simple method, 150 PGs are reduced, and the circuit area overhead is greatly reduced.
In the embodiment, the method disclosed by the invention is applied to design a chip of an adaptive voltage regulation system, under the condition of 1.1V, the working frequency of the chip is 1.25GHz, the total number of registers in the design is 1856 (3-bit AES cores in total), the number of inserted monitoring units is 188, the insertion rate is 10.1%, the area of all monitoring and regulation modules is increased by 4.3%, the loss and gain reach 64.3%, and the area cost of the AVS module and the control module is only 4.3%.
In the embodiment, the total number of chips tested is 24, and 8 chips are selected from three wafers of FF, TT and SS from test wafers of a process factory for testing. The designed working voltage range of the batch of chips is 0.46V-1.1V. The reference frequency refers to the highest operating frequency considering the reserved timing margin of the chip, i.e. the highest frequency that can operate in the worst case. The worst case is: the worst temperature in the temperature range of 0-85 ℃ is selected as the temperature (usually the highest temperature, and the lowest temperature is taken due to the temperature flipping effect under the near threshold) when the reference chip is tested, the worst process corner chip is represented by the chip with the worst performance, and 90% of the standard voltage is used as the worst voltage. It should be noted that due to the temperature inversion effect, the worst operating temperature of the chip is 85 ℃ at 0.8V-1.1V, and 0 ℃ at 0.5V-0.7V. The actual test is performed on the batch of chips, the reference frequency under the worst condition is found, the reference frequency under different voltages is tested, meanwhile, a chip with a process corner of Typical is selected, the highest frequency under 0.55V-1.1V is tested, and the tested highest working frequency and the reference frequency distribution diagram are shown in FIG. 8. Therefore, the highest working frequency of the chip is obviously improved compared with the reference frequency in a wide voltage range. Especially under the voltage of a near threshold value of 0.55V, the highest working frequency of the chip applying the technology can be improved to be 3 times of the reference frequency. The self-adaptive voltage frequency adjustment based on the pulse latch can effectively detect the time sequence situation in the chip, and self-adaptively adjust the working voltage of the chip according to the monitored time sequence situation, thereby effectively reducing the reserved time sequence allowance of the circuit, reducing the power consumption of the chip and resisting the performance loss caused by deviation.
Claims (8)
1. A wide voltage self-adaptive adjusting system based on pulse latch time sequence monitoring is characterized by comprising a plurality of time sequence monitoring unit modules and a plurality of pulse generators, wherein the time sequence monitoring unit modules are formed by connecting a monitoring circuit with a time sequence monitoring function with latches in parallel; the method comprises the steps of comprehensively considering the load requirement of a pulse generator and the distance between the pulse generator and a time sequence monitoring unit module, clustering the plurality of time sequence monitoring unit modules, solving the position coordinates of the pulse generator when the minimum value of a target function is met by using a linear programming method and the capacitance limit met by the coordinates of the pulse generator and the time sequence monitoring unit module as a constraint condition, and inserting one pulse generator into each cluster and providing clock pulse signals for the time sequence monitoring unit modules in the same cluster;
the capacitance limit satisfied by the coordinates of the pulse generator and timing monitoring unit modules is shown in equation (2):
the objective function is shown in equation (3):
where (x, y) are the coordinates of the pulse generator, (a)i，bi) Is the coordinate of the ith time sequence monitoring unit module connected with the pulse generator, M represents the number of the time sequence monitoring unit modules connected with the pulse generator, CGeneral assemblyRepresenting the maximum load that the pulse generator can drive, CLatchRepresenting the gate capacitance of the MOS transistor in the latch, CTDRepresenting the gate capacitance, C, of the MOS transistor in the monitoring unitwrie1Representing the lateral track capacitance, Cwrie2Representing the vertical trace capacitance.
2. The wide voltage adaptive adjustment system based on pulse latch timing monitoring of claim 1, further comprising a control module, wherein the control module adaptively adjusts the operating voltage and/or frequency of the chip according to the timing monitoring result of the timing monitoring unit module.
3. The wide voltage adaptive adjustment system based on pulse latch timing monitoring of claim 1, wherein the input terminals of the monitoring circuit and the latch are both connected to the end of the monitored critical path, and the output of the monitoring circuit is a critical path timing early warning signal.
4. The adaptive wide voltage regulation system based on pulse latch timing monitoring of claim 1, wherein the pulse generator comprises an adaptable delay module for adapting the size of the delay to achieve the pulse width regulation.
5. The adaptive wide voltage regulation system based on pulse latch timing monitoring of claim 1, further comprising a dynamic OR circuit for collecting the monitoring results of the plurality of timing monitoring unit modules to obtain a total timing monitoring result and transmitting the total timing monitoring result to the voltage frequency control module.
6. The wide voltage adaptive regulation system based on pulse latch timing monitoring of claim 1, wherein the timing monitoring unit modules in the same cluster are relatively evenly distributed around the inserted pulse generator.
7. The clustering method applied to the wide voltage adaptive regulation system based on the pulse latch timing monitoring as claimed in claim 1 is characterized by comprising the following steps:
1) under the condition of not considering the wiring capacitance, determining the maximum load capacity of each pulse generator and the number of the maximum time sequence monitoring unit modules which can be connected with each pulse generator;
2) randomly selecting one from all deployed time sequence monitoring unit modules, selecting other time sequence monitoring unit modules adjacent to the selected time sequence monitoring unit module according to the number of the maximum time sequence monitoring unit modules which can be connected with each pulse generator and are determined in the step 1), and classifying the selected time sequence monitoring unit modules into the same cluster;
3) preliminarily determining the position of the pulse generator according to the positions of the time sequence monitoring unit modules contained in the clusters divided in the step 2);
4) the wiring capacitor is introduced as a constraint condition, and the pulse generator and the time sequence monitoring unit module connected with the pulse generator meet the capacitance limit shown in formula (2):
wherein, (x, y) is the coordinate of the pulse generator, (ai, bi) is the coordinate of the ith time sequence monitoring unit module connected with the pulse generator, M represents the number of the time sequence monitoring unit modules connected with the pulse generator, CGeneral assemblyRepresenting the maximum load that the pulse generator can drive, CLatchRepresenting the gate capacitance of the MOS transistor in the latch, CTDRepresenting the gate capacitance, C, of the MOS transistor in the monitoring unitwrie1Representing the lateral track capacitance, Cwrie2Representing the longitudinal wiring capacitance;
5) calculating the position coordinate of the pulse generator when the target function shown in the following formula (3) takes the minimum value by using a linear programming method and taking the capacitance limit of the pulse generator and the time sequence monitoring unit module connected with the pulse generator in the step 4) as a constraint condition;
6) if the step 5) is successful, calculating the coordinates of the pulse generator, namely, using the coordinates as the insertion position of the pulse generator; if the load capacity of the pulse generator is not enough to drive all the time sequence monitoring unit modules connected with the pulse generator after the wiring capacitor is introduced, removing one time sequence monitoring unit module on the basis of the original cluster, and repeating the operations of the step 3), the step 4) and the step 5) until all the time sequence monitoring unit modules are classified into a proper cluster and calculating the coordinates of the pulse generator.
8. The clustering method according to claim 7, wherein the calculation of the maximum number N of sequential monitoring unit modules that each pulse generator can connect to is as shown in formula (1) without considering the trace capacitance, if N is an integer, the number of sequential monitoring unit modules actually selected is N-1, and if N is a decimal, the number of sequential monitoring unit modules actually selected is an integer part of N:
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