CN112131172A - PCIe equipment chip initialization method for reducing time delay - Google Patents
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Abstract
The invention discloses a PCIe equipment chip initialization method for reducing time delay, which comprises the following steps: 1. and judging a fixed initialization mode according to the level value of the input control pin: if fixed initialization is needed, executing the step 2; otherwise, executing step 3; 2. reading fixed initialization content from the hard-wired logic, and writing the fixed content into a register and a memory area of a fixed address position in the chip to complete a fixed initialization process; 3. judging a configurable initialization mode: if configurable initialization is needed, executing step 4; otherwise, the PCIe equipment chip initialization process is ended; 4. and reading the configuration command from an erasable memory outside the chip, analyzing and executing the configuration command, writing corresponding contents into a register and a memory area of a corresponding address position inside the chip, and finishing the configurable initialization process. The invention has the characteristics of flexibility, rapidness and low cost, and can be widely applied to the technical field of information.
Description
Technical Field
The invention relates to the field of information equipment, in particular to a PCIe equipment chip initialization method for reducing time delay.
Background
PCIe has long dominated the field of computer expansion buses. In order to adapt the PCIe device chip to different host platforms, it is often necessary to initialize the functional parameters of the chip after the chip is powered on. These functional parameters include, but are not limited to, device number, speed level, address space, address mapping, etc.
With the increasing speed level of PCIe, analog circuits of PCIe transceivers in PCIe device chips are also more and more complex. In order to enable PCIe device chips of different production batches to obtain better electrical performance, in order to enable the PCIe device chips to be applicable to different host electrical environments, it is often necessary to initialize circuit parameters of the chips after the chips are powered on. These circuit parameters include, but are not limited to, phase locked loops, pre-emphasis, de-emphasis, equalizers, clock recovery circuits, etc.
These initialization requirements are related to the write operation to the chip internal registers and also to the write (firmware load) operation of the data blocks to the chip internal memory. Meanwhile, during the initialization process, a certain waiting time may need to be inserted.
The initialization of the PCIe device chip functional parameters and circuit parameters needs to be completed before establishing a PCIe link with the host. Due to the limitation of the PCIe protocol on the relevant time, the initialization work of the PCIe device chip is completed quickly and flexibly, which is an urgent need. In a conventional technical solution, many PCIe device chips complete initialization of the chips by a method of executing a program by an internal Micro Control Unit (MCU). The initialization method is flexible, but the initialization speed is slow, and the hardware cost is large.
Disclosure of Invention
The invention aims to overcome the defects of the background technology and provide a method for initializing a PCIe device chip with reduced time delay, so that the method has the characteristics of flexibility, rapidness and low cost.
The invention provides a PCIe equipment chip initialization method for reducing time delay, which comprises the following steps: s1, after the chip reset signal is released, according to the level value of the input control pin, judging the fixed initialization mode: if fixed initialization is required, go to step S2; otherwise, skipping step S2, executing step S3; s2, reading fixed initialization content from the hard-wired logic inside the chip, and writing the fixed content into the register and the memory area of the fixed address position inside the chip to complete the fixed initialization process; s3, judging the configurable initialization mode according to the level value of the input control pin: if configurable initialization is required, go to step S4; otherwise, skipping step S4, ending the PCIe device chip initialization process; s4, reading the configuration command from the erasable memory outside the chip, analyzing and executing the configuration command, writing the corresponding content into the register and memory area of the corresponding address position inside the chip, and completing the configurable initialization process.
In the above technical solution, in the step S2, a specific process before reading the fixed initialization content from the hard-wired logic inside the chip is as follows: s21, analyzing the universal initialization requirement of the PCIe equipment chip under a typical working scene; and S22, extracting the corresponding register and memory area and the initialization content thereof according to the general initialization requirement.
In the above technical solution, in the step S4, a specific process before the configuration command is read from the external erasable memory of the chip is as follows: s41, analyzing the special initialization requirement of the PCIe equipment chip in a specific application scene; s42, extracting corresponding registers, memory areas and initialization contents thereof according to the special initialization requirements; s43, comparing the special initialization requirement with the general initialization requirement to obtain difference points, and extracting corresponding register and memory areas and initialization content thereof according to the difference points.
In the above technical solution, in the step S4, before the configuration command is read from the external erasable memory of the chip, the first address of the configuration command in the erasable memory is obtained from the hard-wired logic.
In the above technical solution, the specific process of step S4 is as follows: s41', reading a configuration command from an erasable memory outside the chip; s42', the read configuration command is analyzed, and the next operation is carried out according to the operation code; s43', if the operation code of the configuration command is not the exit command, executing corresponding operation according to the operation code content; s44', after the configuration command is executed, incrementing the address of the configuration command by 8 bytes to obtain the address of the next configuration command in the configuration command storage module; s45', if the operation code of the configuration command is an exit command, ending the configurable initialization process of the chip; s46 ', repeating steps S41', S42 ', S43', S44 'until an exit command is read, and exiting the configurable initialization process by the step S46'.
In the above technical solution, in the step S4, a specific process of executing the configuration command is as follows: s401, when the read configuration command is a data block writing command, directly obtaining a source address, a destination address and a transmission length of a data block to be written from the configuration command; s402, reading a piece of data in the data block to be written from a source address in the configuration command storage module; s403, writing the read data into a destination address in a memory area inside the chip; s404, subtracting 1 from the transmission length to obtain the transmission length of the residual data block to be written; s405, if the transmission length of the residual data block to be written is greater than 0, adding 4 to the source address and the destination address to obtain the source address and the destination address of the next data in the data block to be written; s406, repeatedly executing the steps S401, S402, S403, S404 and S405 until the transmission length of the remaining data block to be written is reduced to 0, and finishing the command of writing the data block; s407, when the read configuration command is a register writing command, directly obtaining a destination address and data to be written from the configuration command; s408, writing the data to be written into the destination address in the register area inside the chip to complete the register writing command; and S409, when the read configuration command is the idle operation command, performing no operation and finishing the idle operation command.
In the above technical solution, in the step S4, the configuration command includes the following encoding format: (1) each configuration command consists of 2 command fields, each 32 bits; (2) the 1 st command field contains an 8-bit opcode and a 24-bit operation address; (3) the 2 nd command field contains 32 bits of operation data.
In the above technical solution, the specific processes of steps S1-S4 are as follows: s11, fixing the initialization stage, writing fixed initialization content into a register area including a device number register, a speed level register, an address space register and an address mapping register in the PCIe module by a hardware state machine in the chip; meanwhile, writing fixed initialization content into a circuit parameter firmware memory in the PCIe module; s12, in the initialization stage, the hardware state machine in the chip updates the content of the address 2 position in the circuit parameter firmware memory.
In the above technical solution, the specific processes of steps S1-S4 are as follows: s21, fixing the initialization stage, writing fixed initialization content into a register area including a device number register, a speed level register, an address space register and an address mapping register in the PCIe module by a hardware state machine in the chip; meanwhile, writing fixed initialization content into a circuit parameter firmware memory in the PCIe module; s22, skipping the configurable initialization phase, without requiring configurable initialization of any register or memory area.
In the above technical solution, the specific processes of steps S1-S4 are as follows: s31, the fixed initialization content does not meet the application requirement, and the fixed initialization step is directly skipped; and S32, performing a configurable initialization step on all registers and memory areas.
The PCIe equipment chip initialization method for reducing time delay has the following beneficial effects: the invention combines fixed initialization with configurable initialization, takes the fixed initialization as a main body, takes the configurable initialization as correction and supplement, takes the speed advantage of the fixed initialization and the flexibility advantage of the configurable initialization into consideration, and solves the problem that the chip of PCIe equipment needs to be quickly and flexibly initialized in the process of adapting to different host platforms. In practical application, the PCIe device chip can obtain better initialization performance by reasonably extracting the fixed initialization content and the configurable initialization content, and lower initialization cost is realized due to the fact that dependence on hardware purchase is reduced.
Drawings
FIG. 1 is a schematic diagram of a hardware load-bearing architecture of a latency-reduced PCIe device chip initialization method of the present invention;
FIG. 2 is a flowchart illustrating a method for initializing a reduced latency PCIe device chip in accordance with the present invention;
FIG. 3 is a schematic flow chart illustrating the process of extracting fixed initialization content and configuration commands in the method for initializing a reduced latency PCIe device chip in accordance with the present invention;
FIG. 4 is a flowchart illustrating the step S4 executed by the hardware state machine inside the chip in the method for initializing the chip of the PCIe device with reduced latency according to the present invention;
FIG. 5 is a schematic flow chart of a hardware state machine inside a chip executing a write data block, a write register and a no-operation command in the method for initializing a chip of a PCIe device with reduced latency according to the present invention;
FIG. 6 is a schematic structural diagram of a configuration command encoding format in the latency reduction PCIe device chip initialization method of the present invention;
FIG. 7 is a flowchart illustrating a first embodiment of a latency reduction PCIe device chip initialization method of the present invention;
FIG. 8 is a flowchart illustrating a second embodiment of a latency reduction PCIe device chip initialization method of the present invention;
fig. 9 is a flowchart illustrating a third embodiment of a method for initializing a PCIe device chip with reduced latency according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and examples, which should not be construed as limiting the invention.
Referring to fig. 1, a hardware carrier architecture required by the PCIe device chip initialization method with reduced latency according to the present invention includes the following components: the device comprises a fixed initialization module, a fixed initialization content storage module, a configurable initialization module, a configuration command storage module, an initialization control module and a PCIe module.
101: and the fixed initialization module consists of a hardware state machine in the chip and is used for reading the fixed initialization content and finishing the fixed initialization process of the chip.
102: and the fixed initialization content storage module consists of hard-wired logic inside the chip and is used for storing the fixed initialization content.
103: the configurable initialization module consists of a hardware state machine and hard-wired logic inside the chip and is used for finishing reading, analyzing and executing the configuration command so as to finish the configurable initialization process of the chip.
104: and the configuration command storage module consists of an erasable memory outside the chip and is used for storing the configuration command.
105: and the initialization control module consists of a hardware state machine in the chip and is used for controlling the whole initialization process of the chip and selecting a corresponding initialization mode according to the level value input into the control pin.
106: initialization related registers and memory areas in the PCIe module include, but are not limited to, device number registers, speed class registers, address space registers, address mapping registers, and circuit parameter firmware memory. The initialization work of the PCIe device chip includes data writing and data block writing (firmware loading) to the above-described registers and memory area.
Referring to fig. 2, a preferred embodiment of the fast and flexible PCIe device chip initialization method according to the present invention includes the following steps:
201: after the chip reset signal is released, the fixed initialization mode is judged according to the level value of the input control pin: if fixed initialization is needed, executing step 202; otherwise, step 202 is skipped and step 203 is performed.
202: and reading the fixed initialization content from the hard-wired logic inside the chip, and writing the fixed content into the register and the memory area of the fixed address position inside the chip to complete the fixed initialization process.
203: judging a configurable initialization mode according to a level value of an input control pin: if configurable initialization is needed, executing step 204; otherwise, skipping step 204 and ending the initialization process of the PCIe device chip.
204: and reading the configuration command from an erasable memory outside the chip, analyzing and executing the configuration command, writing corresponding contents into a register and a memory area of a corresponding address position inside the chip, and finishing the configurable initialization process.
Referring to fig. 3, the process of extracting the fixed initialization content includes the following steps:
301: analyzing the common initialization requirements of the PCIe device chip under a typical working scene.
302: and extracting corresponding registers, memory areas and initialization contents thereof according to the general initialization requirements.
303: the register and the memory area corresponding to the general initialization requirement and the initialization content thereof are fixed initialization content.
Referring to fig. 3, the extraction process of the configuration command includes the following steps:
304: analyzing the special initialization requirements of the PCIe device chip under a specific application scene.
305: and extracting corresponding registers, memory areas and initialization contents thereof according to special initialization requirements.
306: and comparing the special initialization requirement with the general initialization requirement to obtain difference points, and extracting corresponding register and memory areas and initialization contents thereof according to the difference points.
307: the register and the memory area corresponding to the difference point between the special initialization requirement and the general initialization requirement and the initialization content thereof are configuration commands.
Referring to fig. 4, the hardware state machine inside the chip performs a configurable initialization process, further comprising the following steps:
401: and the hardware state machine in the chip obtains the first address of the configuration command in the configuration command storage module from the hard-wired logic in the chip.
402: and reading the configuration command from the configuration command storage module by a hardware state machine in the chip.
403: the hardware state machine in the chip analyzes the read configuration command and performs the next operation according to the operation code, which is as follows:
the hardware state machine in the chip analyzes and executes the read configuration command: if the reading is the exit command, the hardware state machine in the chip ends the configurable initialization process; if the read command is a register writing command, the hardware state machine in the chip writes corresponding data into the register at the corresponding address position in the chip, and then continues to read the next command from the erasable memory; if the read command is a data block writing command, a hardware state machine in the chip sequentially reads data blocks with corresponding lengths from corresponding source address positions in the erasable memory and writes the data blocks into a memory at corresponding destination address positions in the chip; if the read command is the idle operation command, the hardware state machine in the chip does not do any operation, and the next configuration command is continuously read from the erasable memory;
404: and if the operation code of the configuration command is not the exit command, executing corresponding operation according to the content of the operation code.
405: after the configuration command is executed, the address of the configuration command is increased by 8 bytes to obtain the address of the next configuration command in the configuration command storage module.
The configuration command for configurable initialization adopts a compact and efficient coding format, and continuous 8 bytes are used for representing elements such as operation codes, operation addresses, operation data and the like.
406: and if the operation code of the configuration command is an exit command, ending the configurable initialization flow of the chip.
The steps 402, 403, 404, 405 are repeatedly executed until an exit command is read, and the configurable initialization process is exited from step 406.
Referring to fig. 5, the process of executing a configuration command by the hardware state machine inside the chip further includes the following steps:
501: when the configuration command read by the hardware state machine in the chip is a data block writing command, the source address, the destination address and the transmission length of the data block to be written can be directly obtained from the configuration command.
502: and the hardware state machine in the chip reads one (4-byte) data in the data block to be written from the source address in the configuration command storage module.
503: the hardware state machine inside the chip writes the read (4 bytes) data into the destination address in the internal memory area of the chip.
504: and the hardware state machine in the chip performs minus 1 operation on the transmission length to obtain the transmission length of the residual data block to be written.
505: and if the transmission length of the residual data block to be written is greater than 0, adding 4 operations to the source address and the destination address to obtain the source address and the destination address of the next data in the data block to be written.
And the hardware state machine in the chip repeatedly executes the steps of 501, 502, 503, 504 and 505 until the transmission length of the residual data block to be written is reduced to 0, and the command of writing the data block is completed.
506: when the read configuration command is a register writing command, the hardware state machine in the chip can directly obtain a destination address and data to be written from the configuration command.
507: and the hardware state machine in the chip writes the data to be written into the destination address in the register area in the chip to complete the register writing command.
508: and when the read configuration command is a null operation command, the hardware state machine in the chip does not perform any operation, and the null operation command is completed.
Referring to fig. 6, the present invention provides a configuration command further comprising the following encoding format:
(1) each configuration command consists of 2 command fields, each 32 bits;
(2) the 1 st command field contains an 8-bit opcode and a 24-bit operation address;
(3) the 2 nd command field contains 32 bits of operation data.
Referring to FIG. 7, a diagram illustrating initialization of the register and the memory according to the first embodiment of the invention is shown.
701: in the fixed initialization stage, a hardware state machine in the chip writes fixed initialization content into register areas such as a device number register, a speed level register, an address space register, an address mapping register and the like in a PCIe module; and simultaneously, writing fixed initialization content into a circuit parameter firmware memory in the PCIe module.
702: in practical application, except that the content of the address 2 position in the circuit parameter firmware memory needs to be corrected, the content written by fixed initialization in other registers and memory areas can meet the application requirement; therefore, the initialization phase can be configured, and the hardware state machine inside the chip only needs to update the content of the address 2 position in the circuit parameter firmware memory.
703: after initialization is finished, except that the content of the address 2 position in the circuit parameter firmware memory is written by configurable initialization, the content of other registers and memory positions are written by fixed initialization.
Referring to FIG. 8, a diagram illustrating initialization of the register and the memory according to a second embodiment of the invention is shown.
801: in the fixed initialization stage, a hardware state machine in the chip writes fixed initialization content into register areas such as a device number register, a speed level register, an address space register, an address mapping register and the like in a PCIe module; and simultaneously, writing fixed initialization content into a circuit parameter firmware memory in the PCIe module.
802: in practical application, the content written by all registers and memory areas through fixed initialization can meet the application requirement; the hardware state machine in the chip is not required to make any correction and supplement on the fixed initialization; therefore, the hardware state machine inside the chip can directly skip the configuration initialization stage without performing configurable initialization on any register or memory area.
803: after initialization is completed, the contents of all registers and memory areas are written by fixed initialization.
Referring to fig. 9, a register and a memory according to a third embodiment of the invention are initialized.
901: in practical application, the fixed initialized content does not meet the application requirement, and all the fixed initialized content needs to be corrected; therefore, in order to obtain a faster initialization speed, a hardware state machine inside the chip directly skips the fixed initialization step; all registers and memory areas do not contain any fixed initialization content.
902: and performing configurable initialization on all registers and memory areas by a hardware state machine in the chip as required.
903: after initialization is completed, the contents of all registers and memory areas are written by configurable initialization.
The fixed initialization is to write fixed contents into a register and a memory area of a fixed address position in a chip; the fixed initialization is used for meeting the general initialization requirement of the chip in a typical application scene; the fixed initialization is completed by a hardware state machine and a hard-wired logic inside the chip, and the execution speed is high; the fixed initialization content is stored in the hard-wired logic inside the chip, and the chip cannot be modified after being produced if the fixed initialization content is determined in the chip development process.
The configurable initialization is to write corresponding contents into a register and a memory area of a corresponding address position in the chip according to a configuration command; the configurable initialization is used for meeting the special initialization requirement of the chip in a specific application scene and is the correction and supplement of the fixed initialization; the configurable initialization is completed by reading, analyzing and executing configuration commands by a hardware state machine in the chip, and the execution speed is slower than that of fixed initialization; the configurable initialization content is stored in an erasable memory outside the chip in the form of a configuration command, and can be updated as required in the actual application process.
The configurable initialized configuration command provides register writing operation, and a hardware state machine in the chip can write corresponding contents into a register of a corresponding address position in the chip according to the configuration command;
the configurable initialized configuration command provides a data block writing operation, and a hardware state machine in the chip can write a data block with a corresponding length into a memory at a corresponding address position in the chip from a corresponding address position in an erasable memory outside the chip according to the configuration command;
the configuration command of configurable initialization provides null operation, and a hardware state machine in the chip can insert wait in the configurable initialization process according to the configuration command;
all configuration command code combinations except the write register, the write data block and the idle operation are interpreted as exit commands by a hardware state machine in the chip, and can be used for ending the configurable initialization process.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Those not described in detail in this specification are within the skill of the art.
Claims (10)
1. A PCIe device chip initialization method for reducing delay is characterized in that: the method comprises the following steps:
s1, after the chip reset signal is released, according to the level value of the input control pin, judging the fixed initialization mode: if fixed initialization is required, go to step S2; otherwise, skipping step S2, executing step S3;
s2, reading fixed initialization content from the hard-wired logic inside the chip, and writing the fixed content into the register and the memory area of the fixed address position inside the chip to complete the fixed initialization process;
s3, judging the configurable initialization mode according to the level value of the input control pin: if configurable initialization is required, go to step S4; otherwise, skipping step S4, ending the PCIe device chip initialization process;
s4, reading the configuration command from the erasable memory outside the chip, analyzing and executing the configuration command, writing the corresponding content into the register and memory area of the corresponding address position inside the chip, and completing the configurable initialization process.
2. The reduced latency PCIe device chip initialization method of claim 1 wherein: in step S2, the specific process before reading the fixed initialization content from the hard-wired logic inside the chip is as follows:
s21, analyzing the universal initialization requirement of the PCIe equipment chip under a typical working scene;
and S22, extracting the corresponding register and memory area and the initialization content thereof according to the general initialization requirement.
3. The reduced latency PCIe device chip initialization method of claim 2, wherein: in step S4, the specific process before the configuration command is read from the external rewritable memory is as follows:
s41, analyzing the special initialization requirement of the PCIe equipment chip in a specific application scene;
s42, extracting corresponding registers, memory areas and initialization contents thereof according to the special initialization requirements;
s43, comparing the special initialization requirement with the general initialization requirement to obtain difference points, and extracting corresponding register and memory areas and initialization content thereof according to the difference points.
4. The reduced latency PCIe device chip initialization method of claim 1 wherein: in step S4, before the configuration command is read from the external erasable memory, the first address of the configuration command in the erasable memory is obtained from the hard-wired logic.
5. The reduced latency PCIe device chip initialization method of claim 1 wherein: the specific process of step S4 is as follows:
s41', reading a configuration command from an erasable memory outside the chip;
s42', the read configuration command is analyzed, and the next operation is carried out according to the operation code;
s43', if the operation code of the configuration command is not the exit command, executing corresponding operation according to the operation code content;
s44', after the configuration command is executed, incrementing the address of the configuration command by 8 bytes to obtain the address of the next configuration command in the configuration command storage module;
s45', if the operation code of the configuration command is an exit command, ending the configurable initialization process of the chip;
s46 ', repeating steps S41', S42 ', S43', S44 'until an exit command is read, and exiting the configurable initialization process by the step S46'.
6. The reduced latency PCIe device chip initialization method of claim 1 wherein: in step S4, the specific process of executing the configuration command is as follows:
s401, when the read configuration command is a data block writing command, directly obtaining a source address, a destination address and a transmission length of a data block to be written from the configuration command;
s402, reading a piece of data in the data block to be written from a source address in the configuration command storage module;
s403, writing the read data into a destination address in a memory area inside the chip;
s404, subtracting 1 from the transmission length to obtain the transmission length of the residual data block to be written;
s405, if the transmission length of the residual data block to be written is greater than 0, adding 4 to the source address and the destination address to obtain the source address and the destination address of the next data in the data block to be written;
s406, repeatedly executing the steps S401, S402, S403, S404 and S405 until the transmission length of the remaining data block to be written is reduced to 0, and finishing the command of writing the data block;
s407, when the read configuration command is a register writing command, directly obtaining a destination address and data to be written from the configuration command;
s408, writing the data to be written into the destination address in the register area inside the chip to complete the register writing command;
and S409, when the read configuration command is the idle operation command, performing no operation and finishing the idle operation command.
7. The reduced latency PCIe device chip initialization method of claim 5, wherein: in step S4, the configuration command includes the following encoding format:
(1) each configuration command consists of 2 command fields, each 32 bits;
(2) the 1 st command field contains an 8-bit opcode and a 24-bit operation address;
(3) the 2 nd command field contains 32 bits of operation data.
8. The reduced latency PCIe device chip initialization method of claim 1 wherein: the specific processes of the steps S1-S4 are as follows:
s11, fixing the initialization stage, writing fixed initialization content into a register area including a device number register, a speed level register, an address space register and an address mapping register in the PCIe module by a hardware state machine in the chip; meanwhile, writing fixed initialization content into a circuit parameter firmware memory in the PCIe module;
s12, in the initialization stage, the hardware state machine in the chip updates the content of the address 2 position in the circuit parameter firmware memory.
9. The reduced latency PCIe device chip initialization method of claim 1 wherein: the specific processes of the steps S1-S4 are as follows:
s21, fixing the initialization stage, writing fixed initialization content into a register area including a device number register, a speed level register, an address space register and an address mapping register in the PCIe module by a hardware state machine in the chip; meanwhile, writing fixed initialization content into a circuit parameter firmware memory in the PCIe module;
s22, skipping the configurable initialization phase, without requiring configurable initialization of any register or memory area.
10. The reduced latency PCIe device chip initialization method of claim 1 wherein: the specific processes of the steps S1-S4 are as follows:
s31, the fixed initialization content does not meet the application requirement, and the fixed initialization step is directly skipped;
and S32, performing a configurable initialization step on all registers and memory areas.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113553101A (en) * | 2021-07-27 | 2021-10-26 | 上海信昊信息科技有限公司 | PCIE (peripheral component interface express) exchange chip port register initialization method with variable loading frequency |
| CN116049090A (en) * | 2022-12-30 | 2023-05-02 | 成都电科星拓科技有限公司 | Chip initialization data storage method and chip initialization method |
| CN116578352A (en) * | 2023-07-11 | 2023-08-11 | 沐曦集成电路(上海)有限公司 | Chip initializing system |
| CN116719581A (en) * | 2023-07-11 | 2023-09-08 | 沐曦集成电路(上海)有限公司 | Chip multi-instance module initializing system |
| CN116893858A (en) * | 2023-09-11 | 2023-10-17 | 西安智多晶微电子有限公司 | Configuration method for fast starting PCIe (peripheral component interconnect express) by FPGA (field programmable gate array) |
| CN116991484A (en) * | 2023-05-26 | 2023-11-03 | 广东匠芯创科技有限公司 | Initializing method, accessing method and related device of storage device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4933845A (en) * | 1987-09-04 | 1990-06-12 | Digital Equipment Corporation | Reconfigurable bus |
| US20070300050A1 (en) * | 2006-06-08 | 2007-12-27 | Zimmer Vincent J | Maintaining early hardware configuration state |
| US20090055637A1 (en) * | 2007-08-24 | 2009-02-26 | Ingemar Holm | Secure power-on reset engine |
| CN102662711A (en) * | 2012-04-06 | 2012-09-12 | 中兴通讯股份有限公司 | Method and device for quickly initiating chip |
| CN108037965A (en) * | 2017-12-29 | 2018-05-15 | 飞天诚信科技股份有限公司 | A kind of method and device for reading and writing objective chip |
| CN109725941A (en) * | 2018-12-18 | 2019-05-07 | 深圳吉迪思电子科技有限公司 | A kind of programmable initial method and system for display driver chip |
-
2020
- 2020-08-28 CN CN202010884474.2A patent/CN112131172A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4933845A (en) * | 1987-09-04 | 1990-06-12 | Digital Equipment Corporation | Reconfigurable bus |
| US20070300050A1 (en) * | 2006-06-08 | 2007-12-27 | Zimmer Vincent J | Maintaining early hardware configuration state |
| US20090055637A1 (en) * | 2007-08-24 | 2009-02-26 | Ingemar Holm | Secure power-on reset engine |
| CN102662711A (en) * | 2012-04-06 | 2012-09-12 | 中兴通讯股份有限公司 | Method and device for quickly initiating chip |
| CN108037965A (en) * | 2017-12-29 | 2018-05-15 | 飞天诚信科技股份有限公司 | A kind of method and device for reading and writing objective chip |
| CN109725941A (en) * | 2018-12-18 | 2019-05-07 | 深圳吉迪思电子科技有限公司 | A kind of programmable initial method and system for display driver chip |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113553101A (en) * | 2021-07-27 | 2021-10-26 | 上海信昊信息科技有限公司 | PCIE (peripheral component interface express) exchange chip port register initialization method with variable loading frequency |
| CN116049090A (en) * | 2022-12-30 | 2023-05-02 | 成都电科星拓科技有限公司 | Chip initialization data storage method and chip initialization method |
| CN116991484A (en) * | 2023-05-26 | 2023-11-03 | 广东匠芯创科技有限公司 | Initializing method, accessing method and related device of storage device |
| CN116991484B (en) * | 2023-05-26 | 2024-02-06 | 广东匠芯创科技有限公司 | Initializing method, accessing method and related device of storage device |
| CN116578352A (en) * | 2023-07-11 | 2023-08-11 | 沐曦集成电路(上海)有限公司 | Chip initializing system |
| CN116719581A (en) * | 2023-07-11 | 2023-09-08 | 沐曦集成电路(上海)有限公司 | Chip multi-instance module initializing system |
| CN116578352B (en) * | 2023-07-11 | 2023-09-22 | 沐曦集成电路(上海)有限公司 | Chip initializing system |
| CN116719581B (en) * | 2023-07-11 | 2024-02-02 | 沐曦集成电路(上海)有限公司 | Chip multi-instance module initializing system |
| CN116893858A (en) * | 2023-09-11 | 2023-10-17 | 西安智多晶微电子有限公司 | Configuration method for fast starting PCIe (peripheral component interconnect express) by FPGA (field programmable gate array) |
| CN116893858B (en) * | 2023-09-11 | 2023-12-12 | 西安智多晶微电子有限公司 | Configuration method for fast starting PCIe (peripheral component interconnect express) by FPGA (field programmable gate array) |
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