CN112103932A - Electrostatic clamping circuit and chip structure - Google Patents
Electrostatic clamping circuit and chip structure Download PDFInfo
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- CN112103932A CN112103932A CN202010932032.0A CN202010932032A CN112103932A CN 112103932 A CN112103932 A CN 112103932A CN 202010932032 A CN202010932032 A CN 202010932032A CN 112103932 A CN112103932 A CN 112103932A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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Abstract
The application provides an electrostatic clamping circuit and a chip structure. The electrostatic clamping circuit comprises: a detection unit connected to the power supply terminal for detecting whether a voltage of the power supply terminal rises; the input end of the first switch tube is connected with the power supply end, and the output end of the first switch tube is connected with the grounding end; the phase inverter unit comprises N phase inverters which are sequentially cascaded, the input end of the 1 st level phase inverter of the phase inverter unit is connected with the output end of the detection unit, and the output end of the N nth level phase inverter of the phase inverter unit is connected with the grid electrode of the first switch tube; the inverter unit is used for controlling the first switching tube to be conducted when the voltage of the power supply end rises; and the source electrode of the second switching tube is connected with a preset voltage, the drain electrode of the second switching tube is connected with the input end of the Nth-stage phase inverter of the phase inverter unit, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the second switching tube is used for prolonging the conduction time of the first switching tube. The application can improve the charge release rate and improve the safety of the circuit.
Description
Technical Field
The present disclosure relates to power supply circuits, and particularly to an electrostatic clamp circuit and a chip structure.
Background
The structure of a conventional power supply clamp is shown in fig. 1, and includes: the RC unit, an inverter, a switch tube T0 and a diode D0. The inverter consists of a PMOS transistor P0 and an NMOS transistor N0. When the voltage of the power supply terminal VDD suddenly rises due to external static electricity, the voltage of the point a suddenly rises due to the existence of the capacitor C0, the voltage of the point a drives the inverter to drop the voltage of the point B, so that the switching tube T0 is turned on, the charge of the power supply terminal VDD is released, the voltage of the power supply terminal VDD is not too high, and the internal circuit can be protected. When the VSS voltage suddenly rises, the diode D0 will conduct, draining the charge, thereby protecting the internal circuitry.
However, the potential at point a is first raised and then discharged through resistor R0 to gradually drop to VSS, and at the same time, point B is controlled by point a to be first pulled low and then gradually raised until it rises to the voltage at power supply terminal VDD. Since the voltage at the point B is gradually increased, the opening degree of the switching tube T0 is gradually decreased until it is turned off. Therefore, the time for releasing the charges at the power supply terminal VDD is too short, which causes the problem of incomplete discharge, and also causes the problem of charge accumulation, which easily damages the chip or the integrated circuit.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
An object of the embodiments of the present application is to provide an electrostatic clamp circuit and a chip structure, which can improve the charge release time, so that the charge release to the power supply end is more thorough, and the safety of the integrated circuit is further improved.
An embodiment of the present application provides an electrostatic clamp circuit, including:
a detection unit connected to the power supply terminal for detecting whether a voltage of the power supply terminal rises;
the input end of the first switch tube is connected with the power supply end, and the output end of the first switch tube is connected with the grounding end;
the phase inverter unit comprises N phase inverters which are sequentially cascaded, the input end of the 1 st level phase inverter of the phase inverter unit is connected with the output end of the detection unit, and the output end of the N nth level phase inverter of the phase inverter unit is connected with the grid electrode of the first switch tube; the phase inverter unit is used for controlling the first switching tube to be conducted when the voltage of the power supply end rises;
and the source electrode of the second switching tube is connected with a preset voltage, the drain electrode of the second switching tube is connected with the input end of the Nth-stage phase inverter of the phase inverter unit, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the second switching tube is used for prolonging the conduction time of the first switching tube.
In the embodiment of the application, the conduction time of the first switch tube when releasing charges is prolonged by adopting the second switch tube, so that the charge release amount is improved, the discharge of the power supply end is more thorough, and the protection effect on the integrated circuit is better.
Optionally, in the electrostatic clamp according to this embodiment of the present application, the electrostatic clamp further includes:
and the cathode of the diode is connected with the power supply end, and the anode of the diode is connected with the grounding end.
Optionally, in the electrostatic clamp according to this embodiment of the present application, the electrostatic clamp further includes:
one end of the second resistor is connected with the source electrode of the second switch tube, and the other end of the second resistor is connected with the grid electrode of the second switch tube.
In the embodiment of the application, the rising speed of the grid voltage of the first switch tube is increased after the discharge is completed through the second resistor, so that the first switch tube can be turned off more quickly after the discharge is completed, the power supply end is prevented from leaking electricity to the grounding end after the discharge is completed, and the power consumption can be reduced.
Optionally, in the electrostatic clamp circuit according to this embodiment of the application, the detection unit includes a resistive element and a capacitive element, one end of the capacitive element is connected to a power supply terminal, the other end of the capacitive element is connected to one end of the resistive element as an output terminal of the detection unit, and the other end of the resistive element is connected to a ground terminal.
Optionally, in the electrostatic clamp circuit according to this embodiment of the present application, N is an odd number greater than 2, the first switching tube and the second switching tube are both P-channel field effect transistors, and a preset voltage applied to a source of the second switching tube is a first high level.
Optionally, in the electrostatic clamp circuit according to this embodiment of the present application, a source of the second switching tube is connected to the power supply terminal.
Optionally, in the electrostatic clamp circuit according to this embodiment of the present application, N is an even number greater than 1, the first switching tube and the second switching tube are both P-channel field effect transistors, and a preset voltage applied to a source of the second switching tube is a first low level.
Optionally, in the electrostatic clamp circuit according to this embodiment of the present application, a source of the second switch tube is connected to a ground terminal.
Optionally, in the electrostatic clamp circuit according to this embodiment of the application, the detection unit includes a resistive element and a capacitive element, one end of the capacitive element is connected to a ground terminal, the other end of the capacitive element and one end of the resistive element are connected to an output terminal of the detection unit, and the other end of the resistive element is connected to a power supply terminal.
Optionally, in the electrostatic clamp circuit according to this embodiment of the present application, N is an odd number greater than 2, the first switching tube and the second switching tube are both N-channel field effect transistors, and a preset voltage applied to a source of the second switching tube is a first low level.
Optionally, in the electrostatic clamp circuit according to this embodiment of the present application, a source of the second switch tube is connected to the ground terminal.
Optionally, in the electrostatic clamp circuit according to this embodiment of the present application, N is an even number greater than 1, the first switching tube and the second switching tube are both P-channel field effect transistors, and a preset voltage applied to a source of the second switching tube is a first high level.
Optionally, in the electrostatic clamp according to an embodiment of the present application, the capacitive element includes a first field effect transistor, a source and a drain of the first field effect transistor are connected as one end of the capacitive element, and a gate of the first field effect transistor is connected as the other end of the capacitive element.
Optionally, in the electrostatic clamp according to this embodiment of the application, the resistive element includes a second field effect transistor, a source and a drain of the second field effect transistor respectively serve as two ends of the resistive element, and a gate of the second field effect transistor is connected to a preset voltage so that the second field effect transistor remains normally on.
Optionally, in the electrostatic clamp circuit according to this embodiment of the present disclosure, the first switch and/or the second switch is a finfet.
In a second aspect, an embodiment of the present application further provides a chip structure, including:
a chip having a ground pin and a power supply pin;
and a power supply clamping circuit, wherein the power supply end of the power supply clamping circuit is connected with the power supply pin, the grounding end of the power supply clamping circuit is connected with the grounding pin, and the power supply clamping circuit is any one of the power supply clamping circuits.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic diagram of an electrostatic clamp in the prior art.
Fig. 2 is a schematic diagram of a first configuration of an electrostatic clamp according to some embodiments of the present disclosure.
Fig. 3 is a second schematic diagram of an electrostatic clamp according to some embodiments of the present disclosure.
Fig. 4 is a schematic diagram of a third configuration of an electrostatic clamp according to some embodiments of the present disclosure.
Fig. 5 is a schematic diagram of a fourth configuration of an electrostatic clamp according to some embodiments of the present disclosure.
Fig. 6 is a fifth block diagram of an electrostatic clamp according to some embodiments of the present disclosure.
Fig. 7 is a sixth configuration of an electrostatic clamp according to some embodiments of the present disclosure.
Fig. 8 is a schematic diagram of a seventh configuration of an electrostatic clamp in some embodiments of the present application.
Fig. 9 is an eighth schematic diagram of an electrostatic clamp according to some embodiments of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it should be noted that the terms "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Further, in the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
It should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
The embodiment of the application provides an electrostatic clamp circuit, which is connected between a grounding pin and a power supply pin of an integrated circuit and used for eliminating sudden voltage rise of the power supply pin caused by an ESD event, so that the effect of protecting the integrated circuit is achieved. The electrostatic clamping circuit comprises: a detection unit for detecting whether a voltage at the power supply terminal rises; the input end of the first switch tube is connected with the power supply end, the output end of the first switch tube is connected with the grounding end, and the grid electrode of the first switch tube is connected with the first node; the inverter unit comprises N inverters which are sequentially cascaded, the input end of the 1 st-level inverter of the inverter unit is connected with the second node, and the output end of the N-level inverter of the inverter unit is connected with the first node; the phase inverter unit is used for controlling the first switching tube to be conducted when the voltage of the power supply end rises; and the source electrode of the second switching tube is connected with a preset voltage, the drain electrode of the second switching tube is connected with the input end of the Nth-stage phase inverter of the phase inverter unit, the grid electrode of the second switching tube is connected with the first node, and the second switching tube prolongs the conduction time of the first switching tube. The power supply end is connected with a power supply pin of the integrated circuit, and the grounding end is connected with a grounding pin of the integrated circuit.
Compared with the prior art shown in fig. 1, the electrostatic clamping circuit provided by the embodiment of the application prolongs the conducting time of the first switching tube when releasing charges by adopting the second switching tube, so that the charge releasing amount is improved, the discharge of the power supply end is more thorough, and the protection effect on the integrated circuit is better.
The electrostatic clamp circuit will be described in detail with reference to the drawings.
Referring to fig. 2, fig. 2 is a circuit structure diagram of an electrostatic clamp circuit according to an embodiment of the present disclosure. The electrostatic clamping circuit comprises: the detection circuit comprises a detection unit 101, a first switch tube T11, an inverter unit 102, a second switch tube T12 and a diode D11.
The detecting unit 101 is connected between a power supply terminal VDD and a ground terminal VSS, an output terminal of the detecting unit 101, that is, the second node a in fig. 2, is connected to an input terminal of the 1 st-level inverter of the inverter unit 102, an output terminal of the nth and the inverter of the inverter unit 102 is connected to the gate of the first switch transistor T11, a connection node between the output terminal of the nth and the inverter of the inverter unit 102 and the gate of the first switch transistor T11 is defined as a first node B, an input terminal of the first switch transistor T11 is connected to the power supply terminal VDD, and an output terminal of the first switch transistor T11 is connected to the ground terminal VSS. The gate of the second switch transistor T12 and the gate of the first switch transistor T11 are connected to a first node, the source of the second switch transistor T12 is connected to a predetermined voltage, the drain of the second switch transistor T12 and the input terminal of the nth stage inverter are connected to a point C, the anode of the diode D11 is connected to the ground VSS, and the cathode of the diode D11 is connected to the power supply terminal VDD.
Specifically, the detecting unit 101 includes a capacitive element 1011 and a resistive element 1012 connected to the second node. One end of the capacitive element 1011 is connected to the power supply terminal VDD, the other end of the capacitive element 1011 is connected to one end of the resistive element 1012 as the output terminal of the detecting unit 101, and the other end of the resistive element 1012 is connected to the ground terminal VSS. The detecting unit 101 is configured to detect whether the voltage of the power supply terminal rises, and pull up the voltage of the second node when the voltage of the power supply terminal rises.
The capacitive element 1011 may include a first capacitor, or the capacitive element 1011 may include a first field effect transistor, a source and a drain of which are connected as one end of the capacitive element 1011, and a gate of which is used as the other end of the capacitive element.
The resistive element 1012 may include one or more first resistors connected in series or in parallel, or the resistive element 1012 may further include a second field effect transistor, a source and a drain of the second field effect transistor are respectively used as two ends of the resistive element 1012, and a gate of the second field effect transistor is connected to a predetermined electrical signal to maintain a constant conduction. The equivalent resistance value of the resistive element can be controlled by controlling the voltage value of the preset electric signal.
The first switch transistor T11 is a P-channel fet, the source of the first switch transistor T11 is connected to the power supply terminal VDD, and the drain of the first switch transistor is connected to the ground terminal VSS. The first switch transistor T11 is used for switching on or off under the control of the first node voltage, and the first switch transistor T11 is used for discharging the charges accumulated at the power supply terminal when being switched on, thereby pulling down the voltage of the power supply terminal VDD. The first switch transistor T11 may be a P-type finfet transistor.
The inverter unit 102 includes N inverters 1021 cascaded in sequence. The input end of the 1 st-stage inverter is connected with the second node, and the output end of the Nth-stage inverter and the grid electrode of the first switching tube are connected with the first node. The inverter unit 102 is configured to shape the waveform of the first node, and adjust the size of the field effect transistor of the 1 st stage inverter so that the voltage of the first node is kept at a low level until the second node is below the threshold voltage. The inverter unit 102 is used for driving the first switch transistor T11 to be turned on when the voltage of the second node is pulled down to be lower than a predetermined threshold, so as to discharge the charge from the power supply terminal VDD.
In the present embodiment, the inverter 1021 may be a conventional inverter, and the inverter 1021 includes a first P-channel fet P1 and a first N-channel fet N1, wherein a source of the first P-channel fet P1 is connected to the power supply terminal, a source of the first N-channel fet N1 is connected to the ground terminal VSS, a gate of the first P-channel fet P1 is connected to a gate of the first N-channel fet N1 to serve as the input terminal of the inverter 1021, and a drain of the first P-channel fet P1 is connected to a drain of the first N-channel fet N1 to serve as the output terminal of the inverter 1021.
The second switch transistor T12 is a P-channel field effect transistor. The source of the second switch transistor T12 is connected to a predetermined voltage, which in this embodiment needs to be connected to a predetermined high level, for example, it can be connected to the power supply terminal VDD to connect to the predetermined high level. Of course, the source of the second switch tube T12 may also be connected to other high level signals. The drain of the second switch transistor T12 and the input terminal of the nth inverter are connected to point C. The second switch transistor T12 may be a P-type finfet. The second switch tube T12 is used for pulling up the voltage of the point C when the voltage of the first node is at a low level, so as to prolong the on-time of the first switch tube T11, thereby achieving the purpose of improving the charge release amount, achieving more thorough discharge and better protecting effect on the integrated circuit. The size of the second switch transistor T12 is smaller than the sizes of the first N-channel fet and the first P-channel fet of the inverter, so that the pull-up or pull-down action of the first N-channel fet or the first P-channel fet of the inverter on the C point is stronger.
The diode D11 is used to discharge charges to the power supply terminal when the ground terminal voltage VSS rises.
Under the 14nm technology, the electrostatic clamping circuit provided by the embodiment of the application is simulated by cadence, and the original improved power supply voltage clamping circuit and the proposed novel power supply voltage clamping circuit are compared, so that the following results are obtained:
in the above table, the discharge time is 2 us; the remaining power is the power which is not discharged after the esd event is finished; the discharge end voltage is the voltage remained on the power supply end VDD when the first switch tube is closed; the multiple turn-on refers to the stability of the signal from the beginning to the time when the first switch tube is turned off, because the first switch tube is suddenly turned off, if the discharge is not finished, the power supply voltage is increased, and the signal of the second node is triggered again, so that the first switch tube is turned on multiple times.
When the ESD event occurs to cause the voltage of the power supply terminal VDD to suddenly rise during the operation of the electrostatic clamp, the voltage of the second node a is pulled high and then gradually decreased until the voltage is equal to the normal voltage of the power supply terminal. When the voltage of the second node a does not completely decrease to the preset threshold, the first node B is at a low level, the first switch transistor T11 is turned on to discharge the charge from the power supply terminal VDD, the second switch transistor T12 is driven by the voltage of the first node B to turn on, so as to pull up the voltage at the point C, so that the first switch transistor is locked in an on state, and the first node B is at a high level until the N-1 stage inverter pulls down the voltage at the point C to a low level, so as to turn off the first switch transistor T11. When the second node is just pulled down to a preset threshold, the output of the N-1 stage inverter is at a low level, and the point C cannot be directly lowered to the low level due to the pull-up action of the second switch transistor T12, so that a contention phenomenon exists at the second node, and the pull-up or pull-down action of the inverter is stronger because the size of the field effect transistor of the inverter is larger than that of the second switch transistor T12, so that the point C is pulled down to the low level after a period of time X, so that the first node is at the high level, and the first switch transistor T11 is turned off. Therefore, the time that the first node is at the low level is prolonged, so that the time that the first switch tube T11 is in the on state is prolonged, the charge release amount of the power supply terminal VDD is further improved, the discharge is more thorough, and the protection effect on the integrated circuit is better.
It should be understood that, as shown in fig. 3, based on the embodiment shown in fig. 2, the electrostatic clamp circuit further includes a second resistor R2, one end of the second resistor R2 is connected to the first node, and the other end of the second resistor R2 is connected to the source of the second switch transistor T12.
The second resistor R2 can reduce the time consumed by the first node being pulled high after the discharging is completed, i.e. the reset time of the first switch transistor T11 after the discharging is completed, thereby reducing the leakage of the power supply terminal VDD like the ground terminal VSS, and reducing the power consumption.
Referring to fig. 4, fig. 4 is a circuit diagram of an electrostatic clamp according to some embodiments of the present disclosure. The electrostatic clamping circuit comprises: the detection circuit comprises a detection unit 201, a first switch tube T21, an inverter unit 202, a second switch tube T22 and a diode D21.
The detecting unit 201 is connected between a power supply terminal VDD and a ground terminal VSS, a second node of a middle node of the detecting unit 201 is connected to an input terminal of a 1 st-level inverter of the inverter unit 202, an nth of the inverter unit 202 and an output terminal of the inverter are connected to a first node with a gate of the first switch transistor T21, an input terminal of the first switch transistor T21 is connected to the power supply terminal VDD, and an output terminal of the first switch transistor T21 is connected to the ground terminal VSS. The gate of the second switch transistor T22 and the gate of the first switch transistor T21 are connected to a first node, the source of the second switch transistor T22 is connected to a predetermined voltage, the drain of the second switch transistor T22 and the input terminal of the nth stage inverter are connected to a point C, the anode of the diode D21 is connected to the ground VSS, and the cathode of the diode D21 is connected to the power supply terminal VDD.
Specifically, the detecting unit 201 includes a capacitive element 2011 and a resistive element 2012 connected to the second node. One end of the capacitive element 2011 is connected to the ground terminal VSS, the other end of the capacitive element 2011 is connected to one end of the resistive element 2012, and the other end of the resistive element 2012 is connected to the power supply terminal VDD. The detecting unit 201 is used for detecting whether the voltage of the power supply terminal rises or not, and pulling down the voltage of the second node when the voltage of the power supply terminal VDD rises suddenly.
The capacitive element 2011 may include a first capacitor, or the capacitive element 2011 may include a first field effect transistor, a source and a drain of the first field effect transistor are connected as one end of the capacitive element 2011, and a gate of the first field effect transistor is connected as the other end of the capacitive element.
The resistive element 2012 may include one or more first resistors connected in series or in parallel, or the resistive element 2012 may further include a second field effect transistor, a source and a drain of the second field effect transistor are respectively used as two ends of the resistive element 2012, and a gate of the second field effect transistor is connected to a predetermined electrical signal to maintain a constant conduction. The equivalent resistance value of the resistive element can be controlled by controlling the voltage value of the preset electric signal.
The first switch transistor T21 is a P-channel fet, the source of the first switch transistor T21 is connected to the power supply terminal VDD, and the drain of the first switch transistor T21 is connected to the ground terminal VSS. The first switch transistor T21 is used for switching on or off under the control of the first node voltage, and the first switch transistor T21 is used for discharging the charges accumulated at the power supply terminal when being switched on, thereby pulling down the voltage of the power supply terminal VDD. The first switch transistor T21 may be a P-type finfet transistor.
The inverter unit 202 includes N inverters 2021 cascaded in sequence. N is an even number greater than 1. The input end of the 1 st-stage inverter is connected with the second node, and the output end of the Nth-stage inverter and the grid electrode of the first switching tube are connected with the first node. The inverter unit 202 is used to shape the waveform of the first node, and adjust the size of the field effect transistor of the 1 st stage inverter, so that the voltage of the first node can be kept at a low level until the second node is higher than the threshold voltage. The inverter unit 202 is used for driving the first switch transistor T21 to turn on when the voltage of the second node is pulled up to be greater than the predetermined threshold, so as to discharge the charge from the power supply terminal VDD.
In the present embodiment, the inverter 2021 includes a first P-channel fet P1 and a first N-channel fet N1, wherein a source of the first P-channel fet P1 is connected to a power supply terminal, a source of the first N-channel fet N1 is connected to a ground terminal VSS, a gate of the first P-channel fet P1 is connected to a gate of the first N-channel fet N1 to serve as an input terminal of the inverter 2021, and a drain of the first P-channel fet P1 is connected to a drain of the first N-channel fet N1 to serve as an output terminal of the inverter 2021.
The second switch transistor T22 is a P-channel field effect transistor. The source of the second switch transistor T22 is connected to a predetermined voltage, which in this embodiment needs to be connected to a predetermined high level, for example, it can be connected to the power supply terminal VDD to connect to the predetermined high level. Of course, the source of the second switch tube T22 may also be connected to other high level signals. The drain of the second switch transistor T22 and the input terminal of the nth inverter are connected to point C. The second switch transistor T22 may be a P-type finfet. The second switch tube T22 is used for pulling up the voltage of the point C when the voltage of the first node is at a low level, so as to prolong the on-time of the first switch tube T21, thereby achieving the purpose of improving the charge release amount, achieving more thorough discharge and better protecting effect on the integrated circuit. The size of the second switch transistor T22 is smaller than the sizes of the first N-channel fet and the first P-channel fet of the inverter, so that the pull-up or pull-down action of the first N-channel fet or the first P-channel fet of the inverter on the C point is stronger.
The diode D21 is used to discharge charges to the power supply terminal when the ground terminal voltage VSS rises.
When the ESD event occurs to cause the voltage of the power supply terminal VDD to suddenly rise during the operation of the electrostatic clamp, the voltage of the second node is pulled down and then gradually rises until the voltage is equal to the normal voltage of the power supply terminal. When the voltage of the second node does not rise to the preset threshold completely, the first node is at a low level, the first switch transistor T21 is turned on to discharge the charge from the power supply terminal VDD, the second switch transistor T22 is driven by the voltage of the first node to open, so as to pull up the voltage of the point C, so that the first switch transistor is locked in an open state, and the first node does not become at a high level until the N-1 stage inverter pulls down the voltage of the point C to a low level, so that the first switch transistor T21 is turned off. When the second node is just pulled up to a preset threshold, the output of the N-1 stage inverter is at a low level, and the C point cannot be directly lowered to the low level due to the pull-up action of the second switch transistor T22, so that a competitive phenomenon exists at the second node, and the pull-up or pull-down action of the inverter is stronger because the size of the field effect transistor of the inverter is larger than that of the second switch transistor T22, so that the C point is pulled down to the low level after a period of time X, so that the first node is at the high level, and the first switch transistor T21 is turned off. Therefore, the time that the first node is at the high level is prolonged, so that the time that the first switch tube T21 is in the on state is prolonged, the charge release amount of the power supply terminal VDD is further improved, the discharge is more thorough, and the protection effect on the integrated circuit is better.
It should be understood that, as shown in fig. 5, based on the embodiment shown in fig. 4, the electrostatic clamp circuit further includes a second resistor R2, one end of the second resistor R2 is connected to the first node, and the other end of the second resistor R2 is connected to the source of the second switch transistor T22. The second resistor R2 can reduce the time consumed by the first node being pulled high after the discharging is completed, i.e. the reset time of the first switch transistor T21 after the discharging is completed, thereby reducing the leakage of the power supply terminal VDD like the ground terminal VSS, and reducing the power consumption.
Referring to fig. 6, fig. 6 is a circuit structure diagram of an electrostatic clamp circuit according to an embodiment of the present disclosure. The electrostatic clamping circuit comprises: the detection circuit comprises a detection unit 301, a first switch tube T31, an inverter unit 302, a second switch tube T32 and a diode D31.
The detecting unit 301 is connected between a power supply terminal VDD and a ground terminal VSS, a second node of a middle node of the detecting unit 301 is connected to an input terminal of the 1 st-level inverter of the inverter unit 302, an nth of the inverter unit 302 and an output terminal of the inverter are connected to a first node with a gate of the first switch transistor T31, an input terminal of the first switch transistor T31 is connected to the power supply terminal VDD, and an output terminal of the first switch transistor T31 is connected to the ground terminal VSS. The gate of the second switch transistor T32 and the gate of the first switch transistor T31 are connected to a first node, the source of the second switch transistor T32 is connected to a predetermined voltage, the drain of the second switch transistor T32 and the input terminal of the nth stage inverter are connected to a point C, the anode of the diode D31 is connected to the ground VSS, and the cathode of the diode D31 is connected to the power supply terminal VDD.
Specifically, the detection unit 301 includes a capacitive element 3011 and a resistive element 3012 connected to the second node. One end of the capacitive element 3011 is connected to the power supply terminal VDD, the other end of the capacitive element 3011 is connected to one end of the resistive element 3012, and the other end of the resistive element 1012 is connected to the ground terminal VSS. The detecting unit 301 is configured to pull up the voltage of the second node when the voltage of the power supply terminal suddenly rises.
The capacitive element 3011 may include a first capacitor, or the capacitive element 3011 may include a first field effect transistor, a source and a drain of the first field effect transistor are connected as one end of the capacitive element 3011, and a gate of the first field effect transistor is used as the other end of the capacitive element.
The resistive element 3012 may include one or more first resistors connected in series or in parallel, or the resistive element 3012 may further include a second field effect transistor, a source and a drain of the second field effect transistor are respectively used as two ends of the resistive element 3012, and a gate of the second field effect transistor is connected to a predetermined electrical signal to keep being turned on constantly. The equivalent resistance value of the resistive element can be controlled by controlling the voltage value of the preset electric signal.
The first switch transistor T31 is an N-channel fet, the drain of the first switch transistor T31 is connected to the power supply terminal VDD, and the source of the first switch transistor T31 is connected to the ground terminal VSS. The first switch transistor T31 is used for switching on or off under the control of the first node voltage, and the first switch transistor T31 is used for discharging the charges accumulated at the power supply terminal when being switched on, thereby pulling down the voltage of the power supply terminal VDD. The first switch transistor T31 may be an N-type finfet transistor.
The inverter unit 302 includes N inverters 3021 cascaded in sequence. N is an even number greater than 1. The input end of the 1 st-stage inverter is connected with the second node, and the output end of the Nth-stage inverter and the grid electrode of the first switching tube are connected with the first node. The inverter unit 302 is used to shape the waveform of the first node, and adjust the size of the field effect transistor of the 1 st stage inverter, so that the voltage of the first node can be kept high before the second node is pulled down to the threshold voltage. The inverter unit 302 is used to drive the first switch transistor T11 to turn on before the second node is pulled down to the threshold voltage, so as to discharge the charge from the power supply terminal VDD.
In the present embodiment, the inverter 3021 includes a first P-channel fet P1 and a first N-channel fet N1, wherein a source of the first P-channel fet P1 is connected to a power supply terminal, a source of the first N-channel fet N1 is connected to a ground terminal VSS, a gate of the first P-channel fet P1 is connected to a gate of the first N-channel fet N1 as an input terminal of the inverter 3021, and a drain of the first P-channel fet P1 is connected to a drain of the first N-channel fet N1 as an output terminal of the inverter 3021.
The second switch transistor T32 is an N-channel field effect transistor. The source of the second switch transistor T32 is connected to a predetermined voltage, which in this embodiment needs to be connected to a predetermined high level, for example, it can be connected to the power supply terminal VDD to connect to the predetermined high level. Of course, the source of the second switch tube T32 may also be connected to other high level signals. The drain of the second switch transistor T32 and the input terminal of the nth inverter are connected to point C. The second switch transistor T32 may be an N-type finfet. This second switch tube T32 is used for pulling down the voltage of this C point through when this first node voltage is the high level to prolong this first switch tube T31's on-time, and then reach and improve the charge release volume, discharge more thoroughly, it is better to integrated circuit's protection effect. The size of the second switch transistor T32 is smaller than the sizes of the first N-channel fet and the first P-channel fet of the inverter, so that the pull-up or pull-down action of the first N-channel fet or the first P-channel fet of the inverter on the C point is stronger.
The diode D31 is used to discharge charges to the power supply terminal when the ground terminal voltage VSS rises.
When the ESD event occurs to cause the voltage of the power supply terminal VDD to suddenly rise during the operation of the electrostatic clamp, the voltage of the second node is pulled high and then gradually decreased to a steady state until the voltage is equal to the normal voltage of the power supply terminal. When the voltage of the second node does not completely decrease to the preset threshold, the first node is at a high level, the first switch transistor T31 is turned on to discharge the charge from the power supply terminal VDD, the second switch transistor T32 is driven by the voltage of the first node to open, so as to pull down the voltage at the point C, so that the first switch transistor T31 is locked in an open state, and the first node is at a low level until the N-1 stage inverter pulls up the voltage at the point C to a high level, so as to turn off the first switch transistor T31. When the second node is just pulled down to a preset threshold, the output of the N-1 stage inverter is at a high level, and the point C cannot be directly raised to the high level due to the pulling down action of the second switch transistor T32, so that a competitive phenomenon exists at the second node, and the pulling up or pulling down action of the inverter is stronger because the size of the field effect transistor of the inverter is larger than that of the second switch transistor T32, so that the point C is pulled up to the high level after a period of time, so that the first node is at the low level, and the first switch transistor T31 is turned off. Therefore, the time that the first node is at the high level is prolonged, so that the time that the first switch tube T31 is in the on state is prolonged, the charge release amount of the power supply terminal VDD is further improved, the discharge is more thorough, and the protection effect on the integrated circuit is better.
It should be understood that, as shown in fig. 7, based on the embodiment shown in fig. 6, the electrostatic clamp circuit further includes a second resistor R2, one end of the second resistor R2 is connected to the first node, and the other end of the second resistor R2 is connected to the source of the second switch transistor T32. The second resistor R2 can reduce the time consumed by pulling the first node low after the discharging is completed, i.e. the reset time of the first switch transistor T31 is shortened after the discharging is completed, thereby reducing the leakage of the power supply terminal VDD like the ground terminal VSS, and reducing the power consumption.
Referring to fig. 8, fig. 8 is a circuit diagram of an electrostatic clamp according to some embodiments of the present disclosure. The electrostatic clamping circuit comprises: the detection circuit comprises a detection unit 401, a first switch tube T41, an inverter unit 402, a second switch tube T42 and a diode D41.
The detecting unit 401 is connected between a power supply terminal VDD and a ground terminal VSS, a second node of a middle node of the detecting unit 401 is connected to an input terminal of the 1 st-level inverter of the inverter unit 402, an nth of the inverter unit 402 and an output terminal of the inverter are connected to a first node with a gate of the first switch transistor T41, an input terminal of the first switch transistor T41 is connected to the power supply terminal VDD, and an output terminal of the first switch transistor T41 is connected to the ground terminal VSS. The gate of the second switch transistor T42 and the gate of the first switch transistor T41 are connected to a first node, the source of the second switch transistor T42 is connected to a predetermined voltage, the drain of the second switch transistor T42 and the input terminal of the nth stage inverter are connected to a point C, the anode of the diode D41 is connected to the ground VSS, and the cathode of the diode D41 is connected to the power supply terminal VDD.
Specifically, the detection unit 401 includes a capacitive element 4011 connected to the second node and a resistive element 4012. One end of the capacitive element 4011 is connected to the ground terminal VSS, the other end of the capacitive element 4011 is connected to one end of the resistive element 4012, and the other end of the resistive element 4012 is connected to the supply terminal VDD. The detecting unit 401 is configured to pull down the voltage of the second node when the voltage of the power supply terminal VDD suddenly rises.
The capacitive element 4011 may include a first capacitor, or the capacitive element 4011 may include a first field effect transistor, a source and a drain of the first field effect transistor are connected as one end of the capacitive element 4011, and a gate of the first field effect transistor is connected as the other end of the capacitive element.
The resistive element 4012 may include one or more first resistors connected in series or in parallel, or the resistive element 4012 may further include a second field effect transistor, a source and a drain of the second field effect transistor are respectively used as two ends of the resistive element 4012, and a gate of the second field effect transistor is connected to a predetermined electrical signal to maintain a constant conduction. The equivalent resistance value of the resistive element can be controlled by controlling the voltage value of the preset electric signal.
The first switch transistor T41 is an N-channel fet, the source of the first switch transistor T41 is connected to the ground terminal VSS, and the drain of the first switch transistor T41 is connected to the power supply terminal VDD. The first switch transistor T41 is used for switching on or off under the control of the first node voltage, and the first switch transistor T41 is used for discharging the charges accumulated at the power supply terminal when being switched on, thereby pulling down the voltage of the power supply terminal VDD. The first switch transistor T41 may be an N-type finfet transistor.
The inverter unit 402 includes N inverters 4021 cascaded in sequence. N is an odd number greater than 2. The input end of the 1 st-stage inverter is connected with the second node, and the output end of the Nth-stage inverter and the grid electrode of the first switching tube are connected with the first node. The inverter unit 402 is used to shape the waveform of the first node, and adjust the size of the field effect transistor of the 1 st stage inverter, so that the voltage of the first node can be kept at a low level until the second node is higher than the threshold voltage. The inverter unit 402 is used for driving the first switch transistor T41 to turn on when the voltage of the second node is pulled up to be greater than the predetermined threshold, so as to discharge the charge from the power supply terminal VDD.
In this embodiment, the inverter 4021 includes a first P-channel fet P1 and a first N-channel fet N1, wherein a source of the first P-channel fet P1 is connected to a power supply terminal, a source of the first N-channel fet N1 is connected to a ground terminal VSS, a gate of the first P-channel fet P1 is connected to a gate of the first N-channel fet N1 as an input terminal of the inverter 4021, and a drain of the first P-channel fet P1 is connected to a drain of the first N-channel fet N1 as an output terminal of the inverter 4021.
The second switch transistor T42 is an N-channel field effect transistor. The source of the second switch transistor T42 is connected to a predetermined voltage, which in this embodiment is connected to a predetermined high level, for example, it can be connected to the ground terminal VSS to connect to the predetermined low level. Of course, the source of the second switch tube T42 may also be connected to other low level signals. The drain of the second switch transistor T42 and the input terminal of the nth inverter are connected to point C. The second switch transistor T42 may be an N-type finfet. This second switch tube T42 is used for pulling down the voltage of this C point through when this first node voltage is the high level to prolong this first switch tube T41's on-time, and then reach and improve the charge release volume, discharge more thoroughly, it is better to integrated circuit's protection effect. The size of the second switch transistor T42 is smaller than the sizes of the first N-channel fet and the first P-channel fet of the inverter, so that the pull-up or pull-down action of the first N-channel fet or the first P-channel fet of the inverter on the C point is stronger.
The diode D41 is used to discharge charges to the power supply terminal when the ground terminal voltage VSS rises.
When the ESD event occurs to cause the voltage of the power supply terminal VDD to suddenly rise during the operation of the electrostatic clamp, the voltage of the second node is pulled down and then gradually rises until the voltage is equal to the normal voltage of the power supply terminal. When the voltage of the second node does not rise to the preset threshold completely, the first node is at a high level, the first switch transistor T41 is turned on to discharge the charge from the power supply terminal VDD, the second switch transistor T42 is driven by the voltage of the first node to open, so as to pull down the voltage at the point C, so that the first switch transistor is locked in an open state, and the first node does not become a low level until the N-1 stage inverter pulls up the voltage at the point C to a high level, so that the first switch transistor T41 is turned off. When the second node is just pulled up to a preset threshold, the output of the N-1 stage inverter is at a high level, and the point C cannot be directly raised to the high level due to the pull-down action of the second switch transistor T42, so that a contention phenomenon exists at the second node, and the pull-up or pull-down action of the inverter is stronger because the size of the field effect transistor of the inverter is larger than that of the second switch transistor T42, so that the point C is pulled up to the high level after a period of time X, so that the first node is at the low level, and the first switch transistor T41 is turned off. Therefore, the time that the first node is at the low level is prolonged, so that the time that the first switch tube T41 is in the on state is prolonged, the charge release amount of the power supply terminal VDD is further improved, the discharge is more thorough, and the protection effect on the integrated circuit is better.
It is to be understood that, as shown in fig. 9, based on the embodiment shown in fig. 8, the electrostatic clamp circuit may further include a second resistor R2, one end of the second resistor R2 is connected to the first node, and the other end of the second resistor R2 is connected to the source of the second switch transistor T42. The second resistor R2 can reduce the time consumed by pulling the first node low after the discharging is completed, i.e. the reset time of the first switch transistor T41 is shortened after the discharging is completed, thereby reducing the leakage of the power supply terminal VDD like the ground terminal VSS, and reducing the power consumption.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (16)
1. An electrostatic clamp, comprising:
a detection unit connected to the power supply terminal for detecting whether a voltage of the power supply terminal rises;
the input end of the first switch tube is connected with the power supply end, and the output end of the first switch tube is connected with the grounding end;
the phase inverter unit comprises N phase inverters which are sequentially cascaded, the input end of the 1 st level phase inverter of the phase inverter unit is connected with the output end of the detection unit, and the output end of the N nth level phase inverter of the phase inverter unit is connected with the grid electrode of the first switch tube; the phase inverter unit is used for controlling the first switching tube to be conducted when the voltage of the power supply end rises;
and the source electrode of the second switching tube is connected with a preset voltage, the drain electrode of the second switching tube is connected with the input end of the Nth-stage phase inverter of the phase inverter unit, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the second switching tube is used for prolonging the conduction time of the first switching tube.
2. The electrostatic clamp of claim 1, further comprising:
and the cathode of the diode is connected with the power supply end, and the anode of the diode is connected with the grounding end.
3. The electrostatic clamp of claim 1, further comprising:
one end of the second resistor is connected with the source electrode of the second switch tube, and the other end of the second resistor is connected with the grid electrode of the second switch tube.
4. The electrostatic clamp circuit according to any one of claims 1 to 3, wherein the detection unit includes a resistive element and a capacitive element, one end of the capacitive element is connected to a power supply terminal, the other end of the capacitive element is connected to one end of the resistive element as an output terminal of the detection unit, and the other end of the resistive element is connected to a ground terminal.
5. The electrostatic clamp of claim 4, wherein N is an odd number greater than 2, the first switch transistor and the second switch transistor are P-channel field effect transistors, and the predetermined voltage applied to the source of the second switch transistor is a first high level.
6. The electrostatic clamp of claim 5, wherein the source of the second switching tube is connected to a supply terminal.
7. The electrostatic clamp of claim 4, wherein N is an even number greater than 1, the first switch transistor and the second switch transistor are P-channel field effect transistors, and the predetermined voltage applied to the source of the second switch transistor is a first low level.
8. The electrostatic clamp of claim 7, wherein a source of the second switch tube is connected to ground.
9. The electrostatic clamp circuit according to any one of claims 1 to 3, wherein the detection unit includes a resistive element and a capacitive element, one end of the capacitive element is connected to a ground terminal, the other end of the capacitive element and one end of the resistive element are connected to an output terminal of the detection unit, and the other end of the resistive element is connected to a power supply terminal.
10. The electrostatic clamp of claim 9, wherein N is an odd number greater than 2, the first and second switching transistors are N-channel field effect transistors, and the predetermined voltage applied to the source of the second switching transistor is a first low level.
11. The electrostatic clamp of claim 10, wherein a source of the second switch tube is connected to the ground terminal.
12. The electrostatic clamp of claim 9, wherein N is an even number greater than 1, the first and second switching transistors are P-channel field effect transistors, and the predetermined voltage applied to the source of the second switching transistor is a first high level.
13. The electrostatic clamp of any of claims 1-3, wherein the capacitive element comprises a first field effect transistor, a source and a drain of the first field effect transistor being connected as one terminal of the capacitive element, a gate of the first field effect transistor being the other terminal of the capacitive element.
14. The electrostatic clamp of any of claims 1-3, wherein the resistive element comprises a second field effect transistor, a source and a drain of the second field effect transistor respectively serve as two terminals of the resistive element, and a gate of the second field effect transistor is connected to a predetermined voltage so that the second field effect transistor remains normally on.
15. The electrostatic clamp of claim 1, wherein the first switch and/or the second switch is a fin field effect transistor.
16. A chip structure, comprising:
a chip having a ground pin and a power supply pin;
a power clamp having a supply terminal connected to the supply pin and a ground terminal connected to the ground pin, the power clamp being as claimed in any one of claims 1 to 15.
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| CN202010932032.0A CN112103932A (en) | 2020-09-07 | 2020-09-07 | Electrostatic clamping circuit and chip structure |
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