CN112101517A - FPGA implementation method based on piecewise linear pulse neuron network - Google Patents
FPGA implementation method based on piecewise linear pulse neuron network Download PDFInfo
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Abstract
The embodiment of the invention discloses an FPGA (field programmable gate array) implementation method based on a piecewise linear pulse neuron network, which comprises the following steps of: constructing a neuron circuit according to a two-dimensional piecewise linear pulse neuron model so as to integrate and output input information through the neuron circuit, wherein the two-dimensional piecewise linear pulse neuron model comprises an expression of membrane potential of a neuron and an expression of a recovery variable; and the communication circuit is used for expanding and configuring the pulse coding and decoding unit according to the neuron circuit and a random coupling structure to generate a pulse neural network. The invention occupies lower hardware resources, can simulate and present rich neural morphology dynamics, can work with higher hardware computing efficiency, and is convenient for expanding to the hardware architecture realization of a large-scale pulse neural network and the dynamic simulation of a communication system.
Description
Technical Field
The embodiment of the invention relates to the technical field of neural networks, in particular to an FPGA (field programmable gate array) implementation method based on a piecewise linear pulse neural network.
Background
In order to simulate the mechanism of biological information coding and explore the dynamic process of biological information processing, and further simulate the real brain information processing process, researchers have proposed an Artificial Neural Network (ANN). Artificial neural networks are mathematical models inspired by biological neuronal organization and function, can automatically approximate any functional form that best characterizes data, and are widely used to solve many prediction and decision modeling problems. Spiking Neural Network (SNN), which is a third-generation artificial Neural Network, is currently receiving wide attention from researchers due to its unique information processing mechanism and high-performance computational efficiency similar to those of the human brain.
The essence of the pulse neural network is to simulate the information processing mode and dynamic process of real biological neurons by acquiring the clue characteristics of living biological tissues, realize biological authenticity and establish a quantitative analysis model. From this point of view, it is more focused on the in-depth study of the neurodynamic properties, rather than on analyzing the macroscopic variables of the neural network. Therefore, compared with the traditional artificial neural network based on pulse frequency coding information, the pulse neural network has stronger computing power, is very suitable for realizing the processing problem of a complex space-time mode, and has good and efficient application and inspection in the fields of information processing, biomedicine, social economy and the like.
At present, the implementation methods of the impulse neural network can be classified into two methods, namely software implementation and hardware implementation. The software implementation mainly comprises the steps of compiling a code running program and simulating software to carry out simulation test, and has the problems that the execution speed is low, the real-time operation on a large-scale pulse neural network cannot be carried out, and the expandability of the system is poor. Therefore, more researchers are dedicated to the hardware implementation method research of the impulse neural network, and the core goal is to output hardware technical results with low power consumption, low clock frequency and high performance. Due to the complexity of the information processing of the spiking neural network model, a completely new hardware architecture needs to be researched for the hardware implementation of the spiking neural network.
At present, the implementation method and design principle of the neuromorphic hardware system can be divided into three implementation methods, namely an Analog circuit (Analog circuit), a Digital system (Digital Systems) and a Mixed Analog/Digital implementation (Mixed Analog/Digital), from the high level of the hardware system. The digital system implementation devices are mainly classified into two categories, which are FPGA, fully-customized or Application-Specific Integrated Circuit (ASIC) chips. The main technology for realizing the pulse neuron/network FPGA hardware architecture is to carry out hardware reconstruction on the pulse neuron/network FPGA hardware architecture based on theoretical research results of the pulse neural network and simulate the processes of issuing, transmitting and processing pulses in the pulse neural network in real time. The FPGA technology is applied to design and realize an artificial neural network, so that the structure and the function of a biological nervous system are simulated, and the method mainly comprises two aspects: (1) constructing a neuron circuit which is responsible for completing calculation tasks such as integration and output of input information; (2) and a connection and communication circuit is constructed and is responsible for communication interconnection of the computing units, information interaction of data resources is realized, and a specific network topology structure is formed.
In the hardware implementation of the existing impulse neural network, on one hand, only the timeliness of the whole network architecture is considered and the one-dimensional neuron model is directly used, and on the other hand, when the multi-dimensional neuron model is used for observing the neuromorphic dynamic characteristic, only the function curve of a linear approximate differential equation is simply segmented, so that certain neuromorphic dynamic characteristic is lost while the hardware implementation of the impulse neuron model is realized.
Disclosure of Invention
The embodiment of the invention aims to provide an FPGA (field programmable gate array) implementation method based on a piecewise linear pulse neuron network, which is used for solving the problem that certain neuromorphic dynamic characteristics are lost when the existing pulse neuron model is implemented by hardware.
In order to achieve the above object, the embodiments of the present invention mainly provide the following technical solutions:
the embodiment of the invention provides an FPGA (field programmable gate array) implementation method based on a piecewise linear pulse neuron network, which comprises the following steps of: constructing a neuron circuit according to a two-dimensional piecewise linear pulse neuron model so as to integrate and output input information through the neuron circuit, wherein the two-dimensional piecewise linear pulse neuron model comprises an expression of membrane potential of a neuron and an expression of a recovery variable; and the communication circuit is used for expanding and configuring the pulse coding and decoding unit according to the neuron circuit and a random coupling structure to generate a pulse neural network.
According to an embodiment of the invention, constructing the neuron circuit according to the two-dimensional piecewise linear impulse neuron model comprises: providing the two-dimensional piecewise linear impulse neuron model; carrying out digital operation processing, equation transformation and discretization on the two-dimensional piecewise linear pulse neuron model to obtain a discretized piecewise linear pulse neuron model; and constructing the neuron circuit comprising a multiplexer, a transmission channel, a register and a digital summator according to the discrete piecewise linear pulse neuron model.
According to an embodiment of the present invention, a communication circuit for expanding and configuring a pulse encoding and decoding unit to generate a pulse neural network according to the neuron circuit in a random coupling structure includes: randomly generating a pulse neural network comprising A neurons and B synaptic connections by adopting a random function, wherein the A neurons are randomly coupled, and A and B are integers larger than zero; constructing a communication circuit comprising a first circuit unit, a second circuit unit and a third circuit unit according to the impulse neural network; the first circuit unit comprises a weight value storage unit and an input calculation unit, and is used for controlling the enhancement or the weakening of synaptic electrical signals between the neuron node connections; the second circuit unit is used for constructing different impulse neural network topological structures on the basis of the two-dimensional piecewise linear impulse neuron model to generate multi-core storage connection vectors, and aiming at impulse neural network simulation in a hardware architecture; the third circuit unit comprises a control unit, a counting buffer and an output unit, and is used for responding different response requirements, sending a control signal to the weight storage unit, calling the weight to participate in network calculation, judging whether the neuron membrane potential reaches a pulse peak value, and calling a corresponding reset mechanism to reset.
According to an embodiment of the present invention, the weight storage unit includes a plurality of buffers, each buffer includes a plurality of weights, and the plurality of buffers are connected to each other.
According to an embodiment of the present invention, the input calculating unit is configured to input the neuron according to the input weight provided by the weight storing unit, and calculate the input current of the neuron.
According to one embodiment of the invention, the second circuit unit is shared between a part of the neurons through a pipeline and a buffer.
The technical scheme provided by the embodiment of the invention at least has the following advantages:
the FPGA implementation method based on the Piecewise Linear pulse neuron network provided by the embodiment of the invention is characterized in that the circuit design and implementation of the Piecewise Linear pulse neuron are realized, and the used Piecewise Linear Pulse (PLS) neuron model combines the dynamic characteristic of a Hodgkin-Huxley neuron model and the analytic characteristic of an integral-and-Fire neuron model, so that the logic mapping of hardware is facilitated while the abundant neural calculation characteristic and the neural dynamics characteristic are kept, and the operation flow for realizing the digital design is accelerated. The neuron model approximates the zero line of the neuron membrane potential by using a V-shaped curve formed by two straight lines, represents the zero line of a membrane potential recovery variable by using one straight line, and is added with a reset mechanism (judging whether the membrane potential at the time t reaches a pulse peak value V or not)peak) Corresponding to the repolarization process of the neuron. The model of the piecewise linear pulse neuron is designed into a form convenient for circuit coding, programming and simulation are carried out through a Verilog HDL language, and joint simulation is carried out by Quartus II and ModelSim software.
The core technical scheme of the construction of the communication system of the impulse neural network is that the whole hardware architecture of the impulse neural network communication system is constructed on the basis of the circuit design and the synapse interaction mechanism of the two-dimensional piecewise linear impulse neuron model. Starting from the requirements of the stage and the test of the digital system design, on the basis of the existing neuron digital circuit, the neuron digital circuit is expanded according to a random coupling structure, and a corresponding pulse coding and decoding unit is configured and used for completing the response of the digital circuit by acting a pulse memory on the neuron.
In the aspect of neuron circuit design and implementation, the piecewise linear pulse neuron model reduces the use of multipliers, occupies lower hardware resources, can simulate and present rich neural morphology dynamics, can work with higher hardware computing efficiency, and is convenient for expanding to the hardware architecture implementation of a large-scale pulse neural network and the dynamic simulation of a communication system.
Drawings
Fig. 1 is a flowchart of an FPGA implementation method based on a piecewise linear impulse neuron network according to an embodiment of the present invention.
FIG. 2 is a diagram of a parallel operation unit of a neuron model according to an example of the present invention.
FIG. 3 is a pipeline of digital computation of membrane potential V in a two-dimensional piecewise linear pulse neuron mathematical model digital implementation circuit according to an example of the present invention.
FIG. 4 is a digital computation pipeline for recovering a variable U in a digital implementation circuit implementing a two-dimensional piecewise linear pulse neuron mathematical model in accordance with an example of the present invention.
FIG. 5 is a flow chart of a membrane potential V circuit implementation of a neuron model according to an embodiment of the present invention.
FIG. 6 is a block diagram of a spiking neural network with random coupling of synaptic connections in accordance with an example of the present invention.
FIG. 7 is a diagram of synaptic connections between neurons of a spiking neural network with random coupling of synaptic connections in an example of the present invention.
FIG. 8 is an FPGA implementation architecture of a pulse neural network in accordance with an example of the present invention.
Fig. 9 is a detailed digital design structure of a weight storage unit in a W unit digital implementation architecture implemented by an FPGA of a pulse neural network according to an example of the present invention.
Fig. 10 is a detailed digital design structure of an input computing unit in a W unit digital implementation architecture of an FPGA implementation of a pulse neural network according to an example of the present invention.
Fig. 11 is a design structure of a neuron parallel operation array in an N-unit digital implementation architecture of an FPGA implementation of a pulse neural network according to an example of the present invention.
Fig. 12 is a signal design structure of a control unit in a digital implementation architecture of a C unit implemented by an FPGA of a pulse neural network according to an example of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In the description of the present invention, it is to be understood that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as meaning directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Fig. 1 is a flowchart of an FPGA implementation method based on a piecewise linear impulse neuron network according to an embodiment of the present invention. As shown in fig. 1, the FPGA implementation method based on the piecewise linear impulse neural network according to the embodiment of the present invention includes:
s1: and constructing a neuron circuit according to a two-dimensional piecewise linear pulse neuron model so as to integrate and output input information through the neuron circuit, wherein the two-dimensional piecewise linear pulse neuron model comprises an expression of membrane potential of a neuron and an expression of a recovery variable.
In one embodiment of the present invention, step S1 includes:
s1-1: a two-dimensional piecewise linear impulse neuron model is provided.
Specifically, the piecewise linear impulse neuron model formula is described as:
wherein V represents the membrane potential of a neuron; u represents a recovery variable, essentially K activated in the physiological model+Current or deactivated Na+Current, to realize negative feedback to membrane potential; tau ism>0 represents the membrane time constant, VrestIs a resting potential, and both parameters are used to describe the leakage term of the neuron; tau isr>0 denotes a recovery time constant, VthreshRepresents the pulse threshold potential, k represents the coupling of U and V; gsRepresents the pulse conductance when V is more than or equal to VthreshWhen at gsBy opening an initial discharge pulse whose basic unit is the drain conductance gL. Let r be equal to the calculation step in equation (V-V)thresh) So the calculation step size can be converted to r + ═ V (V-V)thresh) When r is>And when 0, r + ═ r, otherwise, r + ═ 0. The sum of the DC currents injected through the synaptic current or neuron connection node is denoted by I. When the membrane potential of the neuron is greater than or equal to the pulse peak value (V is greater than or equal to V)peak) Given the application of the following reset conditions:
wherein, VresetIs the membrane potential to reach VpeakA later reset value; u shaperesetIs the difference (K) between the ion current before and after the pulse+Current and Na+Current flow).
S1-2: and carrying out digital operation processing, equation transformation and discretization on the two-dimensional piecewise linear pulse neuron model to obtain the discretized piecewise linear pulse neuron model.
Performing digital operation on the two-dimensional differential equation system by using the value of tau in the formula (1)mAnd τrThe division to the right of the equation is followed by the operation of the equation. After conversion, in order to implement the neuron model digitally on the FPGA platform, an euler method is used to discretize an equation of a two-dimensional piecewise linear pulse neuron model represented by continuous time, and the discretized neuron model is represented as:
through the mathematical transformation of the segmented linear pulse neuron model, a linear calculation expression (namely, an expression 3) is obtained when V is satisfied<VpeakIn time (limiting conditions), the membrane potential output by the neuron can circularly participate in the operation of an equation to generate a regular continuous pulse sequence, so that the dynamic analysis of an experimental result and the comparison of the biological physiological activity characteristics are facilitated. Meanwhile, the equation set only comprises basic four arithmetic operations, so that the logical mapping of a hardware circuit is facilitated, and the arithmetic pipeline operation of the membrane potential V (t +1) and the recovery variable U (t +1) can be intuitively realized by using a digital design form in a hardware implementation method of the impulse neural network.
S1-3: and constructing a neuron circuit comprising a multiplexer, a transmission channel, a register and a digital summator according to the discrete piecewise linear pulse neuron model.
The piecewise linear pulse neuron model uses four sub-blocks to complete the digital implementation of the circuit design, namely, the four sub-blocks are composed of a V _ Transmission channel, a U _ Transmission channel, a V _ buffer and a U _ buffer.
FIG. 2 is a diagram of a parallel operation unit of a neuron model according to an example of the present invention. As shown in FIG. 2, the V _ Transmit channel Unit contains the computational structure of the V' equation, which is implemented as a V _ S pipeline operation; the U _ transmission channel unit includes a computational structure of U' equations, which is implemented as a U _ S pipeline operation. Further, the V _ buffer and the U _ buffer are memory buffers for V and U values, respectively having a capacity size of V _ buffer _ size and U _ buffer _ size, and each buffer moves one memory cell per clock pulse.
V and U are each Vb、ubNumber of sites, where vbAnd ubAnd determining according to the value ranges of V and U and the required precision. VO is the output membrane potential of the neuron, which is sent to the control unit to be compared with a threshold condition. The "fire pulse" is a one-bit signal from the control unit that resets the position 1 when VO reaches a specified threshold, otherwise. A threshold condition (a secondary equation in the neuron model) is applied to the output values of the V _ transmit channel and the U _ transmit channel, and the result is connected to the inputs of the V _ buffer and the U _ buffer to store the new values. To create a recursive relationship, the outputs of the V _ buffer and the U _ buffer are connected to the V _ Transmission channel and U _ Transmission channel units, respectively.
FIG. 3 is a pipeline of digital computation of membrane potential V in a two-dimensional piecewise linear pulse neuron mathematical model digital implementation circuit according to an example of the present invention. FIG. 4 is a digital computation pipeline for recovering a variable U in a digital implementation circuit implementing a two-dimensional piecewise linear pulse neuron mathematical model in accordance with an example of the present invention. As shown in fig. 3 and 4, in the mathematical model of the two-dimensional piecewise linear impulse neuron, the arithmetic operation in the formula (3) is allocated to the arithmetic functional unit and arranged according to the standard algebraic sequence of the operation, so as to complete the digital design of the arithmetic pipeline by the membrane potential V and the recovery variable U, and for the digital implementation of all neurons, data directly passes through the computation tree from the input stream to the output.
The piecewise linear pulse neuron model circuit realizes joint simulation by Quartus II and ModelSim software, and when a piecewise linear pulse neuron first-order differential equation set is realized, main elements and corresponding functions used in the digital circuit are respectively as follows: using a multiplexer for multiple signal reception and for synthesizing a single signal output; performing an addition/subtraction operation using a digital summer; and the register is used for storing data in real time. Firstly, the calculation process of the membrane potential V (t +1) in the formula (3) is converted into the following functional expression form, so as to facilitate the coding design of the circuit:
FIG. 5 is a flow chart of a membrane potential V circuit implementation of a neuron model according to an embodiment of the present invention. As shown in fig. 5, the construction circuit executes euler approximation equations, a multiplexer is needed to implement each equation, all variable values in the calculation pipeline are updated in time steps, and the formed data is stored in a register and finally output. If the parameter assignment and adjustment in the equation are converted to 2nParticipate in numerical operations and can be replaced by right shifting the corresponding number of bits. The time step t is dynamically updated to t +1 during circuit operation; the derivative dt is designated as 2nParticipating in equation operation, since the value has been determined to be 1/16, it can be replaced by right shift by 4 bits; the design and space and time complexity of the digital operation in the equation are encapsulated together F [ t, V (t)]Is carried out. A unit is constructed in a top-level module realized by a neuron Verilog HDL code through coding, and the specific functions realized by the unit are as follows:
(1) when V (t +1) is not less than VpeakThe parameter tables and state variables can be reset by different bioelectrical properties;
(2) the count variable is a clock prescaler which can reduce the calculation speed by 4096 times;
(3) according to the requirement of a digital operation system, the initial values V (t) and U (t) are reduced by 100 times, so that the dynamic range is [ -1,1 ];
(4) to Vrest、Vthresh、Vpeak、VresetAnd UresetThe parameters are not scaled because they are both set to a constant and are both multiplied by a scaled variable, and variable gs、τmAnd k, τrThen divided by 100. Compared with the formula 3-4, the calculation units in the coding implementation equation are divided by 100 except for the current I and the differential dt, so that the overall operation scaling is realized.
In one embodiment of the invention, the simulation and emulation process selects a fixed-point complement algorithm of 18-bit register and 2 to perform parameter scaling, wherein binary point representation is used between 15 th and 16 th bits (zero bit is the least significant bit), 17 th bit is the sign bit, and the conversion from 18 th bit to 16 th bit only needs to truncate the two least significant bits [1:0], and the represented value ranges from-2.0 to + 1.999985. Meanwhile, the numerical range is also suitable for an audio and video codec, and the latter can only output to a DAC (digital-to-analog converter) by a 16-bit 2 complement code.
S2: and the communication circuit is used for expanding and configuring the pulse coding and decoding unit according to the neuron circuit and a random coupling structure to generate a pulse neural network.
Specifically, the second step completes the construction of the communication system of the impulse neural network, the core work of which is to construct the whole hardware architecture of the impulse neural network communication system based on the circuit design and the synapse interaction mechanism of the two-dimensional piecewise linear impulse neuron model, and the following operations are specifically executed from the stage of digital system design and the requirement of testing: and on the basis of the neuron digital circuit realized in the step one, expanding according to a random coupling structure, and configuring a corresponding pulse coding and decoding unit for a pulse memory to act on the neuron to complete the response of the digital circuit, so as to realize the spatial node connection of a random coupling pulse neural network.
In one embodiment of the present invention, step S2 includes:
s2-1: and randomly generating a pulse neural network comprising A neurons and B synaptic connections by adopting a random function, wherein the A neurons are randomly coupled, and A and B are integers larger than zero.
Illustratively, a pulsed neural network of 1000 neurons and 5000 synaptic connections is randomly generated using a rand function, with random coupling between neurons, and an example of spatial structure connections is shown in fig. 6. Synaptic connections are made between neurons and neurons using synaptic interaction mechanisms including excitatory and inhibitory synapses, as shown in FIG. 7.
S2-2: a communication circuit including a first circuit unit, a second circuit unit, and a third circuit unit is constructed from a spiking neural network.
In combination with the complete process of processing the pulse information by the impulse neural network, the method of the present invention provides an FPGA implementation architecture of the impulse neural network as shown in fig. 8, which can be divided into a first circuit unit W, a second circuit unit N, and a third circuit unit C. Each unit realizes specific operation and processing flow, and specifically comprises the following steps:
the first circuit unit W comprises a weight value storage unit and an input calculation unit, and is used for controlling the enhancement or the weakening of synaptic electrical signals between the neuron node connections.
The detailed digital design structure of the weight storage unit is shown in FIG. 9, and the part is synapse weight WsThe storage unit of (1) is composed of M storage buffers, each buffer comprises N weights, and the number of wb fixed points (which can be determined according to the weight range required by a special application) is used for representing the number of the input neural network participating in numerical operation. A single neuron may store N values in a buffer, with Ws in the buffer being shifted to the memory cells each clock cycle. W _ change represents weight value change, and the control unit provides an instruction signal to call the weight value; i1, i2... iM is a weighted input of wb bits, which is further fed to an input calculation unit.
The detailed digital design structure of the input calculation unit is shown in fig. 10. The module is responsible for calculating the input current I _ in of the neuron through the input weights I1, i2... iM of the weight storage unit and the input neuron of M bits. In the first stage of the unit, the input weights are multiplied by the pulses generated by the last neuron (C1, C2, …, CM). If Ci is 1, the corresponding input weight value is unchanged, and the stage is executed; if Ci is 0, the input weight is converted to the complement of 2 as output at this stage. In subsequent stages, the input values for each section will be calculated in a pipelined structure, and the result will then be added to I _ bias to provide the current of the output neuron, I _ in, as the input for the next neuron. i _ bias is the minimum current that the neuron is guaranteed to emit, and the input current determines the rate of the pulse. Finally, a delay phase is determined according to the number of neurons implemented. Therefore, the whole structure of the unit mainly consists of an I _ S stage pipeline for calculating I _ in and a D _ S stage delay for synchronization.
The second circuit unit N is established on the basis of the neuron model, different impulse neural network topological structures are established to generate multi-core storage connection vectors, and the multi-core storage connection vectors are used for the impulse neural network simulation in a hardware architecture. The second circuit unit N solves the ordinary differential equation of the neuron model by means of a recursion method, utilizes the recursion structure of each part of the neuron, and packages and packs the neuron for resource calling and operation pipeline sharing. Within each clock pulse, a neuron receives an input value and calculates the input current of the neuron, then runs the neuron model once, and uses an excitatory or inhibitory synapse calculation equation between the neuron and the neuron, as shown in fig. 11. In the present structure, the computational unit is shared among a portion of the neurons through a pipeline and a buffer. For the pipeline chain to function properly, it must be ensured that W, V and the U values in the W and N unit outputs are synchronized so that they belong to the same neuron in each clock pulse. The conditions required for this synchronization are:
in a hardware circuit implementation, the necessary conditions for weight update are: the response output of the transmission channels of the weight value and V must be in the same clock pulse, and the formula is as follows:
I_S+D_S+V_S＝N (6)
considering that the number of neurons responding is determined by both fixed point arithmetic and the number of computation stages of V, I, an appropriate delay (D _ S) can be selected to satisfy the equation. In this structure, the number of neurons that have been implemented is (D _ S ═ 0):
I_S+V_S＝N (7)
the third circuit unit C sends control signals to the weight storage unit in response to different response requirements, calls the weight to participate in network calculation, judges whether the neuron membrane potential reaches a pulse peak value or not, and calls a corresponding reset mechanism to reset. The third circuit unit C is composed of three parts, which are a control unit, a count buffer and an output unit.The main function of the unit is to complete the calling of synaptic weights, and when V is more than or equal to V in the piecewise linear neuron modelpeakAnd (3) applying a reset mechanism to complete the reset of the membrane potential V and the recovery variable U. As shown in fig. 12, the operation mechanism of the control unit is described in detail, and the purpose of this section is to acquire necessary data information and apply control signals to other units. Since this unit needs to acquire necessary data and apply control signals to other units, all the input data are:
(1) v (vo) is output from the N unit for threshold condition checking.
(2) The count value is output from the count buffer to evaluate the weight variation.
(3) The user defines N bits of external injection current I for firing the neuron.
(4) "valid" is an input signal from a user, and indicates a stress pulse signal input by an upper neuron and "neuron number selection".
(5) The user provides K bits of "neuron bit number select" for placing the V value of the desired neuron in the output register.
The third circuit unit C contains an internal encoder and logic shift register for generating appropriate commands to the output unit to represent the output of the selected neuron. Encoder provision 2kThe number of bits is used to select k-bit neuron signals, where only one bit is "1" and the others are "0". When the value selected by the neuron digit is valid, the user sets the 'valid' input bit, and the digit code is stored in 2kbit shift register. When the user resets the "valid" bit, 2 is includedkA shift register of 1 bit "0" and one bit "1", to be logically shifted at each clock pulse. Therefore, when the update _ out _ reg signal is "1", there is only one clock pulse; in the state where the signal is "0", there are N-1 clock pulses. This signal is used to write the enable signal into the output register. Because the control unit mainly applies instructions to the W unit, the N unit and the output unit, all output control signals are as follows:
(1) a V reset command and a U update command output to the N cells.
(2) And the command output unit outputs the real-time pulse.
(3) weight _ change: the weight value is updated and stored in a weight value storage unit, and the value is calculated according to excitatory and inhibitory synapse equations in an applied synapse interaction mechanism.
The count buffer of the third circuit unit C is a storage buffer for storing the timing pulse sequence in each neuron according to the number of clock pulses; the output unit is a register that provides the neuron membrane potential V (t +1) at the output terminal.
According to the digital design of the FPGA implementation framework of the impulse neural network, a communication system of the impulse neural network is constructed, electrical synapses are connected among neurons, and a synapse interaction mechanism is mainly realized in network communication by excitatory synapses and inhibitory synapses. In the numerical operation of excitatory and inhibitory synapses in a digital circuit, the invention adopts a numerical integrator for solving an iterative equation, and a mathematical formula for synaptic current I (t +1) is expressed as formula 4 and defined as:
in the formula, λ>0 represents a synaptic time constant, and the value of the synaptic time constant is constant 1/16 in the experiment, so that a reasonable operation result can be obtained; n is the number of inputs into neuron j, wijThe synapse weight from the neuron i to the neuron j takes positive and negative values, so that the synapse current is enhanced or inhibited; ciIs a pulse sequence generated by neuron i.
The FPGA implementation method based on the piecewise linear pulse neuron network provided by the embodiment of the invention is used for designing and implementing the circuit of the piecewise linear pulse neuron, the used piecewise linear pulse neuron model combines the dynamic characteristic of a Hodgkin-Huxley neuron model and the analytic characteristic of an integral-and-Fire neuron model, the logical mapping of hardware is facilitated while the abundant neural computation characteristic and the neural dynamic characteristic are kept, and the implementation of digital design is acceleratedAnd (5) operating the process. The neuron model approximates the zero line of the neuron membrane potential by using a V-shaped curve formed by two straight lines, represents the zero line of a membrane potential recovery variable by using one straight line, and is added with a reset mechanism (judging whether the membrane potential at the time t reaches a pulse peak value V or not)peak) Corresponding to the repolarization process of the neuron. The model of the piecewise linear pulse neuron is designed into a form convenient for circuit coding, programming and simulation are carried out through a Verilog HDL language, and joint simulation is carried out by Quartus II and ModelSim software.
The core technical scheme of the construction of the communication system of the impulse neural network is that the whole hardware architecture of the impulse neural network communication system is constructed on the basis of the circuit design and the synapse interaction mechanism of the two-dimensional piecewise linear impulse neuron model. Starting from the requirements of the stage and the test of the digital system design, on the basis of the existing neuron digital circuit, the neuron digital circuit is expanded according to a random coupling structure, and a corresponding pulse coding and decoding unit is configured and used for completing the response of the digital circuit by acting a pulse memory on the neuron.
In the aspect of neuron circuit design and implementation, the piecewise linear pulse neuron model reduces the use of multipliers, occupies lower hardware resources, can simulate and present rich neural morphology dynamics, can work with higher hardware computing efficiency, and is convenient for expanding to the hardware architecture implementation of a large-scale pulse neural network and the dynamic simulation of a communication system.
It should be noted that, the structure and the function of the undescribed part of the circuit in the embodiment of the present invention are known to those skilled in the art, and are not described in detail in order to reduce redundancy.
The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.
Claims (6)
1. An FPGA implementation method based on a piecewise linear pulse neuron network is characterized by comprising the following steps:
constructing a neuron circuit according to a two-dimensional piecewise linear pulse neuron model so as to integrate and output input information through the neuron circuit, wherein the two-dimensional piecewise linear pulse neuron model comprises an expression of membrane potential of a neuron and an expression of a recovery variable;
and the communication circuit is used for expanding and configuring the pulse coding and decoding unit according to the neuron circuit and a random coupling structure to generate a pulse neural network.
2. The FPGA implementation method based on a piecewise linear impulse neuron network of claim 1, wherein constructing the neuron circuit according to the two-dimensional piecewise linear impulse neuron model comprises:
providing the two-dimensional piecewise linear impulse neuron model;
carrying out digital operation processing, equation transformation and discretization on the two-dimensional piecewise linear pulse neuron model to obtain a discretized piecewise linear pulse neuron model;
and constructing the neuron circuit comprising a multiplexer, a transmission channel, a register and a digital summator according to the discrete piecewise linear pulse neuron model.
3. The FPGA implementation method based on the piecewise linear impulse neural network of claim 1, wherein the communication circuit for generating the impulse neural network by expanding and configuring the impulse coding and decoding unit according to the neuron circuit according to a random coupling structure comprises:
randomly generating a pulse neural network comprising A neurons and B synaptic connections by adopting a random function, wherein the A neurons are randomly coupled, and A and B are integers larger than zero;
constructing a communication circuit comprising a first circuit unit, a second circuit unit and a third circuit unit according to the impulse neural network; the first circuit unit comprises a weight value storage unit and an input calculation unit, and is used for controlling the enhancement or the weakening of synaptic electrical signals between the neuron node connections; the second circuit unit is used for constructing different impulse neural network topological structures on the basis of the two-dimensional piecewise linear impulse neuron model to generate multi-core storage connection vectors, and aiming at impulse neural network simulation in a hardware architecture; the third circuit unit comprises a control unit, a counting buffer and an output unit, and is used for responding different response requirements, sending a control signal to the weight storage unit, calling the weight to participate in network calculation, judging whether the neuron membrane potential reaches a pulse peak value, and calling a corresponding reset mechanism to reset.
4. The FPGA implementation method based on the piecewise linear impulse neuron network of claim 3, wherein the weight storage unit comprises a plurality of buffers, each buffer comprises a plurality of weight values, and the plurality of buffers are connected with each other.
5. The FPGA implementation method based on the piecewise linear impulse neuron network of claim 3, wherein the input calculation unit is configured to input the neurons according to the input weights provided by the weight storage unit, and calculate the input currents of the neurons.
6. The FPGA implementation method based on a piecewise linear pulse neuron network of claim 3, wherein the second circuit unit is shared among a part of neurons through pipelines and buffers.
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