CN112101116B - Simulation circuit fault diagnosis method based on deep learning - Google Patents
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Abstract
One embodiment of the invention discloses a simulation circuit fault diagnosis method based on deep learning, which comprises the following steps: s10, constructing a deep learning network in a deep learning fault diagnosis model; s20, acquiring an output time domain impulse response signal of an analog circuit, wherein the output time domain impulse response signal comprises a training set and a testing set; s30, respectively carrying out normalization processing on the training set and the testing set to obtain normalized impulse response signals of the training set and the testing set; s40, taking a normalized impulse response signal of the training set as input, taking a fault label set during acquisition of the training set as output, training the deep learning fault diagnosis model, and obtaining a fault diagnosis model of the analog circuit; s50, taking the normalized impulse response signal of the test set as the input of a fault diagnosis model of the analog circuit to obtain the diagnosis state of the test set.
Description
Technical Field
The invention relates to the technical field of fault diagnosis, in particular to a simulation circuit fault diagnosis method based on deep learning.
Background
Currently, with the development of electronic technology, electronic devices tend to be integrated and complicated. Whereas it is counted that 80% of the faults occurring in the electronic equipment are caused by analog circuit faults. After the fault occurs, it is very important to judge the fault type and quickly locate the fault. The fault model of the analog circuit is difficult to build due to the non-linear factors of the analog circuit and the existence of analog circuit component tolerances. Therefore, it is important to locate the faulty component of the analog circuit under component tolerance conditions.
The fault diagnosis of the common analog circuit is a fault diagnosis method based on a mathematical model and a fault diagnosis method based on data driving. The fault diagnosis method based on the mathematical model has the advantages that the model reliability is higher, but a better fault mathematical model is difficult to build for different component tolerances. The data-driven based fault diagnosis method consists in building a trainable, adjustable model from a large amount of data. With the rapid development of computer technology, machine learning and artificial intelligence, the deep learning has better performance in the field of data-driven fault diagnosis. At present, there are three kinds of deep learning: deep learning fault diagnosis model, convolutional neural network, cyclic neural network. Variant long and short term memory networks (LSTM) in recurrent neural networks have natural advantages for processing time series signals and operate at a faster speed than other deep learning networks.
Disclosure of Invention
An object of the present invention is to provide a fault diagnosis method for an analog circuit based on deep learning.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a method for diagnosing faults of an analog circuit based on deep learning, the method comprising:
S10, constructing a deep learning network in a deep learning fault diagnosis model;
S20, acquiring an output time domain impulse response signal of an analog circuit, wherein the output time domain impulse response signal comprises a training set and a testing set;
s30, respectively carrying out normalization processing on the training set and the testing set to obtain normalized impulse response signals of the training set and the testing set;
S40, taking a normalized impulse response signal of the training set as input, taking a fault label set during acquisition of the training set as output, training the deep learning fault diagnosis model, and obtaining a fault diagnosis model of the analog circuit;
s50, taking the normalized impulse response signal of the test set as the input of a fault diagnosis model of the analog circuit to obtain the diagnosis state of the test set.
In a specific embodiment, the step S10 further includes:
And constructing a deep learning network in the deep learning fault diagnosis model by utilizing MATLAB, wherein the structure of the deep learning network is connected from top to bottom and sequentially comprises an input layer, an LSTM network, a first full-connection layer, a second full-connection layer, a third full-connection layer, a softmax classification layer and an output layer.
In a specific embodiment, the step S20 further includes:
Simulating an analog circuit by using PSPICE software, taking the output end of the analog circuit as a test point to obtain an impulse response signal, taking the impulse response signal as an input excitation signal of the analog circuit to obtain an output time domain impulse response signal of the analog circuit, collecting the output time domain impulse response signal of a training set as a fault signal under a fault label, collecting the output time domain impulse response signal of a test set as a test signal,
Wherein any element of the analog circuit is placed in a fault condition and the remaining elements are placed in a normal tolerance condition.
In a specific embodiment, the step S30 further includes: the normalization processing mode of the acquired output time domain impulse response signals of the training set and the testing set is as follows:
Wherein x is the acquired time domain impulse response signal at a certain moment, x min is the minimum value in the current impulse response signal, x max is the maximum value in the current impulse response signal, Is normalized result.
In a specific embodiment, the fault diagnosis model of the analog circuit includes:
S401, forward propagation of the LSTM network, wherein the forward propagation comprises forward propagation of forgetting gates, updating gates and output gates, updating of cell states and output of single cells;
s4010, forward propagation of forgetting gate of the LSTM network is as follows:
f(t)＝σ(Wfaa(t-1)+Wfxx(t)+bf)
Wherein, W fa and W fx are forgetting gate weight coefficients, a (t-1) is LSTM hidden output state at t-1 moment, b f is forgetting gate bias, sigma is forgetting gate activation function sigmoid, f (t) is forgetting gate output state at t moment, and x (t) is training set input state;
s4012, forward propagation of the update gate of the LSTM network is:
i(t)＝σ(Wiaa(t-1)+Wixx(t)+bi)
Wherein, W ia and W ix are update gate weight coefficients, a (t-1) is LSTM hidden output state at t-1, b i is update gate bias, sigma is update gate activation function sigmoid, i (t) is update gate output state at t, and x (t) is training set input state;
s4014, updating the cell state of the LSTM network is:
c(t)＝i(t)×(tanh(Wcaa(t-1)+Wcxx(t)+bc))+f(t)×c(t-1)
Wherein i (t) is the output state of the gate updated at the time t, W ca and W cx are the cell state updating weight coefficients, b c is the cell state bias, tanh is the cell state updating activation function tanh function, a (t-1) is the LSTM hidden output state at the time t-1, x (t) is the training set input state, f (t) is the forgetting gate output state at the time t, c (t) is the cell state at the time t, and c (t-1) is the cell state at the time t-1;
s4016, forward propagation of the output gate of the LSTM network is:
o(t)＝σ(Woaa(t-1)+Woxx(t)+bo)
Wherein, W oa and W ox are output gate weight coefficients, a (t-1) is LSTM hidden output state at t-1, b o is output gate bias, sigma is output gate activation function sigmoid, o (t) is output gate output state at t, and x (t) is training set input state;
S4018, single cell output of the LSTM network:
a(t)＝o(t)×tanh(c(t))
wherein a (t) is the LSTM hidden output state at the time t, o (t) is the output state of the output gate at the time t, c (t) is the cell state at the time t, and tanh is the output gate activation function tanh function;
S402, forward propagation of the first full connection layer, wherein the specific process is as follows:
Wherein z 1 (t) is the t output of the first full connection layer, x 1 (t) is the t input of the first full connection layer, w 1t is the weight of the t input of the first full connection layer, b 1 is the bias of the t input of the first full connection layer, t is the moment, any one of 1 … n is taken, and n is a natural number greater than or equal to 1;
s403, forward propagation of the second full connection layer, wherein the specific process is as follows:
Wherein z 2 (t) is the t output of the second fully-connected layer, x 2 (t) is the t input of the second fully-connected layer, w 2t is the weight of the t input of the second fully-connected layer, and b 2 is the bias of the t input of the second fully-connected layer;
S404, forward propagation of the third full connection layer, wherein the specific process is as follows:
wherein z 3 (t) is the t output of the third fully-connected layer, x 3 (t) is the t input of the third fully-connected layer, w 3t is the weight of the t input of the third fully-connected layer, and b 3 is the bias of the t input of the third fully-connected layer;
s405, forward propagation of the softmax classification layer is carried out, wherein the specific process is as follows:
Wherein z 3 (t) is the t output of the third full connection layer, p (t) is the t output of the classification layer, and n is the classification number of the classification layer.
In a specific embodiment, the fault diagnosis model of the analog circuit further includes:
The reverse training of the deep learning network combines the loss value L and the random gradient method to carry out iterative updating on each parameter until reaching the termination condition,
The loss value L is represented by the following formula:
Wherein, And y (t) is the actual value of the fault label of the training set as the output value of the fault diagnosis model.
The stochastic gradient method is represented by the following formula:
Wherein β 1 is the attenuation coefficient of the gradient, n is the number of iterations, W a(n) is the weight coefficient of the nth iteration, L is the loss value, and W a(n+1) is the weight coefficient of the n+1th iteration.
The beneficial effects of the invention are as follows:
The invention establishes the fault model of the analog circuit by extracting the impulse response of the analog circuit and training the deep learning fault diagnosis model. Combining the excellent feature extraction capability of LSTM on the time sequence, introducing a multi-layer fully-connected network to deepen the depth of the neural network, and finally obtaining a responsive fault label by utilizing the high-efficiency classification capability of softmax; the invention can distinguish fault elements and the change trend of the elements in fault state, improves the accuracy of fault diagnosis, reduces the training time of deep learning fault diagnosis model and improves the detection efficiency.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the drawings.
FIG. 1 shows a flow chart of a method for diagnosing analog circuit faults based on deep learning according to an embodiment of the present invention.
FIG. 2 shows a schematic diagram of a deep learning fault diagnosis model according to one embodiment of the invention.
FIG. 3 shows a sallen-key bandpass filter block diagram according to one embodiment of the invention.
FIG. 4 illustrates a deep learning fault diagnosis model training flow diagram according to one embodiment of the invention.
Fig. 5 shows a structure diagram of an LSTM cell according to an embodiment of the present invention.
FIG. 6 shows an analog circuit fault diagnosis flow chart according to one embodiment of the invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to preferred embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.
FIG. 1 shows a flow chart of a deep learning based analog circuit fault diagnosis method according to one embodiment of the application, the method comprising:
S10, constructing a deep learning network in a deep learning fault diagnosis model.
In a specific embodiment, the step S10 further includes:
And constructing a deep learning network in the deep learning fault diagnosis model by utilizing MATLAB, wherein the structure of the deep learning network is connected from top to bottom and sequentially comprises an input layer, an LSTM network, a first full-connection layer, a second full-connection layer, a third full-connection layer, a softmax classification layer and an output layer.
In one example, a deep learning fault diagnosis model schematic diagram of one embodiment of the present invention is shown in FIG. 2. The number of nodes of the deep learning fault diagnosis model structure is N-N-N-a-b-b-1. The deep learning fault diagnosis model structure is set to be 500-500-500-75-11-11-1, wherein the first 500 is the number of data input by an input layer, the second 500 is the number of LSTM unit cells, the third 500 is the number of nodes of a first full-connection layer, the third 500 is the number of nodes of a second full-connection layer, the first 11 is the number of nodes of a third full-connection layer, the second 11 is the number of nodes of a softmax layer, and the first 1 is the number of nodes of an output layer.
S20, collecting output time domain impulse response signals of the analog circuit, wherein the output time domain impulse response signals comprise a training set and a testing set.
In a specific embodiment, the step S20 further includes:
simulating an analog circuit by using PSPICE software, taking the output end of the analog circuit as a test point to obtain an impulse response signal, taking the impulse response signal as an input excitation signal of the analog circuit to obtain an output time domain impulse response signal of the analog circuit, collecting the output time domain impulse response signal of a training set as a fault signal under a fault label, and collecting the output time domain impulse response signal of a test set as a test signal. The input to the circuit is a pulse signal of 5V amplitude, 1us rise time, 10us duration, and 1us fall time. And (3) sampling the output of the circuit with equal time, wherein the sampling period is 0.1us, the total sampling time is 50us, and 500 sampling points are acquired in total to obtain a primary impulse response signal of the analog circuit.
Wherein any element of the analog circuit is placed in a fault condition and the remaining elements are placed in a normal tolerance condition and sampled multiple times.
The sallen-key band-pass filter is selected as an analog circuit in this embodiment, and a sallen-key band-pass filter structure diagram of an embodiment of the invention is shown in fig. 3. Aiming at the sallen-key band-pass filter shown in fig. 3, PSPICE simulation is carried out on the circuit, and component single fault setting is carried out on five components of C1, C2, R1, R2 and R3 respectively, so that the following 10 fault circuits are obtained: c1 ∈, C1 ∈, C2 ∈, R1 ∈, R2 ∈, R3 ∈, and R3 ∈, wherein the ∈ and ∈ of the capacitor represent 10% above and below the normal value, and the ∈ and ∈ of the resistor represent 5% above and below the normal value.
S30, respectively carrying out normalization processing on the training set and the testing set to obtain normalized impulse response signals of the training set and the testing set.
In a specific embodiment, the step S30 further includes: the normalization processing mode of the acquired output time domain impulse response signals of the training set and the testing set is as follows:
Wherein x is the acquired time domain impulse response signal at a certain moment, x min is the minimum value in the current impulse response signal, x max is the maximum value in the current impulse response signal, Is normalized result.
S40, taking the normalized impulse response signal of the training set as input, taking the fault label set during acquisition of the training set as output, training the deep learning fault diagnosis model, and obtaining the fault diagnosis model of the analog circuit.
In a specific embodiment, as shown in fig. 4, a training flowchart of a deep learning fault diagnosis model of an embodiment of the present invention is shown, where the fault diagnosis model of the analog circuit includes:
S401, forward propagation of the LSTM network, including forward propagation of forget gates, update gates and output gates, updating of cell states and output of single cells.
In one embodiment, shown in FIG. 5 is a block diagram of an LSTM cell of one embodiment of the invention, including a forget gate, a refresh gate, a cell state, an output gate, and a single cell.
S4010, forward propagation of forgetting gate of the LSTM network is as follows:
f(t)＝σ(Wfaa(t-1)+Wfxx(t)+bf)
Wherein, W fa and W fx are forgetting gate weight coefficients, a (t-1) is LSTM hidden output state at t-1 moment, b f is forgetting gate bias, sigma is forgetting gate activation function sigmoid, f (t) is forgetting gate output state at t moment, and x (t) is training set input state.
S4012, forward propagation of the update gate of the LSTM network is:
i(t)＝σ(Wiaa(t-1)+Wixx(t)+bi)
Wherein, W ia and W ix are update gate weight coefficients, a (t-1) is LSTM hidden output state at time t-1, b i is update gate bias, sigma is update gate activation function sigmoid, i (t) is update gate output state at time t, and x (t) is training set input state.
S4014, updating the cell state of the LSTM network is:
c(t)＝i(t)×(tanh(Wcaa(t-1)+Wcxx(t)+bc))+f(t)×c(t-1)
Wherein i (t) is the output state of the t-moment updating gate, W ca and W cx are the cell state updating weight coefficients, b c is the cell state bias, tanh is the cell state updating activation function tanh function, a (t-1) is the LSTM hidden output state at the t-1 moment, x (t) is the training set input state, f (t) is the forgetting gate output state at the t moment, c (t) is the cell state at the t moment, and c (t-1) is the cell state at the t-1 moment.
S4016, forward propagation of the output gate of the LSTM network is:
o(t)＝σ(Woaa(t-1)+Woxx(t)+bo)
Wherein, W oa and W ox are output gate weight coefficients, a (t-1) is LSTM hidden output state at time t-1, b o is output gate bias, sigma is output gate activation function sigmoid, o (t) is output gate output state at time t, and x (t) is training set input state.
S4018, single cell output of the LSTM network:
a(t)＝o(t)×tanh(c(t))
Wherein a (t) is the LSTM hidden output state at time t, o (t) is the output gate output state at time t, c (t) is the cell state at time t, and tanh is the output gate activation function tanh function.
S402, forward propagation of the first full connection layer, wherein the specific process is as follows:
Wherein z 1 (t) is the t output of the first full connection layer, x 1 (t) is the t input of the first full connection layer, w 1t is the weight of the t input of the first full connection layer, b 1 is the bias of the t input of the first full connection layer, t is the moment, any one of 1 … n is taken, and n is a natural number greater than or equal to 1.
S403, forward propagation of the second full connection layer, wherein the specific process is as follows:
Where z 2 (t) is the t output of the second fully connected layer, x 2 (t) is the t input of the second fully connected layer, w 2t is the weight of the t input of the second fully connected layer, and b 2 is the bias of the t input of the second fully connected layer.
S404, forward propagation of the third full connection layer, wherein the specific process is as follows:
Where z 3 (t) is the t output of the third fully connected layer, x 3 (t) is the t input of the third fully connected layer, w 3t is the weight of the t input of the third fully connected layer, and b 3 is the bias of the t input of the third fully connected layer.
S405, forward propagation of the softmax classification layer is carried out, wherein the specific process is as follows:
Wherein z 3 (t) is the t output of the third full connection layer, p (t) is the t output of the classification layer, and n is the classification number of the classification layer.
In a specific embodiment, the fault diagnosis model of the analog circuit further includes:
The reverse training of the deep learning network combines the loss value L and the random gradient method to carry out iterative updating on each parameter until reaching the termination condition,
The loss value L is represented by the following formula:
Wherein, And y (t) is the actual value of the fault label of the training set as the output value of the fault diagnosis model.
The stochastic gradient method is represented by the following formula:
Wherein β 1 is the attenuation coefficient of the gradient, n is the number of iterations, W a(n) is the weight coefficient of the nth iteration, L is the loss value, and W a(n+1) is the weight coefficient of the n+1th iteration.
S50, taking the normalized impulse response signal of the test set as the input of a fault diagnosis model of the analog circuit to obtain the diagnosis state of the test set.
In a specific embodiment, as shown in fig. 6, which is a flow chart of fault diagnosis of an analog circuit according to an embodiment of the present invention, firstly, output time domain impulse response signals of a test set are collected, and then normalization processing is performed on the collected output time domain impulse response signals of the test set, where the normalization processing method is as follows, normalization processing is performed on the collected output time domain impulse response signals of the test set:
Wherein x is the acquired time domain impulse response signal at a certain moment, x min is the minimum value in the current impulse response signal, x max is the maximum value in the current impulse response signal, Is normalized result.
And taking the normalized output response of the test set as the input of a fault diagnosis model of the analog circuit, and outputting a fault element and a fault element change trend, such as a fault of R3 #.
To further verify the effectiveness of the present protocol, the method described in the present protocol was verified in conjunction with specific experiments, the results of which are shown in table 1.
Table 1 results of the method and single failure verification described in this embodiment
As can be seen from table 1, the detection rates of the method according to the embodiment of the present invention on the capacitors C1 ∈, C2 ∈, all reach 100%, the method according to the embodiment of the present invention on the resistors R1 ∈, R2 ∈, the detection rate of R3 ∈ reaches 100%, the detection rate of the resistor R1 ∈ reaches 98.7%, the detection rate of the resistor R3 ∈ reaches 99.6%, and the group of experiments prove that the method disclosed by the embodiment of the invention has high diagnosis precision and good fault detection effect.
It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (5)
1. The simulation circuit fault diagnosis method based on deep learning is characterized by comprising the following steps:
S10, constructing a deep learning network in a deep learning fault diagnosis model;
S20, acquiring an output time domain impulse response signal of an analog circuit, wherein the output time domain impulse response signal comprises a training set and a testing set;
s30, respectively carrying out normalization processing on the training set and the testing set to obtain normalized impulse response signals of the training set and the testing set;
S40, taking a normalized impulse response signal of the training set as input, taking a fault label set during acquisition of the training set as output, training the deep learning fault diagnosis model, and obtaining a fault diagnosis model of the analog circuit;
s50, taking the normalized impulse response signal of the test set as the input of a fault diagnosis model of the analog circuit to obtain the diagnosis state of the test set;
The fault diagnosis model of the analog circuit comprises:
s401, forward propagation of LSTM networks, including forward propagation of forget gate, update gate and output gate, update of cell state and output of single cells;
s4010, forward propagation of forgetting gate of the LSTM network is as follows:
f(t)＝σ(Wfaa(t-1)+Wfxx(t)+bf)
Wherein, W fa and W fx are forgetting gate weight coefficients, a (t-1) is LSTM hidden output state at t-1 moment, b f is forgetting gate bias, sigma is forgetting gate activation function sigmoid, f (t) is forgetting gate output state at t moment, and x (t) is training set input state;
s4012, forward propagation of the update gate of the LSTM network is:
i(t)＝σ(Wiaa(t-1)+Wixx(t)+bi)
Wherein, W ia and W ix are update gate weight coefficients, a (t-1) is LSTM hidden output state at t-1, b i is update gate bias, sigma is update gate activation function sigmoid, i (t) is update gate output state at t, and x (t) is training set input state;
s4014, updating the cell state of the LSTM network is:
c(t)＝i(t)×(tanh(Wcaa(t-1)+Wcxx(t)+bc))+f(t)×c(t-1)
Wherein i (t) is the output state of the gate updated at the time t, W ca and W cx are the cell state updating weight coefficients, b c is the cell state bias, tanh is the cell state updating activation function tanh function, a (t-1) is the LSTM hidden output state at the time t-1, x (t) is the training set input state, f (t) is the forgetting gate output state at the time t, c (t) is the cell state at the time t, and c (t-1) is the cell state at the time t-1;
s4016, forward propagation of the output gate of the LSTM network is:
o(t)＝σ(Woaa(t-1)+Woxx(t)+bo)
Wherein, W oa and W ox are output gate weight coefficients, a (t-1) is LSTM hidden output state at t-1, b o is output gate bias, sigma is output gate activation function sigmoid, o (t) is output gate output state at t, and x (t) is training set input state;
S4018, single cell output of the LSTM network:
a(t)＝o(t)×tanh(c(t))
wherein a (t) is the LSTM hidden output state at the time t, o (t) is the output state of the output gate at the time t, c (t) is the cell state at the time t, and tanh is the output gate activation function tanh function;
s402, forward propagation of a first full connection layer, wherein the specific process is as follows:
Wherein z 1 (t) is the t output of the first full connection layer, x 1 (t) is the t input of the first full connection layer, w 1t is the weight of the t input of the first full connection layer, b 1 is the bias of the t input of the first full connection layer, t is the moment, any one of 1 … n is taken, and n is a natural number greater than or equal to 1;
S403, forward propagation of a second full connection layer, wherein the specific process is as follows:
Wherein z 2 (t) is the t output of the second fully-connected layer, x 2 (t) is the t input of the second fully-connected layer, w 2t is the weight of the t input of the second fully-connected layer, and b 2 is the bias of the t input of the second fully-connected layer;
S404, forward propagation of a third full connection layer, wherein the specific process is as follows:
wherein z 3 (t) is the t output of the third fully-connected layer, x 3 (t) is the t input of the third fully-connected layer, w 3t is the weight of the t input of the third fully-connected layer, and b 3 is the bias of the t input of the third fully-connected layer;
S405, forward propagation of a softmax classification layer, which comprises the following specific processes:
Wherein z 3 (t) is the t output of the third full connection layer, p (t) is the t output of the classification layer, and n is the classification number of the classification layer.
2. The method of claim 1, wherein S10 further comprises:
And constructing a deep learning network in the deep learning fault diagnosis model by utilizing MATLAB, wherein the structure of the deep learning network is connected from top to bottom and sequentially comprises an input layer, an LSTM network, a first full-connection layer, a second full-connection layer, a third full-connection layer, a softmax classification layer and an output layer.
3. The method of claim 1, wherein S20 further comprises:
Simulating an analog circuit by using PSPICE software, taking the output end of the analog circuit as a test point to obtain an impulse response signal, taking the impulse response signal as an input excitation signal of the analog circuit to obtain an output time domain impulse response signal of the analog circuit, collecting the output time domain impulse response signal of a training set as a fault signal under a fault label, collecting the output time domain impulse response signal of a test set as a test signal,
Wherein any element of the analog circuit is placed in a fault condition and the remaining elements are placed in a normal tolerance condition.
4. The method of claim 1, wherein S30 further comprises: the normalization processing mode of the acquired output time domain impulse response signals of the training set and the testing set is as follows:
Wherein x is the acquired time domain impulse response signal at a certain moment, x min is the minimum value in the current impulse response signal, x max is the maximum value in the current impulse response signal, Is normalized result.
5. The method of claim 1, wherein the fault diagnosis model of the analog circuit further comprises:
The reverse training of the deep learning network combines the loss value L and the random gradient method to carry out iterative updating on each parameter until reaching the termination condition,
The loss value L is represented by the following formula:
Wherein, Y (t) is the actual value of the fault label of the training set for the output value of the fault diagnosis model;
the stochastic gradient method is represented by the following formula:
Wherein β 1 is the attenuation coefficient of the gradient, n is the number of iterations, W a(n) is the weight coefficient of the nth iteration, L is the loss value, and W a(n+1) is the weight coefficient of the n+1th iteration.
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