CN112099877B

CN112099877B - Method for loading FPGA and DSP by remote programming

Info

Publication number: CN112099877B
Application number: CN202011166242.XA
Authority: CN
Inventors: 周威威; 金垭梅; 蒋张涛; 罗睿梅; 万东燕; 袁鹏程; 封淑青; 吴勤
Original assignee: Shanghai Radio Equipment Research Institute
Current assignee: Shanghai Radio Equipment Research Institute
Priority date: 2020-10-27
Filing date: 2020-10-27
Publication date: 2022-10-18
Anticipated expiration: 2040-10-27
Also published as: CN112099877A

Abstract

The invention discloses a method for remotely programming and loading an FPGA and a DSP, which comprises the following steps: the first FLASH program memory in the signal processor includes: the first FPGA hardware partition is used for storing FPGA skipping and programming programs; the second FPGA hardware partition is used for storing an effective mark of an FPGA formal program storage block; and the third FPGA hardware partition is used for storing a plurality of FPGA formal programs. The second FLASH program memory in the signal processor comprises a first DSP hardware partition for storing DSP jump and programming programs; the second DSP hardware partition is used for storing an effective mark of a DSP formal program storage block and an effective mark of a DSP formal parameter storage block; the third DSP hardware partition is used for storing a plurality of DSP formal programs; and the fourth DSP hardware partition is used for storing a plurality of DSP formal parameters. The invention can remotely and reliably burn, load and switch formal programs/parameters in one memory block without influencing other memory blocks.

Description

Method for loading FPGA and DSP by remote programming

Technical Field

The invention relates to the technical field of information, in particular to a method for remotely programming, loading and switching FPGA (field programmable gate array) and DSP (digital signal processor) programs.

Background

The modern radar Signal processor forms a mainstream architecture taking an FPGA (Field-Programmable Gate Array) and a DSP (Digital Signal Processing) as cores, and debugging and programming of programs of the FPGA and the DSP are mainly performed in a JTAG (Joint Test Action Group) bus manner. In long-distance transmission, the JTAG bus has poor anti-interference capability and high error rate, and can increase burden on the whole radar structure and software and hardware design after being led out, so the JTAG bus is not suitable for being used as an external programming bus of the whole radar. With the progress of radar technology, the algorithm of a signal processor is more and more complex, and the establishment of a verification environment close to a real use scene is difficult, so that the remote reliable programming, loading and rapid switching verification methods of various algorithm schemes need to be researched, and the method is also beneficial to rapidly switching a radar complete machine into a program which is correspondingly optimized according to a deployment environment.

At present, only one formal program is stored in a FLASH program memory of an FPGA and a DSP, and an original program needs to be erased before a new program is programmed, so that the risk that the formal program is not available in FLASH after programming updating fails midway due to unstable communication is caused, the method is not suitable for reliable and rapid updating and upgrading in use of important equipment, and is also not suitable for occasions of multi-scheme rapid verification of a radar complete machine and rapid program algorithm switching according to a deployment environment.

Disclosure of Invention

The invention aims to provide a method for remotely programming and loading an FPGA and a DSP, so as to realize the remote and reliable programming and loading of the FPGA and the DSP programs of a signal processor in the state of a complete radar machine and realize the purpose of quickly switching program algorithms.

In order to achieve the above purpose, the invention is realized by the following technical scheme:

a method for remotely programming and loading an FPGA and a DSP comprises the following steps:

dividing a first FLASH program memory corresponding to each FPGA in the signal processor into three FPGA hardware partitions;

a first FPGA hardware partition in the three FPGA hardware partitions is used for storing FPGA skipping and programming programs;

the second FPGA hardware partition is used for storing an effective mark of an FPGA formal program storage block;

the third FPGA hardware partition is used for storing a plurality of FPGA formal programs;

dividing a second FLASH program memory corresponding to each DSP in the signal processor into four DSP hardware partitions,

the first DSP hardware partition in the four DSP hardware partitions is used for storing DSP jump and programming programs;

the second DSP hardware partition is used for storing an effective mark of a DSP formal program storage block and an effective mark of a DSP formal parameter storage block;

the third DSP hardware partition is used for storing a plurality of DSP formal programs;

the fourth DSP hardware partition is used for storing a plurality of DSP formal parameters;

after each FPGA and each DSP receive a control command sent by an upper computer,

each FPGA executes a control command sent by the upper computer, determines the address range and the effective mark address of a storage block of a formal FPGA program to be programmed according to the control command, and programs the data of the formal FPGA program into the third FPGA hardware partition;

and each DSP executes a control command sent by the upper computer, determines a DSP formal program storage block address range and an effective mark address to be programmed or a DSP formal parameter storage block address range and an effective mark address according to the control command, and correspondingly programs or DSP formal parameters into the third DSP hardware partition or the fourth DSP hardware partition.

Preferably, the second FPGA hardware partition includes a first FPGA storage block, a second FPGA storage block, and a plurality of third FPGA storage blocks;

the first FPGA storage block is used for storing the serial number of a default FPGA formal program storage block;

the second FPGA storage block is used for storing the size of an FPGA formal program storage block;

each third FPGA storage block is used for storing an effective mark of an FPGA formal program storage block;

the third FPGA hardware partition comprises a plurality of FPGA formal program storage blocks, and each FPGA formal program storage block correspondingly stores one FPGA formal program;

the first DSP hardware partition comprises two first DSP memory blocks, wherein one first DSP memory block is used for storing a secondary loading program, and the other first DSP memory block is used for storing a programming program;

the second DSP hardware partition comprises a second DSP storage block, a third DSP storage block, a plurality of fourth DSP storage blocks and a plurality of fifth DSP storage blocks;

the second DSP storage block is used for storing the serial number of the default DSP formal program storage block;

the third DSP storage block is used for storing the size of a DSP formal program storage block;

each fourth DSP memory block is used for storing a valid mark of a DSP formal program memory block;

each fifth DSP storage block is used for storing an effective mark of a DSP formal parameter storage block;

the third DSP hardware partition comprises a plurality of DSP formal program storage blocks, and each DSP formal program storage block correspondingly stores a DSP formal program;

the fourth DSP hardware partition comprises a plurality of DSP formal parameter storage blocks, and each DSP formal parameter storage block correspondingly stores one DSP formal parameter.

Preferably, after the signal processor is powered on, it executes the program and parameter programming operation mode, including:

s1.1, correspondingly operating the FPGA skipping and programming program by the FPGA to be programmed; correspondingly operating the secondary loading program by the DSP to be programmed;

s1.2, in a preset time range, the FPGA to be programmed and the DSP receive a control command sent by an upper computer, and when the control command is a command frame for starting programming, the FPGA to be programmed continues to run the FPGA jump and programming program; the DSP to be programmed runs a programming program;

s1.3, calculating an address range and an effective mark address of a storage block to be programmed by the FPGA and/or the DSP to be programmed, erasing an effective mark of the storage block to be programmed according to the address range and the effective mark address of the storage block to be programmed, and then erasing a formal program or formal parameters stored in the storage block to be programmed;

s1.4, after receiving the data frame sent by the upper computer, the FPGA and/or the DSP to be programmed calculates the programming address of the data frame of the frame, judges whether the address range of the current storage block to be programmed is exceeded, if the address range of the current storage block to be programmed is exceeded, the abnormal state is uploaded to the upper computer, data overrun is displayed, and otherwise, the FPGA and/or the DSP to be programmed correspondingly programs the data frame into the current storage block to be programmed;

and S1.5, after the data frame of the current frame is completely programmed, the FPGA and/or the DSP to be programmed requests the upper computer for a next frame of data frame, and the steps S1.2 to S1.4 are repeated until the upper computer sends a programming ending instruction frame.

Preferably, before executing the step S1.4, the method further includes: testing communication before programming: the upper computer generates and sequentially issues a plurality of data frames, and the FPGA and/or the DSP to be programmed sequentially programs the data frames into a storage block to be programmed currently; after programming is completed, the FPGA and/or the DSP to be programmed transmits all data frames stored in the storage block to be programmed back to the upper computer, and the data frames are compared with effective contents of the data frames generated by the upper computer; if the contents of the two are consistent, the comparison is passed, the current memory block to be programmed is erased again, and the step S1.4 is entered, otherwise, a communication error is displayed until a new programming command is received.

Preferably, the method further comprises the following steps: s1.6, correspondingly reading all data to be programmed from a currently programmed storage block by the FPGA and/or the DSP, segmenting and packaging all the data to be programmed into data frames, transmitting the data frames back to an upper computer, comparing and checking the transmitted data frames with an original programming program file by the upper computer after transmission is finished, if the data frames are consistent with the original programming program file, passing the check, setting a mark corresponding to the currently programmed storage block to be valid, and ending the programming process; otherwise, the verification is failed.

Preferably, each of the data frames includes a frame header, a frame length, a frame stream number, data, and CRC check bits.

Preferably, after the signal processor is powered on, it executes a program to switch the operating mode, including:

s2.1, the FPGA to be converted runs a jump and programming program, and the DSP to be converted runs a secondary loading program;

s2.2, in a preset time range, the FPGA to be converted and the DSP receive a control command sent by an upper computer, and when the control command is a command frame for starting switching, the FPGA to be converted continues to run the FPGA jump and programming program; the DSP to be converted continues to run the secondary loading program;

s2.3, reading the size of a formal program storage block to calculate the address range and the effective mark address of the formal program storage block according to the received formal program storage block number which is sent by the upper computer and needs to be switched by the FPGA and/or the DSP to be converted by combining a fixed formal program, a base address of an effective mark storage area and the size of the effective mark storage block;

s2.4, the FPGA and/or the DSP to be converted reads an effective mark of a formal program storage block from a corresponding first or second FLASH program memory, judges whether the formal program is effective, and enters the step S2.5 if the formal program is effective, otherwise, a program error is output;

and S2.5, erasing the default formal program storage block number in the corresponding first or second FLASH program storage by the FPGA and/or the DSP to be converted, programming the formal program storage block number to be switched, and ending the switching process.

Preferably, after the signal processor is powered on, it executes a program loading mode of operation, including:

s3.1, the FPGA to be loaded runs a jump and programming program, and the DSP to be loaded runs a secondary loading program;

s3.2, in a preset time range, when the FPGA and/or the DSP to be loaded receive a direct start control command sent by an upper computer or do not receive any effective instruction sent by the upper computer in the preset time range, entering the step S3.3;

s3.3, the FPGA and/or the DSP to be loaded reads the default formal program storage block number from the fixed address in the corresponding first or second FLASH program storage, reads the storage block size in the corresponding first or second FLASH program storage by combining the fixed formal program, the effective mark storage area base address and the effective mark storage block size, and calculates the address range and the effective mark address of the storage block;

s3.4, reading an effective mark of a formal program to be loaded by the FPGA and/or the DSP to be loaded, judging whether the formal program is effective, if so, calling an ICAPE core by the FPGA to be loaded, pointing a loading address to a first address of a storage block in which the formal program is stored, and loading the formal program into the FPGA after restarting; the DSP to be loaded reads the formal program from the storage block to the kernel for loading, and the jump from the secondary loading program to the appointed formal program is realized; if the flag is invalid, returning a program error; and completing program loading.

Compared with the prior art, the invention has at least one of the following advantages:

the invention provides a method for reliably programming, loading and switching an FPGA and a DSP of a multi-formal program. In the method, in the complete machine state of the radar seeker, all FPGA and DSP chips on a board are directly programmed, switched and selectively loaded through an original communication bus of a signal processor.

The first FLASH program memory and the second FLASH program memory are divided into regions, a plurality of formal programs and formal parameter memory blocks are arranged, one-time programming is only operated in one memory block, and once errors occur, the existing formal programs and parameters are not influenced, so that the method is favorable for quick switching and reliability improvement, and is suitable for reliable upgrading in use of important equipment.

All FPGA and DSP chips load appointed formal programs through skipping and programming programs, the time-sharing multiplexing design can enable the two programs to completely occupy all resources to realize more complex functions, special requirements on software and hardware design of a signal board are avoided, and programming, switching and loading states can be comprehensively monitored.

Various modes are adopted to ensure that the programming content is complete and accurate: communication test, CRC frame check, frame number query transmission, frame address calculation check and readback check. The method has the advantages that no new control chip is added, the original circuit connection is not changed, the programming function is not realized in a formal program, the structure of a signal processor and the design burden of software and hardware are not increased, and new and old products can be well considered.

Drawings

FIG. 1 is a block diagram of a signal processor according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating the partitioning of a FLASH program memory according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating the partitioning of the FLASH program memory into hardware partitions according to an embodiment of the present invention;

fig. 4 is a flowchart illustrating programming of programs and parameters in a method for remotely programming and loading an FPGA and a DSP according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a data frame structure and programming in a method for remotely programming and loading an FPGA and a DSP according to an embodiment of the present invention;

fig. 6 is a flowchart illustrating program switching in a method for remotely programming and loading an FPGA and a DSP according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating program loading in a method for remotely programming and loading an FPGA and a DSP according to an embodiment of the present invention.

Detailed Description

As described in the background art, only one formal program is stored in the FLASH program memory of the FPGA and the DSP at present, and the original program needs to be erased before programming a new program, which may cause that there is no risk of an available formal program in the FLASH after a programming update fails midway due to unstable communication, and is not suitable for reliable and fast updating and upgrading in use of important devices, and is also not suitable for occasions of multi-scheme fast verification of a radar complete machine and fast program algorithm switching according to a deployment environment. The research shows that the content of the active ingredients in the product is high,

in the prior art: patent number CN201310223392.3 ("interface extensible program programming method based on DSP platform") proposes a DSP remote programming method compatible with multiple communication modes, which can directly program a new program into FLASH from an upper computer through an external DSP interface. However, the method can only perform remote programming on a single DSP with an external interface, the programming function occupies DSP resources, and once programming fails, recovery cannot be performed.

The patent No. CN201410069555.1 ("method and apparatus for programming and starting FPGA and DSP target program") stores FPGA and DSP program in the same FLASH program memory, and loads FPGA first and then loads DSP through FPGA when power is turned on. The method simplifies the programming process, realizes the simultaneous programming of the FPGA and the DSP by one JTAG bus, but still does not get rid of the limitation of the JTAG bus, and is not suitable for the programming with long distance and high reliability.

Therefore, in the FPGA + DSP framework, how to utilize the existing hardware platform to realize remote and reliable programming, loading and fast switching of each FPGA and DSP program is a problem with practical value.

The method for remotely programming and loading the FPGA and the DSP according to the present invention is further described in detail with reference to fig. 1 to 7 and the detailed description. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise scale for the purpose of facilitating and distinctly aiding in the description of the embodiments of the present invention. To make the objects, features and advantages of the present invention comprehensible, reference is made to the accompanying drawings. It should be understood that the structures, ratios, sizes, etc. shown in the drawings and attached to the description are only for understanding and reading the disclosure of the present disclosure, and are not for limiting the scope of the present disclosure, so they do not have the essential meaning in the art, and any modifications of the structures, changes of the ratio relationships, or adjustments of the sizes, should fall within the scope of the present disclosure without affecting the efficacy and the achievable purpose of the present disclosure.

With reference to fig. 1 to 3, the present embodiment provides a method for remotely programming and loading an FPGA and a DSP,

referring to fig. 1, the signal processor includes: a plurality of FPGA chips and a plurality of DSP chips. For better illustration of the internal structure of the signal processor; the following description will be given by taking two FPGAs and two DSP chips as examples: a first FPGA chip FPGA1 and a second FPGA chip FPGA2 in the two FPGA chips are connected by a first JTAG chain; the first FPGA chip FPGA1 is communicated to a first interface through the first JTAG chain and extends to the outside of the plate through the first interface for the programming of the simulator; a first DSP chip DSP1 and a second DSP chip DSP2 in the two DSP chips are connected by a second JTAG chain; and the second interface extends to the outside of the plate and is also used for programming by the simulator. And each FPGA chip and each DSP chip on the board are respectively connected with an upper computer by adopting a data communication bus and communicated with the upper computer. The embodiment can use the original data communication bus of the signal processor without modifying hardware. Each FPGA chip on the board is correspondingly connected with a first FLASH program memory by a FLASH bus; and each DSP chip on the board is correspondingly connected with a second FLASH program memory by adopting a FLASH bus.

In the embodiment, the FPGA chip is a 7K325T chip of XILINX company; the DSP chip is a TMS320C6678 chip of TI company; FLASH is S29GL01GS chip of SPANSION company; the data communication bus is an RS422 bus; the loading bus is a FLASH bus.

Referring to fig. 2 and 3, each first FLASH program memory in the signal processor is divided into three FPGA hardware partitions.

And a first FPGA hardware partition sector00 in the three FPGA hardware partitions is used for storing FPGA jump and programming programs.

The second FPGA hardware partition sector11 is used for storing an effective mark of an FPGA formal program storage block;

specifically, the second FPGA hardware partition sector11 includes a first FPGA storage block, a second FPGA storage block, and a plurality of third FPGA storage blocks.

The first FPGA storage block is used for storing the serial number of the default FPGA formal program storage block.

And the second FPGA storage block is used for storing the size of the formal FPGA program storage block.

Each third FPGA storage block is used for storing an effective mark of an FPGA formal program;

the third FPGA hardware partition Sector22 includes a plurality of FPGA formal program storage blocks, and each FPGA formal program storage block correspondingly stores one FPGA formal program. And dividing each second FLASH program memory in the signal processor into four DSP hardware partitions.

A first DSP hardware partition Sector0 in the four DSP hardware partitions is used for storing DSP jump and programming programs; the second DSP hardware partition Sector1 is used for storing a DSP formal program storage block effective mark and a DSP formal parameter storage block effective mark; the third DSP hardware partition Sector2 is used for storing a plurality of DSP formal programs; and the fourth DSP hardware partition Sector3 is used for storing a plurality of DSP formal parameters.

The first DSP hardware partition Sector0 comprises two first DSP memory blocks, wherein one first DSP memory block is used for storing a secondary loading program (bootloader), and the other first DSP memory block is used for storing a programming program.

The second DSP hardware partition Sector1 comprises a second DSP storage block, a third DSP storage block, a plurality of fourth DSP storage blocks and a plurality of fifth DSP storage blocks.

And the second DSP storage block is used for storing the default DSP formal program storage block number.

And the third DSP storage block is used for storing the size of a DSP formal program storage block.

And each fourth DSP memory block is used for storing a valid mark of a DSP formal program memory block.

And each fifth DSP storage block is used for storing a valid mark of a DSP formal parameter storage block.

The third DSP hardware partition sector2 includes a plurality of DSP formal program storage blocks, and each DSP formal program storage block correspondingly stores one DSP formal program.

The fourth DSP hardware partition sector3 includes a plurality of DSP formal parameter storage blocks, and each DSP formal parameter storage block correspondingly stores one DSP formal parameter.

The FPGA skipping and programming program stored in the first FPGA hardware partition is a complete project; the jump function in the DSP jump and programming program stored in the first DSP hardware partition is realized by a secondary loading program (bootloader), and the programming program in the DSP jump and programming program is realized by a main function, so that the DSP jump and the programming program form a complete project. The sizes of the internal storage blocks for storing the FPGA formal program, the DSP formal program and the DSP formal parameters are respectively equal.

It should be noted that, before the write operation, the first FLASH program memory and the second FLASH program memory need to be erased, and the erase is performed with a hardware partition (Sector) as a minimum operation unit. As shown in fig. 3, in the present embodiment, a model S29GL01GS chip is used as the first FLASH program memory and the second FLASH program memory, the size of the memory space is 128Mbyte, and the memory space is divided into 1024 hardware partitions with size of 128Kbyte from the address 0x 0. The triangle marked area in fig. 2 is a functional area that needs to be changed as a whole, and in order not to affect each other, the address boundary of each functional area needs to be aligned with the hardware partition, that is, each functional area can only use one or a continuous number of 1024 hardware partitions.

The program stored in the 'jump and programming program' in the FLASH is a starting program of each FPGA/DSP after being electrified, and the FPGA/DSP can automatically start to load the program from the 0x0 address after being electrified, so that the program is placed in a plurality of continuous hardware partitions starting from the 0x0 address. The formal FPGA programs start bit stream compression, reduce the data volume of the programs, reduce the size of program storage blocks, improve the programming speed and improve the programming reliability.

In the state of the whole radar, FLASH operations such as formal program and parameter programming, loader switching and the like have high requirements on the accuracy of data and addresses, and once a fault occurs, one or more formal programs (FPGA formal programs and DSP formal programs) or DSP formal parameters are damaged slightly, and the programming and loader are damaged seriously, so that the whole shell can be detached and can be programmed again from a JTAG bus. Therefore, it is essential to ensure that the write global data and address accuracy. The method can be realized by the following steps: formal program/formal parameter partitioning. One-time programming is only operated in the same storage block, and the existing formal programs/parameters do not need to be erased before the FLASH storage block is completely used up. The CRC frame is checked. And command frames and data frames communicated with each FPGA/DSP by the upper computer contain CRC check, so that the accuracy of frame data is ensured. And (5) testing communication. The random data communication test before programming completely simulates the programming flow and can ensure normal communication. The frame number query is transmitted. The data frame in programming is marked by the frame number, and the upper computer repeatedly sends the content of the current frame until the DSP/FPGA in programming writes the data of the frame into the FLASH and requests the next frame. And (5) frame address calculation checking. The data frame comprises a frame length with a fixed size and a frame serial number which is increased from zero, the number of a current storage block is set in advance by a command frame, the FPGA/DSP to be programmed is combined with a formal program/parameter base address and the size of the storage block to calculate a data storage address, and the programming is allowed only when the address is checked to be programmed in the currently operated storage block. The method does not need to insert an address into each frame, can improve the communication efficiency, and prevents the unstable communication from causing a frame address error and damaging other programs. And (6) reading back and checking. After all the programming contents are written into the FLASH, all the information of the programming is read out from the FLASH and transmitted back to the upper computer, and the information is compared with the original programming file in the upper computer, so that the accuracy and the integrity of the finally written contents into the FLASH are ensured.

The method for remotely programming and loading the FPGA and the DSP comprises the following three working modes, namely a program and parameter programming working mode, a program switching working mode and a program loading working mode.

Referring to fig. 4, after the signal processor is powered on, it executes a program and a parameter programming mode, and the specific process includes:

step S1.1, after power-on, each FPGA chip and/or DSP chip loads a program which is programmed in 0x0 address of each FLASH in advance through each FLASH bus (FPGA jump and programming programs stored in a plurality of continuous partitions starting from 0x0 address in each first FPGA hardware partition Sector00, DSP jump and programming programs stored in a plurality of continuous partitions starting from 0x0 address in each first DSP hardware partition Sector 00): specifically, an FPGA (FPGA chip) to be programmed correspondingly runs the FPGA skipping and programming program; and correspondingly operating the secondary loading program by the DSP to be programmed.

It is understood that the number of FPGAs to be programmed and DSPs to be programmed may be one or more.

S1.2, in a preset time range, the FPGA to be programmed and the DSP receive a control command sent by an upper computer, and when the control command is a command frame of 'start programming', the FPGA to be programmed continues to run the FPGA skip and programming program; and the DSP to be programmed runs a programming program. And waiting for the upper computer to send the data frame.

Step S1.3, calculating the address range and the effective mark address of a storage block to be programmed (comprising an FPGA formal program storage block, a DSP formal program storage block and a DSP formal parameter storage block) by the FPGA to be programmed and/or the DSP to be programmed, erasing the storage block to be programmed according to the address range and the effective mark address of the storage block to be programmed, specifically, erasing the effective mark of the storage block to be programmed firstly, and then erasing all contents (the FPGA formal program, the DSP formal program and the DSP formal parameter) stored in the storage block to be programmed. Therefore, the mismatch of the effective mark of the actual program and the effective mark of the storage block storing the actual program caused by the midway power-off can be prevented.

And S1.4, after receiving the data frame sent by the upper computer, the FPGA and/or the DSP to be programmed calculates the programming address of the data frame of the frame, judges whether the address range of the current storage block to be programmed is exceeded, if the address range of the current storage block to be programmed is exceeded, the abnormal state is uploaded to the upper computer, and data overrun is displayed, otherwise, the FPGA and/or the DSP to be programmed correspondingly programs the data frame into the current storage block to be programmed.

Specifically, step S1.4 includes: referring to fig. 5, each of the data frames includes a frame header, a frame length, a frame serial number (frame number), data, and CRC check bits.

The FPGA and/or the DSP to be programmed receives a current storage block number to be programmed sent by the upper computer, and calculates the address range and the effective mark address of the current storage block to be programmed by combining a base address (a starting address), an effective mark storage area (a second FPGA hardware partition Sector11 and a second DSP hardware partition Sector 1), an effective mark storage block (any third FPGA storage block or any fourth DSP storage block) and a formal parameter storage block (any fifth DSP storage block) of a fixed formal program or a formal parameter storage area (a third FPGA hardware partition Sector22, a third DSP hardware partition Sector2 and a fourth DSP hardware partition Sector 3), and the sizes of the formal program storage block or the FPGA formal program storage block read from the FLASH.

And calculating the data frame received by the FPGA and/or the DSP to be programmed to obtain the storage address of the current frame (data frame) according to the frame length of the data frame, the frame serial number and the initial address of the storage block to be programmed currently.

Judging whether the storage address of the current frame (data frame) exceeds the range of the current storage block address to be programmed;

if not, the data in the current data frame is programmed into the memory block to be programmed currently.

The upper computer converts the FPGA formal program to be programmed generated in the ISE software into a bin file through iMPACT software, and the bin file is segmented and encapsulated into a data frame format (the bin programming file generated by Vivado is directly segmented and encapsulated); the upper computer converts an out file of a DSP formal program obtained by compiling in CCS software into an in-bin file through TI official format conversion software hex6x.exe, b2ccs.exe, ccs2bin.exe and the like in sequence, and the out file is divided and encapsulated into a data frame format; and the bin file which is written by the formal parameters of the DSP is directly segmented and encapsulated into a data frame format by the upper computer.

And the upper computer issues the data frames to the FPGA and/or the DSP to be programmed in sequence, and the frame serial numbers are increased from zero in sequence. And the FPGA and/or the DSP to be programmed calculates a programming address (programming starts from a low address, and the programming address refers to the current frame storage address), and checks whether the programming address exceeds the address range of the current storage block to be programmed. After the FPGA and/or the DSP which are to be programmed after the data frame is checked to be programmed are programmed into a specified storage block, requesting a next frame data frame from an upper computer; otherwise, the data overrun is returned. Repeating the operation until receiving a command of programming ending sent by the upper computer.

As can be seen, this embodiment employs partitioned storage of the main program/parameter. One-time programming only operates in the same storage block, and the existing formal programs/parameters do not need to be erased before the FLASH storage block is completely used up.

The program file to be programmed comprises the following protection processes: the CRC frame is checked. And command frames and data frames communicated with each FPGA/DSP by the upper computer contain CRC check, so that the accuracy of frame data is ensured. And (5) testing communication. The random data communication test before programming completely simulates the programming flow, and can ensure normal communication. The frame number query is transmitted. The data frame in programming is marked by the frame number, the upper computer repeatedly sends the content of the current frame until the DSP/FPGA in programming writes the data of the frame into the FLASH and requests the next frame, and the frame serial numbers of the repeated frames are the same. And (5) frame address calculation checking. The data frame comprises a frame length with a fixed size and a frame serial number which is increased from zero, the number of a current storage block is set in advance by a command frame, the FPGA/DSP to be programmed combines the base address of a formal program/parameter storage area and the size of the storage block to calculate a data storage address, and the address is checked to be programmed in the currently operated storage block. The method does not need to insert an address into each frame, can improve the communication efficiency, and prevents the unstable communication from causing a frame address error and damaging other programs. And (6) reading back and checking. After all the programming contents are written into the FLASH, all the information of the programming is read out from the FLASH and transmitted back to the upper computer, and the information is compared with the original programming file in the upper computer, so that the accuracy and the integrity of the finally written contents into the FLASH are ensured.

S1.5, after the data frame of the current frame is completely programmed, the FPGA and/or the DSP to be programmed requests the upper computer for a next frame data frame, and the steps S1.2-S1.4 are repeated; until the upper computer sends out a command frame of 'programming end'.

Before the step S1.4 is executed, the method further includes: testing communication before programming: the upper computer generates and sequentially issues a plurality of data frames, and the FPGA and/or the DSP to be programmed sequentially programs the data frames into a storage block to be programmed currently; after programming is completed, the FPGA and/or the DSP to be programmed transmits all data frames stored in the storage block to be programmed back to the upper computer, and the data frames are compared with effective contents of the data frames generated by the upper computer; if the contents of the two are consistent, the comparison is passed, the memory block which needs to be programmed at present is erased again, and the step S1.4 is entered, otherwise, a communication error is displayed until a new programming command is received.

This embodiment still includes: s1.6, correspondingly reading all data (FPGA formal program, DSP formal program and DSP formal parameters) of the programming from a storage block which is currently programmed, dividing and packaging all data of the programming into data frames, transmitting the data frames back to an upper computer, after the data frames are transmitted, comparing and checking the transmitted data frames with an original programming file by the upper computer, if the data frames are consistent with the original programming file, checking the data frames to pass, setting an effective mark corresponding to the storage block which is currently programmed to be effective, and ending the programming process; otherwise, the verification fails.

Referring to fig. 6, after the signal processor is powered on, it executes a program to switch the operating mode, and the specific process includes:

step S2.1, each FPGA chip and/or DSP chip loads, through the respective FLASH bus, a program programmed in advance at the 0x0 address of the respective FLASH (the FPGA jump and programming program stored in a plurality of consecutive partitions starting from the 0x0 address in each first FPGA hardware partition Sector00, and the DSP jump and programming program stored in a plurality of consecutive partitions starting from the 0x0 address in each first DSP hardware partition Sector 0): specifically, the FPGA to be converted runs a jump and programming program, and the DSP to be converted runs a secondary loading program.

S2.2, in a preset time range, the FPGA to be converted and the DSP receive a control command sent by an upper computer, and when the control command is a command frame of 'start switching', the FPGA to be converted continues to run the FPGA jump and programming program; and the DSP to be converted continues to run the secondary loading program.

And S2.3, reading the size of the formal program storage block (DSP formal program storage block or FPGA formal program storage block) to be converted to calculate the address range and the effective sign address of the formal program storage block (DSP formal program storage block or FPGA formal program storage block) according to the received formal program storage block (DSP formal program storage block or FPGA formal program storage block) number which needs to be switched and is sent by the upper computer, combining the base address of a fixed formal program storage area (third FPGA hardware partition Sector22 or third DSP hardware partition Sector 2) and the base address of an effective sign storage area (second FPGA hardware partition Sector11 or second DSP hardware partition Sector 1) and the size of an effective sign storage block (any third FPGA storage block or any fourth DSP storage block).

And S2.4, reading the effective mark of the storage block to be switched from the corresponding first or second FLASH program memory by the FPGA to be switched and/or the DSP to be switched, judging whether the formal program (the DSP formal program or the FPGA formal program) is effective, and entering the step S2.5 if the formal program is effective, otherwise, outputting a program error.

And S2.5, erasing the default formal program storage block (DSP formal program storage block or FPGA formal program storage block) number in the corresponding first or second FLASH program storage by the FPGA to be converted and/or the DSP, programming the formal program storage block (DSP formal program storage block or FPGA formal program storage block) number to be switched, and ending the switching process. Reading an effective mark of a formal program (a DSP formal program or an FPGA formal program), switching the formal program (the DSP formal program or the FPGA formal program) only in a program switching mode, calculating an effective mark address of the formal program (the DSP formal program or the FPGA formal program) to be switched, reading the effective mark, and judging whether the formal program (the DSP formal program or the FPGA formal program) is effective or not.

Referring to fig. 7, after the signal processor is powered on, it executes a program loading working mode, and the specific process includes:

step S3.1, each FPGA chip and/or DSP chip loads, through the respective FLASH bus, a program programmed in advance at the 0x0 address of the respective FLASH (the FPGA jump and programming program stored in a plurality of consecutive partitions starting from the 0x0 address in each first FPGA hardware partition Sector00, and the DSP jump and programming program stored in a plurality of consecutive partitions starting from the 0x0 address in each first DSP hardware partition Sector 0): specifically, the FPGA to be loaded runs a jump and programming program, and the DSP to be loaded runs a secondary loading program.

And S3.2, in a preset time range, when the FPGA and/or the DSP to be loaded receive a direct start control command sent by the upper computer or any effective instruction sent by the upper computer is not received in the preset time range, the step S3.3 is carried out.

And S3.3, reading the size of the storage block in the corresponding first or second FLASH program memory by the FPGA to be loaded and/or the DSP from the fixed address in the corresponding first or second FLASH program memory to calculate the address range and the effective mark address of the storage block in combination with the base address of the fixed formal program storage area (the third FPGA hardware partition Sector22 or the third DSP hardware partition Sector 2), the base address of the effective mark storage area (the second FPGA hardware partition Sector11 and the second DSP hardware partition Sector 1) and the size of the effective mark storage block (any one of the third FPGA storage block or any one of the fourth DSP storage block).

S3.4, reading an effective mark of a formal program to be loaded by the FPGA and/or the DSP to be loaded, judging whether the formal program is effective, if so, calling an ICAPE core by the FPGA to be loaded, pointing a loading address to a first address of a storage block in which the formal program is stored, and loading the formal program into the FPGA after restarting; the DSP to be loaded reads the formal program from the storage block into a kernel for loading, and the jump from a secondary loading program to a specified formal program is realized; if the flag is invalid, returning a program error; and completing program loading.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

In summary, the present embodiment provides a method for reliably programming, loading, and switching an FPGA and a DSP with multiple formal programs. In the method, in the complete machine state of the radar seeker, all FPGA and DSP chips on a board are directly programmed, switched and selectively loaded through an original communication bus of a signal processor.

The first FLASH program memory and the second FLASH program memory are divided into areas, a plurality of formal program and formal parameter storage blocks are arranged, one-time programming is only operated in one storage block, once errors happen, the existing formal programs and parameters are not affected, fast switching and reliability improvement are facilitated, and the method is suitable for reliable upgrading in use of important equipment.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims

1. A method for remotely programming and loading an FPGA and a DSP is characterized by comprising the following steps:

the first FPGA hardware partition in the three FPGA hardware partitions is used for storing FPGA skipping and programming programs;

a first DSP hardware partition in the four DSP hardware partitions is used for storing DSP skipping and programming programs;

each DSP executes a control command sent by the upper computer, determines a DSP formal program storage block address range and an effective mark address to be programmed or a DSP formal parameter storage block address range and an effective mark address according to the control command, and correspondingly programs or DSP formal parameters into the third DSP hardware partition or the fourth DSP hardware partition;

the second FPGA hardware partition comprises a first FPGA storage block, a second FPGA storage block and a plurality of third FPGA storage blocks;

2. The method for remotely programming and loading an FPGA and a DSP according to claim 1,

after the signal processor is powered on, the signal processor executes a program and parameter programming working mode, and the program and parameter programming working mode comprises the following steps:

s1.1, correspondingly operating the FPGA skipping and programming program of the FPGA to be programmed; correspondingly operating the secondary loading program by the DSP to be programmed;

3. The method for remotely programming and loading an FPGA and a DSP as recited in claim 2,

before the step S1.4 is executed, the method further includes: testing communication before programming: the upper computer generates and sequentially issues a plurality of data frames, and the FPGA and/or the DSP to be programmed sequentially programs the data frames into a storage block to be programmed currently; after programming is finished, the FPGA and/or the DSP to be programmed transmits all data frames stored in the storage block to be programmed to the upper computer and compares the data frames with effective contents of the data frames generated by the upper computer; if the contents of the two are consistent, the comparison is passed, the current storage block to be programmed is erased again, and the step S1.4 is entered, otherwise, a communication error is displayed until a new programming command is received.

4. The method for remotely programming and loading the FPGA and the DSP as recited in claim 3, further comprising: s1.6, correspondingly reading all data to be programmed from a currently programmed storage block by the FPGA and/or the DSP, segmenting and packaging all the data to be programmed into data frames, transmitting the data frames back to an upper computer, comparing and checking the transmitted data frames with an original programming program file by the upper computer after transmission is finished, if the data frames are consistent with the original programming program file, passing the check, setting a mark corresponding to the currently programmed storage block to be valid, and ending the programming process; otherwise, the verification is failed.

5. The method for remotely programming and loading an FPGA and a DSP according to claim 4,

each of the data frames includes a frame header, a frame length, a frame serial number, data, and a CRC check bit.

6. The method for remotely programming and loading an FPGA and a DSP according to claim 1,

after the signal processor is powered on, the signal processor executes a program to switch the working mode, and the method comprises the following steps:

s2.3, reading the size of a formal program storage block to calculate the address range and the effective mark address of the formal program storage block according to the received formal program storage block number to be switched, which is sent by the upper computer, by the FPGA and/or the DSP to be converted by combining a fixed formal program, the base address of an effective mark storage area and the size of the effective mark storage block;

s2.4, the FPGA and/or the DSP to be converted reads an effective mark of a formal program storage block from a corresponding first or second FLASH program memory, judges whether the formal program is effective or not, if the formal program is effective, the step S2.5 is carried out, and if the formal program is not effective, a program error is output;

7. The method for remotely programming and loading FPGAs and DSPs of claim 1,

after the signal processor is powered on, the signal processor executes a program loading working mode, and the program loading working mode comprises the following steps:

s3.1, running a jump and programming program by the FPGA to be loaded, and running a secondary loading program by the DSP to be loaded;