CN112087637A - High-pixel bit depth video image data coding and decoding processing method - Google Patents
High-pixel bit depth video image data coding and decoding processing method Download PDFInfo
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- CN112087637A CN112087637A CN202010942440.4A CN202010942440A CN112087637A CN 112087637 A CN112087637 A CN 112087637A CN 202010942440 A CN202010942440 A CN 202010942440A CN 112087637 A CN112087637 A CN 112087637A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/65—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience
- H04N19/68—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience involving the insertion of resynchronisation markers into the bitstream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/184—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
- H04N19/88—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving rearrangement of data among different coding units, e.g. shuffling, interleaving, scrambling or permutation of pixel data or permutation of transform coefficient data among different blocks
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Abstract
The invention discloses a high pixel bit depth video image data coding and decoding processing method, and belongs to the field of image processing. Collecting high bit depth video image data; splitting high bit depth video image data into multiple paths; synchronously encoding and decoding multi-channel video image data; and (4) recombining high bit depth video image data. The invention can effectively realize the high bit depth video image coding and decoding processing and ensure the high restoration of the video information.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to a high-pixel bit depth video image data coding and decoding processing method.
Background
The video image coding and decoding technology is a key technology in the technical field of multimedia video at present, and the most common H.264/H.265 video coding and decoding standard at present is designed for the YUV format video image coding and decoding. In the YUV video format standard, the Y, U, V components are 8-bit pixel depth, i.e. the h.264/h.265 codec cannot perform codec processing on images with pixel depth exceeding 8-bit.
Disclosure of Invention
The invention aims to provide a high pixel bit depth video image data coding and decoding processing method to solve the problem that the current H.264/H.265 video coding and decoding standard can not carry out coding and decoding processing on the more than 8bit pixel bit depth video image.
In order to solve the above technical problem, the present invention provides a method for encoding and decoding high pixel bit depth video image data, comprising:
collecting high bit depth video image data;
splitting high bit depth video image data into multiple paths;
synchronously encoding and decoding multi-channel video image data;
and (4) recombining high bit depth video image data.
Optionally, the high bit depth video image data is collected through an FPGA.
Optionally, the FPGA splits the gray value of each pixel in the acquired video image into multiple paths of 8-bit values.
Optionally, in the splitting process, the part with less than 8 bits is supplemented by a high bit fill 0 mode to become an 8bit depth video image.
Optionally, before the synchronous encoding processing of the multiple paths of video image data, the encoding and decoding processing method for high pixel bit depth video image data further includes: .
Optionally, each path of video image data is marked with a frame number.
Optionally, the marking the frame number of each path of video image data includes:
and writing a frame number in the front n BYTE positions of each frame of video image data structure, wherein the range of n is 1-32.
Alternatively to this, the first and second parts may,
firstly, the video coding and decoding chip respectively preprocesses each path of video image data;
the video coding and decoding chip respectively carries out coding processing on each path of video image data to obtain video coding data;
and the video coding and decoding chip writes the frame sequence number marks into the tail n BYTE positions of each frame of video coding data in sequence, and writes the marked video coding data into a storage medium in sequence to be stored in a file form.
Optionally, the pre-processing comprises: reading out the frame serial number mark in each frame of video image data and storing the frame serial number mark in an array queue.
Optionally, the name of the file written in the storage medium is named by the channel number and time.
Optionally, the synchronous decoding processing of the multiple paths of video image data includes: the video coding and decoding chip retrieves and reads out a plurality of paths of video coding data files belonging to the same source video from the storage medium, carries out synchronous decoding processing by taking the frame number mark as a synchronous characteristic, and sends the decoded video image data to the FPGA for recombination.
Optionally, the FPGA performs data reassembly frame by frame according to a data splitting rule according to the channel number and the frame number.
In the high pixel bit depth video image data coding and decoding processing method provided by the invention, high bit depth video image data is collected; splitting high bit depth video image data into multiple paths; synchronously encoding and decoding multi-channel video image data; and (4) recombining high bit depth video image data. The invention can effectively realize the high bit depth video image coding and decoding processing and ensure the high restoration of the video information.
Drawings
FIG. 1 is a flow chart of a high pixel bit depth video image data encoding and decoding processing method according to the present invention;
FIG. 2 is a high bit depth video image splitting schematic;
FIG. 3 is a schematic diagram of a 8-bit deep video data frame number marker;
FIG. 4 is a schematic diagram of video coding data frame number marking.
Detailed Description
The following describes a method for encoding and decoding high pixel bit depth video image data according to the present invention in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a high pixel bit depth video image data coding and decoding processing method, the flow of which is shown in figure 1, and the method comprises the following steps:
step S11, collecting high bit depth video image data;
step S12, splitting high bit depth video image data into multiple paths;
step S13, synchronously encoding and decoding the multi-channel video image data;
and step S14, recombining the high bit depth video image data.
The high bit depth video image data are collected through the FPGA, the FPGA divides the gray value of each pixel in the collected video image into a plurality of paths of 8-bit numerical values, and the part with less than 8 bits in the dividing process is supplemented into the 8-bit depth video image in a high bit filling 0 mode. Fig. 2 is a schematic diagram of splitting 14-bit pixel bit depth image data into two 8-bit depth video image channels. In fig. 2, the FPGA first takes out the high 8-bit data in the 14-bit depth image data as 8-bit depth image data (i.e., VideoChanel _ 0), and then takes out the low 6-bit data and adds data 0 of 2 bits to the high bit of bit5 to compose another 8-bit depth image data (i.e., VideoChanel _ 1).
Before sending the split multi-path 8-bit video image data to a video coding and decoding chip, the FPGA needs to mark the frame number of each path of 8-bit image, wherein the frame number mark is a frame number written in n BYTE positions in front of the 8-bit video image data structure of each path, and the range of n is 1-32; in the first embodiment, n is 16, as shown in fig. 3.
And the multi-path 8-bit depth video image data is synchronously sent to a video coding and decoding chip for coding processing. Firstly, the video coding and decoding chip respectively preprocesses each path of 8-bit depth video image data, namely reading out the frame number marks in each frame of image and storing the marks in an array queue; and then, the video coding and decoding chip respectively carries out coding processing on each path of 8-bit depth video data to obtain video coding data. Finally, the video codec chip writes the frame number marks in the array queue into the 16 BYTE position at the tail of each frame of video coded data in sequence, as shown in fig. 4. The marked video coded data can be written into the storage medium in sequence and stored in the form of a file, and the file name can be named by channel number and time, such as videochannel _0_20200810110327, videochannel _1_20200810110327, and the like.
When decoding, the video coding and decoding chip retrieves and reads out a multi-channel 8-bit depth video coding data file belonging to the same source video from the storage medium, synchronous decoding processing is carried out by taking the frame number mark as a synchronous characteristic, and the decoded video image data is sent to the FPGA for recombination.
And after receiving the decoded video image data, the FPGA carries out data recombination frame by frame according to a data splitting rule according to the channel number and the frame number.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (11)
1. A high pixel bit depth video image data coding and decoding processing method is characterized by comprising the following steps:
collecting high bit depth video image data;
splitting high bit depth video image data into multiple paths;
synchronously encoding and decoding multi-channel video image data;
and (4) recombining high bit depth video image data.
2. The method according to claim 1, wherein the high bit depth video image data is captured by an FPGA.
3. The method as claimed in claim 2, wherein the FPGA splits the gray level value of each pixel in the acquired video image into multiple 8-bit values.
4. The method as claimed in claim 3, wherein during the splitting process, less than 8bit is supplemented into 8bit depth video image by high bit fill 0.
5. The method of claim 1, wherein before the step of encoding and decoding the multiple video image data synchronously, the method further comprises:
and marking the frame number of each path of video image data.
6. The method as claimed in claim 5, wherein the frame number marking of each video image data path comprises:
and writing a frame number in the front n BYTE positions of each frame of video image data structure, wherein the range of n is 1-32.
7. The method as claimed in claim 1, wherein the video codec chip performs synchronous encoding on multiple paths of video image data, and comprises:
firstly, the video coding and decoding chip respectively preprocesses each path of video image data;
the video coding and decoding chip respectively carries out coding processing on each path of video image data to obtain video coding data;
and the video coding and decoding chip writes the frame sequence number marks into the tail n BYTE positions of each frame of video coding data in sequence, and writes the marked video coding data into a storage medium in sequence to be stored in a file form.
8. The method of claim 7, wherein the pre-processing comprises: reading out the frame serial number mark in each frame of video image data and storing the frame serial number mark in an array queue.
9. The method of claim 7, wherein the names of the files written in the storage medium are named by channel number and time.
10. The method of claim 9, wherein the synchronously decoding the multiple video image data comprises: the video coding and decoding chip retrieves and reads out a plurality of paths of video coding data files belonging to the same source video from the storage medium, carries out synchronous decoding processing by taking the frame number mark as a synchronous characteristic, and sends the decoded video image data to the FPGA for recombination.
11. The method according to claim 10, wherein the FPGA reassembles the data frame by frame according to the channel number and the frame number and the data splitting rule.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114173189A (en) * | 2021-10-29 | 2022-03-11 | 荣耀终端有限公司 | Video editing method and electronic equipment |
| CN114222187A (en) * | 2021-08-12 | 2022-03-22 | 荣耀终端有限公司 | Video editing method and electronic equipment |
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| CN109600618A (en) * | 2018-12-19 | 2019-04-09 | 上海数迹智能科技有限公司 | Video-frequency compression method, decompression method, device, terminal and medium |
| WO2020141260A1 (en) * | 2019-01-02 | 2020-07-09 | Nokia Technologies Oy | An apparatus, a method and a computer program for video coding and decoding |
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| CN106791858A (en) * | 2017-01-09 | 2017-05-31 | 国家新闻出版广电总局电影数字节目管理中心 | A kind of high sampling rate rgb video data lossless compression method |
| CN109600618A (en) * | 2018-12-19 | 2019-04-09 | 上海数迹智能科技有限公司 | Video-frequency compression method, decompression method, device, terminal and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114222187A (en) * | 2021-08-12 | 2022-03-22 | 荣耀终端有限公司 | Video editing method and electronic equipment |
| CN114222187B (en) * | 2021-08-12 | 2023-08-29 | 荣耀终端有限公司 | Video editing method and electronic equipment |
| CN114173189A (en) * | 2021-10-29 | 2022-03-11 | 荣耀终端有限公司 | Video editing method and electronic equipment |
| EP4224870A4 (en) * | 2021-10-29 | 2024-05-22 | Honor Device Co., Ltd. | Video editing method and electronic device |
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