CN112087358A

CN112087358A - CPCI-based multi-channel CAN bus communication universal module implementation method

Info

Publication number: CN112087358A
Application number: CN202010940354.XA
Authority: CN
Inventors: 王青松; 所玉君; 崔建飞
Original assignee: Tianjin Jinhang Computing Technology Research Institute
Current assignee: Tianjin Jinhang Computing Technology Research Institute
Priority date: 2020-09-09
Filing date: 2020-09-09
Publication date: 2020-12-15
Anticipated expiration: 2040-09-09
Also published as: CN112087358B

Abstract

The invention relates to a method for realizing a CPCI-based multi-channel CAN bus communication universal module, belonging to the technical field of CAN bus communication. In the invention, the DSP processor combines chip selection signals through an integrated SPI interface to complete the configuration and data interaction of 20 CAN controllers; the dual-port memory is accessed through the EMIF interface, a dual-port communication protocol is designed, the main device accesses the dual-port RAM through the CPCI bus to communicate with the module, and finally the configuration and communication functions of the 20-channel CAN node are achieved. The invention can greatly save hardware resources, is suitable for various processor platforms with CPCI interfaces, can configure and close channels on line, has good universality and portability, and has higher popularization and application values.

Description

CPCI-based multi-channel CAN bus communication universal module implementation method

Technical Field

The invention belongs to the technical field of CAN bus communication, and particularly relates to a method for realizing a CPCI-based multi-channel CAN bus communication universal module.

Background

The CAN bus is a serial multi-master controller local area network bus which is easy to establish and high in cost performance. The CAN bus communication adopts a message broadcast transmission mode, and has a perfect error detection mechanism and fault-tolerant processing capability. Due to their high performance, high reliability, unique design and modest price, are widely used in the automotive industry, the aerospace industry, industrial control, and medical devices, and have been recognized as one of several of the most promising field buses.

In practical application, there are many architectural methods for implementing the CAN communication function, including using a CAN communication module integrated in a DSP chip, using an architecture of a DSP + CAN controller, and using an architecture of a DSP + FPGA + CAN controller, but there are mainly the following three problems:

1. the DSP processor is limited in application requiring a plurality of CAN bus interfaces due to the limited number of CAN bus interfaces that the DSP processor CAN provide; in the method disclosed at present, the number of CAN channels expanded by using the architecture of the DSP + CAN controller and the architecture of the DSP + FPGA + CAN controller is less, and the method is not enough to meet the requirement of testing a plurality of CAN bus channels.

2. The CAN bus interface of industrial control practical application is mainly hung on a local bus of a host, and provides a CAN bus communication function for a single-type host.

3. At present, corresponding CAN communication modules are mainly developed aiming at specific application, the specific parameter settings such as transmission baud rate, acceptance filtering, acceptance shielding and the like are all set and fixed in advance by software, communication function software needs to be frequently modified when different CAN bus tests are faced, and the universality and the transportability are poor.

In order to solve the above three problems, a multi-channel CAN bus communication module is realized, the requirements of various platforms such as PowerPC, X86, DSP, ARM and the like on CAN bus interface communication are met, differences among processor platforms are shielded, and a universal module which has a multi-processor platform access capability and CAN realize a multi-channel configurable CAN bus communication function is urgently needed.

Disclosure of Invention

Technical problem to be solved

The technical problem to be solved by the invention is as follows: how to design a general module which has the access capability of a multiprocessor platform and CAN realize the communication function of a multi-channel configurable CAN bus.

(II) technical scheme

In order to solve the technical problem, the invention provides a realization method of a CPCI-based multi-channel CAN bus communication general module, wherein the module is integrally used as a CPCI slave device and CAN communicate with an external CPCI master device through a dual-port memory;

wherein, the DSP processor selects TMS320f28377S processor chip of TI company; the CAN controller adopts MCP2515 of Microchip company;

the DSP processor completes configuration and data interaction of 20 CAN controllers through SPIA and SPIB interfaces and chip selection signals, and realizes the communication function of 20 paths of CAN buses; meanwhile, the DSP processor puts the received data into the dual-port memory through the EMIF interface, and by designing a dual-port communication protocol, the CPCI master device CAN access the dual-port memory through the CPCI bus to communicate with the module, so that the configuration and communication functions of 20 paths of CAN bus nodes are realized;

in the SPIA and SPIB interfaces integrated by the DSP processor, each interface is connected with 10 SPI slave device CAN controllers, wherein, the CPCI master device output line, the CPCI master device input line and the serial clock line of the SPIA interface are respectively connected with the CPCI slave device input line, the CPCI slave device output line and the serial clock line of the first 10 CAN controllers MCP2515, the general purpose input and output GPIOs 0-9 of the DSP processor are configured into output modes and are respectively connected with the chip selection ends of the first 10 MCPs 2515, the CPCI master device output line, the CPCI master device input line and the serial clock line of the SPIB interface are respectively connected with the CPCI slave device input line, the CPCI slave device output line and the serial clock line of the last 10 MCPs 2515, the general purpose input and output ports GPIO 55-64 of the DSP processor are configured into output modules and are respectively connected with the chip selection ends of the last 10 MCPs 2515, and each MCP2515 device is independently operated and used by outputting a control chip selection signal through the GPIO to complete the function of CAN bus communication with 20 channels independently configured.

Preferably, the DSP accesses an external double-port memory through the EMIF interface, CAN put received data on the CAN bus into the double-port memory, and CAN also take out a message to be sent, which is put into the double-port memory by the CPCI master device, to send CAN bus data; the DSP processor is connected with signals corresponding to the dual-port memory by using EM1A 0-EM 1A19 address buses, EM1D 0-EM 1D15 data buses, EM1CS2 chip selection enabling signals, EM1OE reading enabling signals and EM1WE writing enabling signals, and the 64K 16bit space addressing function is achieved.

Preferably, the module as a whole is used as a CPCI slave device, and when the module communicates with a CPCI master device through a dual-port memory, the CPCI master device accesses the dual-port memory through a base address and an offset to perform data exchange.

Preferably, the dual-port memory is designed for word access, the dual-port memory is divided into a data area and a command area, the data area comprises a data receiving buffer area and a data sending buffer area, the data receiving buffer area is written by the DSP processor and read by the CPCI main equipment, the data sending buffer area is written by the CPCI main equipment, the DSP processor reads, and in order to adapt to the characteristic of byte transmission of the CAN, the content of the data area is effective with 8 bits lower; the command area comprises 7 areas including a receiving area writing offset, a sending area writing offset, a module power-on completion identifier, a module power-on self-test result, a DeviceID, a version number and control instructions of 1-20 CAN channels, and 16-bit contents are all effective.

Preferably, the two data areas of the receiving data buffer area and the sending data buffer area both adopt a design mode of a ring buffer area, and each data area CAN buffer 512 CAN messages; each message occupies a storage space with a fixed length, and the starting and stopping storage positions of the CAN messages are guaranteed to be fixed when the number of turns is different.

Preferably, the write offset of the received data buffer is written by the module, and the CPCI host device is read only; the write offset of the sending data buffer area is written by the CPCI main equipment, and the module is read only; after the module is electrified and completes self-checking and initialization operation, fixed content is written into an electrified and completed identification area, and the CPCI main equipment can know whether the module is electrified and completed or not through the identification; if the module is electrified, writing a self-checking result into the module, wherein the self-checking result comprises a checking result of the double-port memory and a checking result of the 20-channel CAN channel; DeviceID and version number are respectively the equipment number and the version number of software; the control instruction of the CAN channel comprises initialization operation and channel closing operation of the 20 CAN channels, wherein the initialization parameters comprise a working mode, a baud rate, an acceptance filter ID and an acceptance mask ID.

Preferably, the overall design of the dual-port memory is as shown in table 1 below:

TABLE 1

Preferably, wherein the CAN message design is as shown in table 2 below:

TABLE 2

Offset address	Variable names	Value taking	Definition of
				0x0	FrameFormat	0 — standard frame mode; 1-extended frame mode
0x1	RTR	0-data frame; 1-remote frame
				0x2	DataLenCode	0-8	Data length code
0x3～0x6	ID[4]	11 bits-standard frame, 29 bits-extended frame	Target node ID
				0x7～0xE	Data[8]	Data content	Data area
0xF	Channel	0-19 (corresponding to lanes 1 to 20 of CAN)	Data channel number
				。。。	。。。	。。。	。。。
0x1F	Retention	Retention	Retention

Preferably, the CAN control command generic format is as follows in table 3:

TABLE 3

Address	0xA**0	0xA**1	0xA**2	0xA**3
					Data of	Cmd:0xC1/0xCC	FrameFormat	LocalIDH	LocalIDL
Address	0xA**4	0xA**5	0xA**6	0xA**7
					Data of	LocalIDMaskH	LocalIDMaskL	BaudIndex	Mode
Address	0xA**8	0xA**9	0xA**A	0xA**B
					Data of	Retention	Retention	Retention	Retention
Address	0xA**C	0xA**D	0xA**E	0xA**F
					Data of	Retention	Retention	Retention	Retention

In table 3 above, after the module receives the initialization command 0xC1, the CAN controller is automatically initialized according to the given parameters, and after the initialization command is completed, the unit value of 0xA × 0 is rewritten to 0x 0; when the module receives an initialization command 0xC1, the corresponding CAN channel is closed, after the completion, the unit value of 0xA x0 is rewritten into 0x0, and the host acquires the current operation state by inquiring the unit value.

The invention also provides a channel CAN bus communication universal module designed by the method.

(III) advantageous effects

In the invention, the DSP processor combines chip selection signals through an integrated SPI interface to complete the configuration and data interaction of 20 CAN controllers; the dual-port memory is accessed through the EMIF interface, a dual-port communication protocol is designed, the main device accesses the dual-port RAM through the CPCI bus to communicate with the module, and finally the configuration and communication functions of the 20-channel CAN node are achieved. The invention can greatly save hardware resources, is suitable for various processor platforms with CPCI interfaces, can configure and close channels on line, has good universality and portability, and has higher popularization and application values.

Drawings

FIG. 1 is a block diagram of a method for implementing a CPCI-based multi-channel CAN bus general module according to the present invention;

FIG. 2 is a topology diagram of a CAN bus in the implementation method of the multi-channel CAN bus universal module based on CPCI of the present invention;

FIG. 3 is a block software flow chart of a method for implementing a CPCI-based multi-channel CAN bus universal module according to the present invention;

fig. 4 is a flowchart of the host operation in the method for implementing a CPCI-based multi-channel CAN bus universal module according to the present invention.

Detailed Description

In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

Aiming at the problems of the prior CAN communication module, the invention designs a universal module which has the access capability of a multiprocessor platform and CAN realize the multi-channel and configurable CAN bus communication function.

Referring to fig. 1, fig. 2, fig. 3, and fig. 4, the method for implementing a multi-channel CAN bus communication general module based on CPCI provided in the present invention specifically includes:

as shown in fig. 1, in the method for implementing a CPCI-based multi-channel CAN bus communication general module according to the present invention, the module as a whole is used as a CPCI slave device and communicates with an external CPCI master device through a dual-port memory, and the module is designed as a hardware component including 1 DSP processor, 1 dual-port memory, 20 CAN controllers, a CAN transceiver, and a corresponding optoelectronic isolation module.

The DSP processor of the embodiment adopts TMS320f28377S processor chip of TI company, the processor has dominant frequency of 200MHz, integrates SPIA, SPIB, SPIC interface and EMIF interface, has multiple GPIO pins, and can fully meet the functional requirements of the module; the CAN controller selects MCP2515 of Microchip company, the device is an independent CAN protocol controller with an SPI interface, the CAN controller completely supports CAN V2.0B technical specifications, CAN send and receive standard and extended data frames and remote frames, and is provided with two acceptance shielding registers and six acceptance filtering registers, so that the expense of a host MCU CAN be reduced. The CAN transceiver selects Philips TJA1050, and the device adopts SOI technology, CAN effectively reduce electromagnetic radiation, has transient protection and thermal protection functions, and has strong anti-electromagnetic interference capability. And the receiving and transmitting channels of CAN communication adopt an HCPL0631 high-speed optical coupler isolator for signal isolation, and the electromagnetic interference between CAN bus nodes is eliminated. IDT70V9289 of IDT company is selected for use to the double port memory, and memory capacity is 64K 16bit, satisfies the user demand of this module.

The DSP processor is used as a core controller of the module, and the configuration and data interaction of 20 CAN controllers are completed through SPIA and SPIB interfaces and chip selection signals, so that the communication function of 20 paths of CAN buses is realized; meanwhile, the DSP processor puts the received data into the dual-port memory through the EMIF interface, and through designing a reasonable dual-port communication protocol, the CPCI master device CAN access the dual-port memory through the CPCI bus to communicate with the module (CAN module), so that the configuration and communication functions of 20 paths of CAN bus nodes are realized.

Fig. 2 shows a 10-node dual redundancy topology. In actual use, the method CAN be used in different bus topological structures according to requirements, and CAN be used for single-node CAN module communication with 10-channel dual redundancy function; the CAN bus CAN also be used for single-node CAN module communication in different CAN buses with 20 channels; the CAN bus is also used as 20 CAN nodes in a 1-channel CAN bus for simulating a CAN network to test some equipment.

The DSP processor accesses an external double-port memory through the EMIF interface, CAN put received data on the CAN bus into the double-port memory, and CAN also take out a message to be sent, which is put into the double-port memory by the CPCI main equipment, so as to send CAN bus data. The DSP processor is connected with signals corresponding to the dual-port memory by using EM1A 0-EM 1A19 address buses, EM1D 0-EM 1D15 data buses, EM1CS2 chip selection enabling signals, EM1OE reading enabling signals and EM1WE writing enabling signals, and the 64K 16bit space addressing function is achieved.

The module is integrally used as a CPCI slave device, and when the module communicates with a CPCI main device through a dual-port memory, the CPCI main device accesses the dual-port memory to exchange data through a base address + offset mode. Through proper double-port memory design and DSP processor driving program, the CAN module function of multi-channel, multi-platform and universal configuration is realized, different industrial requirements are met, and the good compatibility is suitable for various system configurations.

The double-port memory is accessed by words, the double-port memory is divided into a data area and a command area, the data area comprises a data receiving buffer area and a data sending buffer area, the data receiving buffer area is written by the DSP processor and read by the CPCI main equipment, the data sending buffer area is written by the CPCI main equipment, the DSP processor reads, and in order to adapt to the characteristic that the CAN is transmitted by bytes, the content of the data area is effective by 8 bits; the command area comprises 7 areas including a receiving area writing offset, a sending area writing offset, a module power-on completion identifier, a module power-on self-test result, a DeviceID, a version number and control instructions of 1-20 CAN channels, and 16-bit content is fully effective.

The two data areas of the receiving data buffer area and the sending data buffer area adopt a design mode of a ring buffer area, and each data area CAN buffer 512 CAN messages, so that data coverage or packet loss caused by processing delay is avoided; each message occupies a storage space with a fixed length, the starting and stopping storage positions of the CAN messages are guaranteed to be fixed when the number of turns is different, the complexity is reduced, and the reliability is improved.

The write offset of the received data buffer area is written by the module, and the CPCI main equipment is read only; the write offset of the sending data buffer area is written by the CPCI main equipment, and the module is read only; after the module is electrified and completes self-checking and initialization operation, fixed content is written into an electrified and completed identification area, and the CPCI main equipment can know whether the module is electrified and completed or not through the identification; if the module is electrified, writing a self-checking result into the module, wherein the self-checking result comprises a checking result of the double-port memory and a checking result of the 20-channel CAN channel; DeviceID and version number are respectively the equipment number and the version number of software; the control instruction of the CAN channel comprises initialization operation and channel closing operation of the 20 CAN channels, wherein the initialization parameters comprise a working mode, a baud rate, an acceptance filter ID, an acceptance mask ID and the like.

The overall design of the dual-port memory is shown in the following table 1:

TABLE 1

The CAN message design is shown in table 2 below:

TABLE 2

The general format of the CAN control commands is as follows in Table 3:

TABLE 3

The data corresponding to the operating mode of the MCP2515 is as follows in table 4:

TABLE 4

Data of

Default

0

1

2

3

4

Mode of operation

Is normal

Go back to

Listening only

Sleep mode

Configuration of

The baud rate numbers correspond to the transmission rates as shown in table 5 below:

TABLE 5

Numbering	Default	1	2	3	4	5	6	7	8
										Communication rate	1M	20K	50K	100K	125K	200K	250K	500K	1M

With the above design content, the power-on process at the module DSP processor end is as shown in fig. 3, after the software of the power-on DSP processor is started, the initialization operation of each interface of the system is first performed, then the power-on detection is performed on the dual-port memory and the 20-way MCP2515, after the check is completed, information such as DeviceID, the software version number, the self-detection result, and the like is written into the dual-port memory, then the CAN control commands of each channel are polled and executed, data reception and transmission are performed on the initialized channels, and communication is performed with the CPCI master device through the dual-port memory.

The using process of the CPCI master device end is as shown in fig. 4, after the CPCI master device completes self-initialization, the version and the self-checking information of the CAN module are inquired, the channel which is successfully self-checked is configured and used according to the requirement, and the functions of initialization configuration, data receiving and sending, channel closing and the like of the CAN channel are realized through interaction with the dual-port memory of the module.

Through the above example, the design implementation of the CPCI-based 20-channel CAN bus communication universal module is completed, and nothing described in the present invention is applicable to the prior art.

It CAN be seen that the invention utilizes the SPI interface integrated by DSP to control 20 CAN controller slave devices, and only uses the single board module to realize the CAN bus communication function of 20 channels, thus saving a great deal of hardware resources and cost. The module is used as standard CPCI bus slave equipment, CAN provide reliable and uniform CAN bus access function for a multi-type processor platform, and has good compatibility of the application mode. By designing a universal double-port RAM protocol and a universal driving program, 20 CAN channels CAN be configured on line in real time, the requirements of different application occasions CAN be met, and the universality and the transportability are good.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. A realization method of a CPCI-based multi-channel CAN bus communication general module is characterized in that the module is integrally used as a CPCI slave device and CAN communicate with an external CPCI master device through a dual-port memory, and in the method, the module is designed to comprise 1 DSP processor, 1 dual-port memory and 20 CAN controllers;

2. The method of claim 1, wherein the DSP processor accesses the external dual-port memory through the EMIF interface, and CAN put the received data on the CAN bus into the dual-port memory, and CAN also take out the message to be sent, which is put into the dual-port memory by the CPCI master device, to send the CAN bus data; the DSP processor is connected with signals corresponding to the dual-port memory by using EM1A 0-EM 1A19 address buses, EM1D 0-EM 1D15 data buses, EM1CS2 chip selection enabling signals, EM1OE reading enabling signals and EM1WE writing enabling signals, and the 64K 16bit space addressing function is achieved.

3. The method of claim 2, wherein the module as a whole is a CPCI slave device, and when communicating with the CPCI master device through the dual port memory, the CPCI master device accesses the dual port memory for data exchange in the form of a base address and an offset.

4. The method of claim 3, wherein the dual port memory is designed for word access, the dual port memory is divided into two areas, a data area and a command area, the data area comprises two areas, a receive data buffer area and a transmit data buffer area, the receive data buffer area is written by the DSP processor and read by the CPCI host device, the transmit data buffer area is written by the CPCI host device and read by the DSP processor, and the data area is valid with 8-bit lower content in order to adapt to the characteristics of CAN transmission in bytes; the command area comprises 7 areas including a receiving area writing offset, a sending area writing offset, a module power-on completion identifier, a module power-on self-test result, a DeviceID, a version number and control instructions of 1-20 CAN channels, and 16-bit contents are all effective.

5. The method of claim 4, wherein the two data areas of the receiving data buffer and the sending data buffer are designed as ring buffers, and each data area CAN buffer 512 CAN messages; each message occupies a storage space with a fixed length, and the starting and stopping storage positions of the CAN messages are guaranteed to be fixed when the number of turns is different.

6. The method of claim 5, wherein the receive data buffer write offset is written by the local module, the CPCI host device is read-only; the write offset of the sending data buffer area is written by the CPCI main equipment, and the module is read only; after the module is electrified and completes self-checking and initialization operation, fixed content is written into an electrified and completed identification area, and the CPCI main equipment can know whether the module is electrified and completed or not through the identification; if the module is electrified, writing a self-checking result into the module, wherein the self-checking result comprises a checking result of the double-port memory and a checking result of the 20-channel CAN channel; DeviceID and version number are respectively the equipment number and the version number of software; the control instruction of the CAN channel comprises initialization operation and channel closing operation of the 20 CAN channels, wherein the initialization parameters comprise a working mode, a baud rate, an acceptance filter ID and an acceptance mask ID.

7. The method of claim 6, wherein the overall design of the dual port memory is as shown in table 1 below:

TABLE 1

8. The method of claim 7, wherein the CAN message design is as shown in table 2 below:

TABLE 2

Offset address Variable names Value taking Definition of 0x0 FrameFormat 0 — standard frame mode; 1-extended frame mode 0x1 RTR 0-data frame; 1-remote frame 0x2 DataLenCode 0-8 Data length code 0x3～0x6 ID[4] 11 bits-standard frame, 29 bits-extended frame Target node ID 0x7～0xE Data[8] Data content Data area 0xF Channel 0-19 (corresponding to lanes 1 to 20 of CAN) Data channel number 。。。。。。。。。。。。 0x1F Retention Retention Retention

9. The method of claim 8 wherein the CAN control command generic format is as follows in table 3:

TABLE 3

In table 3 above, after the module receives the initialization command 0xC1, the CAN controller is automatically initialized according to the given parameters, and after the initialization command is completed, the unit value of 0xA × 0 is rewritten to 0x 0; when the module receives an initialization command 0xC1, the module closes the corresponding CAN channel, and after completion, rewrites the unit value of 0xA × 0 to 0x0, and the CPCI master device acquires the current operating state by querying the unit value.

10. A channel CAN-bus communication generic module designed with the method according to any of claims 1 to 9.