CN112087276B - Clock calibration method and device - Google Patents
Clock calibration method and device Download PDFInfo
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- CN112087276B CN112087276B CN201910518154.2A CN201910518154A CN112087276B CN 112087276 B CN112087276 B CN 112087276B CN 201910518154 A CN201910518154 A CN 201910518154A CN 112087276 B CN112087276 B CN 112087276B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
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Abstract
The application discloses a clock calibration method and a clock calibration device, wherein the method comprises the steps of receiving a standard second pulse signal; obtaining a first local second pulse signal; acquiring a first phase difference between a first local second pulse signal and a standard second pulse signal; and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering an interference signal in the standard second pulse signal by using the threshold value for filtering the phase difference. Through the mode, the method and the device can automatically adjust the threshold value of the filtering phase difference for filtering the interference signals, reduce the influence of the interference signals and improve the stability of the local clock.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for clock calibration.
Background
The time reference of the communication system is derived from GNSS (Global Navigation Satellite System ), and satellite signals are easily interfered by weather, shielding objects or electromagnetic fields, and these interference can cause the standard second pulse signal output by the GNSS chip to be unstable, so in order to obtain a stable time reference, the communication system needs to eliminate the interference of the standard second pulse to obtain better performance. The inventor of the present application has found in long-term research and development that, in general, a mode of setting a threshold is adopted to eliminate interference, that is, a second pulse normally input to a system is considered to be periodic, the second pulse can occur in a preset time, a normal signal appears in a threshold range of a standard time, otherwise, the second pulse is considered to be an interference signal, and the interference signal is filtered; however, since the threshold for filtering the interference signal is fixed, the threshold must be relatively large in order to adapt to all application environments, so that part of the interference signal cannot be filtered, thereby resulting in reduced performance of the clock system; in addition, when the external second pulse is fixedly changed to another position and the phase difference exceeds a threshold value, the external second pulse is filtered as an interference signal.
Disclosure of Invention
The application mainly solves the problem of providing a clock calibration method and device, which can automatically adjust the threshold value for filtering interference signals, reduce the influence of the interference signals and improve the stability of a local clock.
In order to solve the technical problems, the technical scheme adopted by the application is to provide a clock calibration method, which comprises the following steps: receiving a standard second pulse signal; obtaining a first local second pulse signal; acquiring a first phase difference between a first local second pulse signal and a standard second pulse signal; and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering an interference signal in the standard second pulse signal by using the threshold value.
In order to solve the above technical problems, another technical solution adopted by the present application is to provide a clock calibration device, which at least includes: the phase detector is coupled with the clock source and the local clock generation circuit, one end of the processor is coupled with the phase detector, the other end of the processor is coupled with one end of the local clock generation circuit, the phase detector and the processor form negative feedback, the clock source is used for outputting a standard second pulse signal, the local clock generation circuit is used for obtaining a first local second pulse signal, the phase detector is used for receiving the standard second pulse signal and the first local second pulse signal, and obtaining a first phase difference between the first local second pulse signal and the standard second pulse signal, and the processor is used for obtaining a threshold value for filtering the phase difference according to the first phase difference and filtering an interference signal in the standard second pulse signal by utilizing the threshold value for filtering the phase difference.
Through the scheme, the application has the beneficial effects that: firstly, receiving a standard second pulse signal and a first clock signal, multiplying the frequency of the first clock signal by a phase-locked loop, generating a second clock signal, and then counting the second clock signal to generate a first local second pulse signal; then, a first phase difference between the first local second pulse signal and the standard second pulse signal is obtained; the threshold value of the filtered phase difference is obtained by utilizing the first phase difference, and interference signals mixed in the standard second pulse signals are filtered by utilizing the threshold value of the filtered phase difference, so that the threshold value of the filtered interference signals can be automatically adjusted, and when the standard second pulse input from the outside is stable, a small threshold value is generated, and a better filtering effect is achieved; meanwhile, when the standard second pulse input from the outside is stably switched to another phase, the new phase can be locked again, so that the interference filtering effect is improved, the function of locking the standard second pulse is ensured, the frequency change of the local clock is reduced, and the stability of the local clock is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a timing diagram of a prior art signal for filtering interference;
FIG. 2 is a timing diagram of another prior art signal for filtering interference;
FIG. 3 is a flow chart of an embodiment of a method for clock calibration according to the present application;
FIG. 4 is a flow chart of another embodiment of a method for clock calibration provided by the present application;
FIG. 5 is a flow chart of another embodiment of a method for clock calibration provided by the present application;
FIG. 6 is a timing diagram of signals in yet another embodiment of a method for clock calibration provided by the present application;
FIG. 7 is a schematic diagram showing a state transition of a phase threshold in a method of clock calibration according to another embodiment of the present application;
FIG. 8 is a schematic diagram of a phase difference in another embodiment of a method for clock calibration provided by the present application;
FIG. 9 is a schematic diagram of an embodiment of a clock calibration device according to the present application;
fig. 10 is a schematic structural diagram of another embodiment of the clock calibration device provided by the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The current solution for filtering the interference signal mainly has two modes, namely, one is to generate a window second pulse, as shown in fig. 1, if the GPS second pulse is not located in the window second pulse, the GPS second pulse is considered as the interference signal, the filtering range is the pulse outside the window in practice, and if the interference signal is in the window second pulse, the filtering can not be realized; the other is to use a counter to eliminate interference, for example, it uses a counting pulse with frequency of 2MHz to count the period of GPS second pulse, and the normal interval between two standard GPS second pulses is 2×10 6 As shown in fig. 2, the occurrence of the second pulse within the preset threshold value range is normal, and the occurrence of the second pulse outside the threshold value range is interference, for example: the preset threshold is 20 clock cycles of counting pulses, and the interval between the two pulses is [2×10 ] 6 -20，2×10 6 +20]All belonging to normal signals in a single clock cycle, if two pulse per second intervals of 2 x 10 are monitored 6 +30 clock cycles, the normal range is exceeded and the jammer signal is considered.
Both the two methods are to filter the interference signals by using a fixed threshold value method, and in order to realize the stability of the filtering function, the threshold value is usually set to be relatively large, so that the interference signals in the threshold value range cannot be filtered, and the filtering effect is not good enough.
Referring to fig. 3, fig. 3 is a flowchart of a method for clock calibration according to an embodiment of the present application, where the method includes:
step 31: a standard second pulse signal is received.
To achieve clock calibration, a standard second pulse signal needs to be received first.
Step 32: a first local second pulse signal is obtained.
The first clock signal may be generated using an oscillator, which may be a thermostatic crystal oscillator; then the phase-locked loop can be utilized to multiply the frequency of the first clock signal, and count the second clock signal after generating the second clock signal so as to generate a first local second pulse signal with the period of 1 second; for example: the period of the first clock signal is 100ns, and the period is generated by using a phase-locked loopA second clock signal of 10ns, counting the number of periods of the second clock signal, and counting 100 x 10 per received 6 After the second clock signal, a first local second pulse signal is generated.
Step 33: a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal is obtained.
In order to track the standard second pulse signal by the local clock signal, so that the phase of the first local second pulse signal is consistent with the phase of the standard second pulse signal, a first phase difference between the first local second pulse signal and the standard second pulse signal needs to be acquired, and the first phase difference is reduced by adjusting the phase of the first local second pulse signal, so that the local clock signal follows the standard second pulse signal.
Step 34: and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering an interference signal in the standard second pulse signal by using the threshold value for filtering the phase difference.
Since satellite signals are susceptible to interference, the phase of the standard second pulse signal may be suddenly changed, and in order to prevent the local clock from tracking the wrong input signal, the wrong input signal needs to be filtered, i.e. the interference signal needs to be filtered.
After a first phase difference between the first local pulse signal and the standard pulse signal is obtained, determining a threshold value for filtering the phase difference by utilizing the first phase difference so as to filter interference signals in the obtained standard pulse signal and avoid the interference signals from affecting the local pulse signal.
Compared with the prior art, the embodiment provides a clock calibration method, which is characterized in that a standard second pulse signal and a first clock signal are received, the first clock signal is multiplied by a phase-locked loop to generate a second clock signal, and then the second clock signal is counted to generate a first local second pulse signal; then, a first phase difference between the first local second pulse signal and the standard second pulse signal is obtained; the threshold value of the filtered phase difference is obtained by utilizing the first phase difference, and interference signals mixed in the standard second pulse signals are filtered by utilizing the threshold value of the filtered phase difference, so that the threshold value of the filtered phase difference for filtering the interference signals can be automatically adjusted, and when the standard second pulse input from the outside is stable, a small threshold value of the filtered phase difference is generated, and a better filtering effect is achieved; meanwhile, when the standard second pulse input from the outside is stably switched to another phase, the new phase can be locked again, so that the interference filtering effect is improved, the function of locking the standard second pulse is ensured, the frequency change of the local clock is reduced, and the stability of the local clock is improved.
Referring to fig. 4, fig. 4 is a flowchart of another embodiment of a clock calibration method according to the present application, where the method includes:
step 41: a standard second pulse signal is received.
The standard second pulse signal is a pulse signal generated by a global navigation satellite system or a precision clock synchronization protocol (Precision Timing Protocol, PTP).
Step 42: a first local second pulse signal is obtained.
Step 43: a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal is obtained.
Steps 41 to 43 are the same as steps 31 to 33 in the above embodiment, and will not be described here again.
Step 44: and comparing each first phase difference in the preset period with a preset phase difference threshold value.
After the first phase difference between the first local second pulse signal and the standard second pulse signal is obtained, in order to obtain a threshold value for filtering the filtered phase difference of the interference signal included in the standard second pulse signal, each first phase difference in a preset period can be compared with a preset phase difference threshold value, wherein the preset phase difference threshold value is a threshold value for presetting a first filtered phase difference, the threshold value of the first filtered phase difference is also a threshold value of a maximum filtered phase difference, the preset phase difference threshold value can be infinite, and specific data can be used for representing infinity.
Step 45: after the system is powered on, the threshold value of the filtered phase difference defaults to a preset threshold value of a first filtered phase difference; when all the first phase differences in the preset period are smaller than the threshold value of the preset second filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset second filtering phase difference; and when all the first phase differences in the preset period are smaller than the threshold value of the preset third filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset third filtering phase difference.
When all the first phase differences are smaller than the preset second filtering phase difference threshold value in the preset period, the current preset first filtering phase difference threshold value is larger, and in order to filter interference signals, the preset first filtering phase difference threshold value needs to be reduced to the preset second filtering phase difference threshold value; if all the first phase differences in the preset period are smaller than the threshold value of the preset third filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset third filtering phase difference; wherein the threshold value of the first filtered phase difference is greater than the threshold value of the second filtered phase difference, which is greater than the threshold value of the third filtered phase difference; and directly filtering when all the first phase differences in the preset period are larger than a threshold value of the preset first filtering phase difference.
Step 46: and filtering the interference signal in the standard second pulse signal by using a threshold value for filtering the phase difference.
After determining the threshold value of the current filtered phase difference, the threshold value of the filtered phase difference can be used for filtering the interference signals in the standard second pulse signals, and signals outside the threshold value of the filtered phase difference are used as the interference signals for filtering.
Step 47: and processing the first phase difference after filtering the interference signals to obtain a second local second pulse signal, so that the second phase difference between the second local second pulse signal and the standard second pulse signal is smaller than the first phase difference.
After the interference signal is filtered, in order to realize the following of the standard second pulse signal by the first local second pulse signal, the first phase difference after the interference signal is filtered can be processed, and the frequency or the phase of the first local second pulse signal is adjusted to be changed into the second local second pulse signal, so that the second phase difference between the second local second pulse signal and the standard second pulse signal is smaller than the first phase difference.
The steps can be repeatedly executed to reduce the phase difference between the local pulse-per-second signal and the standard pulse-per-second signal, so that the phase difference between the local pulse-per-second signal and the standard pulse-per-second signal is close to 0, and the aim of following the standard pulse-per-second signal is fulfilled.
Compared with the prior art, the clock calibration method provided by the application has the advantages that the first phase difference between the first local second pulse signal and the standard second pulse signal is obtained, each first phase difference in the preset period is compared with the preset phase difference threshold value, when all the first phase differences in the preset period are larger than the preset phase difference threshold value, filtering is directly carried out, when the first phase difference is smaller than the preset phase difference threshold value, the threshold value of the filtered phase difference of the filtered interference signal is reduced, the threshold value of the filtered phase difference can be automatically adjusted according to the current first phase difference, the threshold value of the filtered phase difference is not directly set as a constant value, the threshold value can be amplified to infinity through the amplifying threshold value, when the phase mutation of the standard second pulse signal and the phase difference between the standard second pulse signal and the first local second pulse signal exceed the filtered phase difference threshold value, the standard second pulse signal or the first local second pulse signal can not be filtered as the interference signal, the influence of the interference signal is reduced, and the stability of the local clock is improved.
Referring to fig. 5, fig. 5 is a flowchart of a clock calibration method according to another embodiment of the present application, where the method includes:
step 51: a standard second pulse signal is received.
Step 52: a first clock signal output by the oscillator is received.
Steps 51 to 52 are the same as steps 31 to 32 in the above embodiment, and will not be described here again.
Step 53: and multiplying the frequency of the first clock signal output by the oscillator, and counting the multiplied first clock signal to generate a first local second pulse signal.
Multiplying the frequency of the first clock signal output by the oscillator, and counting the number of the received first clock signals after frequency multiplication, wherein the number of the first clock signals after frequency multiplication is equal to the number of the first clock signals after frequency multiplicationGenerating a first local second pulse signal after receiving the first clock signal in a period; for example: the frequency of the first clock signal output by the oscillator is 1MHz, then 1×10 6 A first local second pulse signal is generated after a clock period as shown in fig. 6.
Step 54: a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal is obtained.
Step 55: and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering an interference signal in the standard second pulse signal by using the threshold value for filtering the phase difference.
Steps 54 to 55 are the same as steps 33 to 34 in the above embodiment, and will not be described here again.
Step 56: the first phase difference is processed using a clock calibration algorithm to obtain a digital signal and the digital signal is converted to an analog signal.
After the first phase difference is obtained, the first phase difference may be processed using a clock calibration algorithm (e.g., PID algorithm, proportion Integral Differential, proportional-integral-derivative), the first phase difference is converted to a digital signal, and the digital signal is converted to an analog signal.
Step 57: the oscillator is caused to output a first clock signal using the analog signal.
The analog signal may be a voltage signal, and the generated voltage may be used to adjust an oscillation frequency of the oscillator such that the oscillator outputs the first clock signal.
Step 58: the first clock signal is multiplied to generate a second clock signal.
Step 59: the second clock signal is counted to generate a second local second pulse signal.
After the first clock signal is acquired, frequency multiplication is carried out on the first clock signal so as to generate a second clock signal, and then the second clock signal is counted to acquire a second local second pulse signal with the period of 1 second; the second phase difference between the second local second pulse signal and the standard second pulse signal is smaller than the first phase difference, so that the local second pulse signal follows the standard second pulse signal.
Further, the threshold value of the default filtering phase difference is the maximum value after power is on, the threshold value of the filtering phase difference is unchanged before clock locking, and the threshold value of the filtering phase difference is adjusted after clock locking; firstly, calculating the maximum value and the minimum value of a plurality of first phase differences between a first local pulse signal and a standard pulse signal in preset time, and judging whether to modify the phase difference threshold according to the threshold of the current filtered phase difference and the maximum value and the minimum value of the current first phase difference.
And (3) recording the signal with the phase difference between the standard pulse per second signal and the signal with the phase difference larger than the modified phase difference threshold value as a useless signal, and recording the signal with the phase difference between the standard pulse per second signal and the signal with the phase difference smaller than the modified phase difference threshold value as a useful signal, so as to filter the interference signal.
The following specifically describes the change in the phase difference threshold, assuming that there are three phase difference thresholds: the states corresponding to the first phase difference threshold, the second phase difference threshold and the third phase difference threshold are respectively represented by State1, state2 and State3, and the automatic adjustment of the phase difference threshold is realized through State jump, as shown in fig. 7.
(1) After the clock is locked, the clock enters a first phase difference threshold, namely a maximum phase difference allowable range, and at the moment, the threshold of the filtered phase difference is also the maximum value (the threshold of the preset first filtered phase difference).
When all the first phase differences are smaller than the second phase difference threshold value within the preset time, the first phase difference between the first local second pulse signal and the standard second pulse signal is considered to be reduced, the State2 corresponding to the second phase difference threshold value is needed to be jumped, the threshold value of the filtered phase difference is reduced, and the threshold value of the filtered phase difference is set as the threshold value of the preset second filtered phase difference.
If all the first phase differences are smaller than the third phase difference threshold value within the preset time, jumping to a State3 corresponding to the third phase difference threshold value, reducing the threshold value of the filtered phase difference to be lower, and setting the threshold value of the filtered phase difference to be the threshold value of the preset third filtered phase difference.
If at least one first phase difference is larger than the second phase difference threshold and smaller than the first phase difference threshold, the state corresponding to the first phase difference threshold is kept unchanged, namely the threshold of the filtered phase difference is a preset threshold of the first filtered phase difference.
(2) When in State2 corresponding to the second phase difference threshold
If all the first phase differences within the preset time are larger than the second phase difference threshold, namely the phase differences within the preset time are all filtered, the first phase differences are considered to be increased, and the State1 corresponding to the first phase difference threshold is skipped.
If all the first phase differences are smaller than the third phase difference threshold value within the preset time, jumping to a State3 corresponding to the third phase difference threshold value, and further reducing the threshold value of the filtered phase difference to be the threshold value of the third filtered phase difference.
If at least one first phase difference is larger than the third phase difference threshold and smaller than the second phase difference threshold, the State2 corresponding to the second phase difference threshold is kept unchanged, namely the threshold of the filtered phase difference is a preset threshold of the second filtered phase difference.
(3) When in State3 corresponding to the third phase difference threshold
If all the first phase differences within the preset time are larger than the third phase difference threshold, namely the phase differences within the preset time are all filtered, the first phase differences are considered to be increased, the State2 corresponding to the second phase difference threshold is jumped, and the threshold of the filtered phase differences is set as the threshold of the preset second filtered phase differences.
If all the first phase differences within the preset time are larger than the second phase difference threshold, jumping to a State1 corresponding to the first phase difference threshold, and setting the threshold of the filtered phase difference as the threshold of the preset first filtered phase difference.
If at least one first phase difference is smaller than the third phase difference threshold, the State3 corresponding to the third phase difference threshold is kept unchanged, namely the threshold of the filtered phase difference is a preset threshold of the third filtered phase difference.
If the first phase difference is smaller and smaller, the local clock well tracks the standard clock, the phase difference threshold value is reduced, the threshold value of the filtered phase difference is reduced, and signals larger than the threshold value of the filtered phase difference are regarded as interference signals and are filtered; if the first phase difference is larger and larger, the phase difference threshold value is larger, and the threshold value for filtering the phase difference is larger; therefore, the threshold value of the filtered phase difference which is more fit to the actual environment can be generated according to the first phase difference data of the actual local pulse-second signal and the standard pulse-second signal.
In the following process of the first local pulse per second signal to the standard pulse per second signal, the three states may be continuously converted, and the threshold value of the current filtering phase difference can be continuously adjusted according to the current first phase difference, so that the threshold value of the filtering phase difference can be automatically adjusted, and the effect of filtering interference signals is improved.
For example, as shown in fig. 8, the power-up is started at the 0 th second, the threshold value of the default phase difference is at the maximum, and after M seconds, the clock is locked, and the State1 corresponding to the first phase difference threshold value is entered.
At the end of the first N seconds, all the first phase differences are smaller than the second phase difference threshold Diff2, so that the State2 corresponding to the second phase difference threshold is skipped.
At the end of the second N seconds, since all the first phase differences are larger than the second phase difference threshold Diff2, the State rises to the State1 corresponding to the first phase difference threshold.
At the end of the third N seconds, since all the first phase differences are smaller than the second phase difference threshold Diff2, the State falls to State2 corresponding to the second phase difference threshold.
At the end of the last fourth N seconds, since all the first phase differences are smaller than the third phase difference threshold Diff3, the State falls to State3 corresponding to the third phase difference threshold.
As can be seen from the above, although the same judgment value Diff2 is used for the mutual jump between two adjacent states (e.g. State2 and State 1), one condition is that all the first phase differences are larger than the second phase difference threshold Diff2 in the preset time, and the other condition is that all the first phase differences are smaller than the second phase difference threshold Diff2 in the preset time, and the two conditions are different, so that different states can be distinguished, and the threshold of the filtering phase difference is changed.
In summary, if the current State is in State2 corresponding to the second phase difference threshold, and the threshold for filtering the phase difference is to be kept unchanged, at least one first phase difference must fall between the phase difference thresholds [ Diff1, diff2] within a preset time; if the phase difference threshold is to be reduced to a third phase difference threshold Diff3, all the first phase differences within the preset time are smaller than the third phase difference threshold Diff3; if the phase difference threshold is to be increased to the first phase difference threshold Diff1, all the first phase differences within the preset time are larger than the second phase difference threshold Diff2.
Compared with the prior art, the application provides a clock calibration method, which is characterized in that a first phase difference between a first local second pulse signal and a standard second pulse signal is obtained, a threshold value of a filtering phase difference is adjusted according to the relation between the first phase difference and a preset phase difference, the threshold value of the filtering phase difference for filtering interference signals can be automatically adjusted, the influence of the interference signals is reduced, then the first phase difference is processed by using a clock calibration algorithm to obtain a digital signal, the digital signal is converted into an analog signal, then an oscillator is controlled by the analog signal to output a second clock signal to generate a second local second pulse signal, and the second phase difference between the regenerated second local second pulse signal and the standard second pulse signal is smaller than the first phase difference, so that the aim of locking the standard second pulse is fulfilled.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a clock calibration device according to the present application; the clock calibration means comprises at least a clock source 91, a local clock generation circuit 92, a phase detector 93 and a processor 94.
The phase detector 93 is coupled to the clock source 91 and the local clock generation circuit 92, one end of the processor 94 is coupled to the phase detector 93, the other end of the processor 94 is coupled to one end of the local clock generation circuit 92, and the local clock generation circuit 92, the phase detector 93, and the processor 94 form a negative feedback.
The clock source 91 is configured to output a standard second pulse signal, the local clock generating circuit 92 is configured to obtain a first local second pulse signal, the phase discriminator 93 is configured to receive the standard second pulse signal and the first local second pulse signal, obtain a first phase difference between the first local second pulse signal and the standard second pulse signal, and the processor 94 is configured to obtain a threshold value for filtering the phase difference according to the first phase difference, and filter an interference signal in the standard second pulse signal by using the threshold value for filtering the phase difference.
Compared with the prior art, the application provides a clock calibration device, which obtains a first phase difference between a standard second pulse signal output by a clock source 91 and a first local second pulse signal output by a local clock generation circuit 92 through a phase discriminator 93, and adjusts a threshold value of a filtering phase difference according to the first phase difference through a processor 94, so that the threshold value of the filtering phase difference of a filtering interference signal is automatically adjusted, the influence of the interference signal is reduced, and meanwhile, the processor 94 is utilized to control the local clock generation circuit 102, so that the first local second pulse output by the local clock generation circuit 102 locks the clock source 91, and the stability of a local clock is improved.
Referring to fig. 10, fig. 10 is a schematic structural diagram of another embodiment of a clock calibration device according to the present application; the clock calibration device comprises at least a clock source 101, a local clock generation circuit 102, a phase detector 103 and a processor 104.
The clock source 101 is a global navigation satellite system or a precision clock synchronization protocol, and is used for outputting a standard second pulse signal; the local clock generation circuit 102 includes a frequency doubling and counting circuit 1021 and an oscillator 1022 connected to each other.
The frequency doubling and counting circuit 1021 is a local clock source, and is configured to receive the first clock signal output by the oscillator 1022, generate a higher frequency clock by frequency doubling, and then generate a first local second pulse signal by counting, and output the first local second pulse signal to the phase detector 103.
The phase detector 103 is coupled to the clock source 101 and the frequency doubling and counting circuit 1021, and is configured to receive the standard second pulse signal and the first local second pulse signal, and obtain a first phase difference between the first local second pulse signal and the standard second pulse signal.
The processor 104 includes at least: the adjustment filter circuit 1041, the adjuster 1042, the digital-to-analog converter 1043, and the clock status report circuit 1044.
The adjusting and filtering circuit 1041 is coupled to the phase detector 103, and is configured to obtain a threshold value of a filtered phase difference according to the first phase difference, and filter an interference signal in the standard second pulse signal by using the threshold value of the filtered phase difference; the adjusting and filtering circuit 1041 is further configured to compare the first phase difference in the preset period with a preset phase difference threshold, and after the system is powered on, the threshold of the filtered phase difference defaults to the threshold of the preset first filtered phase difference; when all the first phase differences in the preset period are smaller than the threshold value of the preset second filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset second filtering phase difference; when all the first phase differences in the preset period are smaller than the threshold value of the preset third filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset third filtering phase difference; and determining whether to adjust the threshold value and to which threshold value according to the numerical intervals of all the first phase differences in the preset period. Wherein the threshold value of the first filtered phase difference is greater than the threshold value of the second filtered phase difference, which is greater than the threshold value of the third filtered phase difference.
The clock status reporting circuit 1044 is coupled to the adjustment filter circuit 1041, and configured to upload the status of whether the clock is locked and the first phase difference to a central processing unit (not shown).
The regulator 1042 is coupled to a regulation filter circuit 1041 for processing the first phase difference to obtain a digital signal using a clock calibration algorithm, and the regulator 1042 can be a PID controller.
One end of the digital-to-analog converter 1043 is coupled to the regulator 1042, and is used for converting the digital signal transmitted by the regulator 1042 into an analog signal.
The other end of the digital-to-analog converter 1043 is coupled to the oscillator 1022, the oscillator 1022 is configured to generate a first clock signal according to the analog signal, and send the first clock signal to the frequency doubling and counting circuit 1021, where the oscillator 1022 may be a voltage-controlled oscillator; specifically, the oscillator 1022 may be a constant temperature crystal oscillator, and the frequency of the first clock signal may be 10MHz.
The frequency multiplication and counting circuit 1021 is connected to the phase detector 103, and is configured to multiply the first clock signal output by the oscillator 1022, and count the received first clock signal after frequency multiplication, so as to generate a first local second pulse signal.
The processor 104 adjusts the frequency of the first clock signal output from the oscillator 1022 using the first phase difference output from the phase detector 103, specifically, the processor 104 outputs different voltage signals according to the different first phase differences, thereby controlling the frequency of the first clock signal output from the oscillator 1022; when the first phase difference output by the phase detector 103 is non-zero, the processor 104 adjusts the frequency of the output first clock signal, thereby adjusting the phase of the first local second pulse signal output by the frequency doubling and counting circuit 1021, so that the phase difference between the adjusted first local second pulse signal output by the frequency doubling and counting circuit 1021 and the standard second pulse signal output by the clock source 101 is reduced.
The phase discriminator 103, the adjusting filter circuit 1041, the adjuster 1042, the digital-to-analog converter 1043 and the frequency doubling and counting circuit 1021 form negative feedback; when the frequency of the clock signal output by the oscillator 1022 is greater than the standard frequency value, the phase discriminator 103 compares the first phase difference between the standard second pulse signal output by the clock source 101 and the first local second pulse signal output by the frequency doubling and counting circuit 1021, then determines a threshold value of the filtered phase difference by using the adjusting and filtering circuit 1041, filters the interference signal by using the threshold value of the filtered phase difference, then inputs the first phase difference to the regulator 1042 to be processed into a digital signal, and the regulator 1042 transmits the digital signal to the digital-to-analog converter 1043, so that the analog signal output by the digital-to-analog converter 1043 is reduced, and the output frequency of the oscillator 1022 is reduced to approach the standard value.
For example, assuming that the frequency output by the oscillator 1022 is 10mhz+10hz, which is slightly greater than the preset value (10 MHz), by comparing the phases of the first local second pulse signal and the standard second pulse signal to obtain the phase advanced standard second pulse signal of the first local second pulse signal, and then reducing the value of the output digital signal by the PID regulator, the voltage output by the digital-to-analog converter 1043 is correspondingly reduced, so that the frequency output by the oscillator 1022 is correspondingly reduced, and the frequency is reduced to 10mhz+5hz, thereby reducing the first phase difference between the first local second pulse signal and the standard second pulse signal, and repeating this procedure, that is, the frequency output by the oscillator 1022 is made to approach 10MHz.
On the contrary, if the frequency output by the oscillator 1022 is 10MHz-10Hz, which is smaller than the preset value, the phase of the local second pulse signal is obtained by comparing the first local second pulse signal with the standard second pulse signal, and the phase of the local second pulse signal is lagging behind the phase of the standard second pulse signal, and the digital signal output by the digital-to-analog converter 1043 is increased by using the PID regulator, so that the frequency output by the oscillator 1022 is increased correspondingly, and the frequency is increased to 10MHz-5Hz, so that the first phase difference between the first local second pulse signal and the standard second pulse signal is reduced, and the process is repeated, thus obtaining a local accurate 10M clock and providing an accurate clock for the communication system. .
Compared with the prior art, the application provides a clock calibration device, the phase difference between a clock source 101 and a frequency doubling and counting circuit 1021 is obtained through a phase discriminator 103, the threshold value of the filtering phase difference for filtering interference signals is automatically adjusted by utilizing an adjusting and filtering circuit 1041, the influence of the interference signals is reduced, then the voltage input into an oscillator 1022 is adjusted through a regulator 1042 and a digital-to-analog converter 1043, the output frequency of the oscillator 1022 is changed, the phase difference between the frequency doubling and counting circuit 1021 output local second pulse phase is changed, the phase difference between the local second pulse signal and a standard second pulse signal is reduced, the local second pulse signal is locked, and finally the accurate and stable local clock is obtained.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing is only illustrative of the present application and is not to be construed as limiting the scope of the application, and all equivalent structures or equivalent flow modifications which may be made by the teachings of the present application and the accompanying drawings or which may be directly or indirectly employed in other related art are within the scope of the application.
Claims (9)
1. A method of clock calibration, comprising:
receiving a standard second pulse signal;
obtaining a first local second pulse signal;
acquiring a first phase difference between the first local pulse per second signal and the standard pulse per second signal;
acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering an interference signal in the standard second pulse signal by utilizing the threshold value for filtering the phase difference;
and processing the first phase difference after filtering the interference signal to obtain a second local second pulse signal, so that a second phase difference between the second local second pulse signal and the standard second pulse signal is smaller than the first phase difference.
2. The method of clock calibration according to claim 1, wherein the step of obtaining a threshold value for a filtered phase difference from the first phase difference comprises:
after the system is powered on, the threshold value of the filtered phase difference defaults to a preset threshold value of a first filtered phase difference;
when all the first phase differences in the preset period are smaller than the threshold value of the preset second filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset second filtering phase difference;
when all the first phase differences in the preset period are smaller than a preset third phase difference filtering threshold value, setting the phase difference filtering threshold value as a preset third phase difference filtering threshold value;
the threshold value of the first filtering phase difference is larger than the threshold value of the second filtering phase difference, the threshold value of the second filtering phase difference is larger than the threshold value of the third filtering phase difference, and the standard second pulse signal is a pulse signal generated by a global navigation satellite system or a precise clock synchronization protocol.
3. The method of clock calibration according to claim 1, wherein the step of processing the first phase difference after filtering the interference signal to obtain a second local second pulse signal such that a second phase difference between the second local second pulse signal and the standard second pulse signal is smaller than the first phase difference, comprises:
processing the first phase difference by using a clock calibration algorithm to obtain a digital signal, and converting the digital signal into an analog signal;
using the analog signal to enable the oscillator to output a first clock signal;
multiplying the first clock signal to generate a second clock signal;
the second clock signal is counted to generate the second local second pulse signal.
4. The method of clock calibration of claim 1, wherein the step of obtaining a first local second pulse signal comprises:
and multiplying the frequency of the first clock signal output by the oscillator, and counting the multiplied first clock signal to generate the first local second pulse signal.
5. The clock calibration device is characterized by at least comprising a clock source, a phase detector, a local clock generation circuit and a processor, wherein the phase detector is coupled with the clock source and the local clock generation circuit, one end of the processor is coupled with the phase detector, the other end of the processor is coupled with one end of the local clock generation circuit, the phase detector and the processor form negative feedback, the clock source is used for outputting a standard second pulse signal, the local clock generation circuit is used for obtaining a first local second pulse signal, the phase detector is used for receiving the standard second pulse signal and the first local second pulse signal, and acquiring a first phase difference between the first local second pulse signal and the standard second pulse signal, and the processor is used for acquiring a threshold value of a filtering phase difference according to the first phase difference and filtering an interference signal in the standard second pulse signal by utilizing the threshold value of the filtering phase difference; the processor is further configured to process the first phase difference after filtering the interference signal to obtain a digital signal, and convert the digital signal into an analog signal, and control the local clock generating circuit to output a second clock signal by using the analog signal to generate a second local second pulse signal, where a second phase difference between the second local second pulse signal and the standard second pulse signal is smaller than the first phase difference.
6. The clock calibration device of claim 5, wherein,
the clock source is a global navigation satellite system or a precision clock synchronization protocol.
7. The clock calibration device of claim 5, wherein the local clock generation circuit comprises an interconnected oscillator and frequency doubling and counting circuit, the processor comprising at least: the adjusting filter circuit, the regulator, the digital-to-analog converter and the clock state reporting circuit,
the adjusting and filtering circuit is coupled with the phase discriminator and is used for acquiring a threshold value of a filtering phase difference according to the first phase difference and filtering an interference signal in the standard second pulse signal by utilizing the threshold value of the filtering phase difference; the clock state reporting circuit is coupled with the adjusting and filtering circuit and is used for uploading the first phase difference to the central processing unit; the regulator is coupled with the regulation filter circuit and is used for processing the first phase difference by using a clock calibration algorithm to obtain a digital signal; one end of the digital-to-analog converter is coupled with the regulator and is used for converting the digital signal sent by the regulator into an analog signal; one end of the oscillator is coupled with the digital-to-analog converter, and the oscillator is used for generating a first clock signal according to the analog signal and sending the first clock signal to the frequency multiplication and counting circuit; the frequency multiplication and counting circuit is connected with the phase discriminator and is used for multiplying the frequency of the first clock signal output by the oscillator and counting the frequency-multiplied first clock signal to generate the first local second pulse signal.
8. The clock calibration device of claim 7, wherein,
after the system is powered on, the threshold value of the filtered phase difference defaults to a preset threshold value of a first filtered phase difference; when all the first phase differences in the preset period are smaller than the threshold value of the preset second filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset second filtering phase difference; when all the first phase differences in the preset period are smaller than a preset third phase difference filtering threshold value, setting the phase difference filtering threshold value as a preset third phase difference filtering threshold value; wherein the threshold value of the first filtered phase difference is greater than the threshold value of the second filtered phase difference, which is greater than the threshold value of the third filtered phase difference.
9. The clock calibration device of claim 7, wherein,
the oscillator is a constant temperature crystal oscillator, and the frequency of the first clock signal is 10MHz.
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| CN115202182B (en) * | 2022-07-07 | 2023-08-08 | 深圳市金科泰通信设备有限公司 | Second pulse signal output method, circuit and chip |
| CN117979412B (en) * | 2024-03-29 | 2024-07-19 | 江铃汽车股份有限公司 | Internal time synchronization method and system for vehicle-mounted communication remote terminal |
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