CN112071974A - Three-dimensional integrated system and preparation method - Google Patents
Three-dimensional integrated system and preparation method Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/87—Electrodes or interconnections, e.g. leads or terminals
- H10N30/875—Further connection or lead arrangements, e.g. flexible wiring boards, terminal pins
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/32—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from a charging set comprising a non-electric prime mover rotating at constant speed
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
- H02N2/00—Electric machines in general using piezoelectric effect, electrostriction or magnetostriction
- H02N2/18—Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
- H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
- H10N30/077—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by liquid phase deposition
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/30—Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors
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- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a three-dimensional integrated system and a preparation method thereof, wherein the integrated system comprises a nano generator, a nano capacitor structure, a first silicon through hole structure and a second silicon through hole structure; the method comprises the following steps: selecting an etching substrate, etching a plurality of silicon nano holes on the surface of the etching substrate, and preparing to obtain a nano capacitor structure; preparing a nano generator with a common electrode on the surface of the nano capacitor structure; processing two sides of the top of the nano generator to obtain a first silicon through hole structure and a second silicon through hole structure; and metal wiring is carried out in the first silicon through hole structure and the second silicon through hole structure, the nano capacitor structure is connected with the nano generator in a conduction mode to obtain a final integrated system, electric energy generated by the piezoelectric generator is stored in the nano capacitor structure to obtain continuous and stable energy output, and the whole system is easy to shrink in size and small in occupied area.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a three-dimensional integrated system and a preparation method thereof.
Background
Besides leading to the miniaturization technology development route of devices by moore's law, the functionalized micro-nano devices are integrated to form a multifunctional micro-nano device system, and large-scale networks in the aspects of human health, environmental monitoring, human-computer interaction, personal electronics, biological diagnosis and the like are realized, and the importance of the system is increasingly prominent. The integration of embedded energy harvesting devices to form intelligent self-powered systems is an important aspect of the development of electronic devices, which can convert environmental energy sources such as thermal energy, solar energy, mechanical energy, and the like into electrical energy. The nano generator has a better prospect in self-power supply, can drive an LCD (liquid crystal display), light an LED (light emitting diode) and the like, and further supplies power to portable electronic products such as mobile phones and the like.
However, nanogenerators rely on energy sources that are not continuously available in the environment. Therefore, there is a need for an energy storage device that can provide peak loads, yet an energy generating device cannot provide, to maintain uninterrupted operation of the device. Generally, the energy storage device is either a battery or a capacitor. However, batteries are generally separate energy supply components and are difficult to integrate directly with other devices. Furthermore, another disadvantage of the battery is its limited discharge efficiency. In contrast, a capacitor may provide a larger discharge current. Other advantages of using a capacitor as an energy storage include longer cycle life and higher power density. In addition to the advantages mentioned above, capacitors are easier to scale down than batteries using appropriate materials and structural designs.
Therefore, there is a need to provide a novel three-dimensional integrated system and a method for manufacturing the same to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a three-dimensional integrated system and a preparation method thereof, which can store electric energy generated by a piezoelectric generator in a nano capacitor structure to obtain continuous and stable energy output.
In order to achieve the above object, the three-dimensional integrated system of the present invention includes a nanogenerator, a nanocapacitor structure, a first through-silicon-via structure, and a second through-silicon-via structure;
the nanometer capacitor structure is installed the nanometer generator bottom, first through-silicon via structure with the second through-silicon via structure sets up respectively the top left and right sides of nanometer generator, the nanometer generator with pass through between the nanometer capacitor structure first through-silicon via structure, the integration of second through-silicon via structure is in the same place and electric connection, makes the electric energy that the nanometer generator will produce is stored inside the nanometer capacitor structure, just the nanometer capacitor structure with an electrode is shared to the nanometer generator.
The invention has the beneficial effects that: through being in the same place nanometer generator and nanometer capacitor structure integration, not only reduced whole volume size, be favorable to the system area to reduce and the improvement of integrated level, the electric energy storage that produces the nanometer generator moreover can obtain lasting stable energy output among the nanometer capacitor structure, and first through-silicon via structure and second through-silicon via structure distribute in the local region in both sides of nanometer generator simultaneously, can not exert an influence to the electricity generation work of nanometer generator.
Furthermore, the nano capacitor structure comprises an etching substrate, a plurality of silicon nano holes are formed in the etching substrate, a first isolation medium, a first bottom metal electrode layer, a first insulation medium and a first top metal electrode layer are sequentially arranged on the surface of the etching substrate and the surface of each silicon nano hole from bottom to top, and the insides of the silicon nano holes are completely filled. The beneficial effects are that: the first isolation medium isolates the etched substrate from the first bottom metal electrode layer, and the first bottom metal electrode layer and the first top metal electrode layer are isolated in an insulating mode through the first insulation medium, so that the nano capacitor structure is not prone to interference influence during working, and the nano capacitor structure is stable in working.
Further, the nano-generator comprises a second insulating medium layer and a second top metal electrode layer, a second isolation medium is arranged on the outer wall of the second top metal electrode layer, the second isolation medium further covers the surface of the first top metal electrode layer, the first top metal electrode layer and the second top metal electrode layer are respectively used as two electrodes of the nano-generator, ports are arranged at two ends of the second isolation medium, and polycrystalline silicon is arranged on the ports. The beneficial effects are that: the nanometer generator is arranged at the top of the nanometer capacitor structure, and the nanometer generator and the nanometer capacitor structure share one electrode, so that the nanometer generator and the nanometer capacitor structure are integrated together, the system volume is reduced, and the system integration level is improved.
Furthermore, the first through silicon via structure penetrates through the polysilicon and contacts with the first top metal electrode layer, the second through silicon via structure penetrates through the polysilicon, the second isolation medium, the first top metal electrode layer and the first insulation medium and contacts with the first bottom metal electrode layer, and third isolation media are arranged on the side walls, the upper surface and the upper surface of the first through silicon via structure and the second through silicon via structure. The beneficial effects are that: through first through-silicon via structure and the second through-silicon via structure that distributes in nanometer generator top both sides, with integrated being in the same place between nanometer capacitor structure and the nanometer generator, when having improved the integration of system, because first through-silicon via structure and second through-silicon via structure all distribute in the local area of nanometer generator top both sides, the influence that produces the electricity generation work of nanometer generator is less, guarantees nanometer generator's normal operating.
Furthermore, a groove structure is further arranged inside the third isolation medium, the groove structure is arranged adjacent to the second through silicon via structure, and the groove structure is separated from the first through silicon via structure by the third isolation medium. The beneficial effects are that: the first silicon through hole structure and the second silicon through hole structure are separated through the groove structure and the third isolation medium, and mutual influence is avoided.
Furthermore, the surfaces of the first silicon through hole structure, the second silicon through hole structure and the groove structure are all provided with a copper diffusion barrier layer, the copper diffusion barrier layer electrically connects the first bottom metal electrode layer with the second top metal electrode layer, the surface of the copper diffusion barrier layer is provided with a copper seed crystal layer, the surface of the copper seed crystal layer is provided with a copper metal layer, and the interiors of the first silicon through hole structure, the second silicon through hole structure and the groove structure are completely filled with a structure consisting of the copper diffusion barrier layer, the copper seed crystal layer and the copper metal layer. The beneficial effects are that: through the material layers deposited in the first silicon through hole structure and the second silicon through hole structure, electric energy collected in the nano capacitor structure can be transmitted to the outside, and a good conduction effect is achieved.
Further, the height of the third isolation medium between the trench structure and the first through silicon via structure is the same as the height of the copper metal layer. The beneficial effects are that: the surface of the whole integrated system is smooth, and the nano generator can conveniently generate electricity.
Furthermore, a first metal contact bump is arranged at the top of the first silicon through hole structure, a second metal contact bump is arranged at the top of the second silicon through hole structure, the first metal contact bump is conducted with the first top metal electrode layer through the first silicon through hole structure, the second metal contact bump is conducted with the first bottom metal electrode layer through the second silicon through hole structure, and the first metal contact bump and the second metal contact bump are in contact connection with the copper metal layer. The beneficial effects are that: the energy collected in the nano capacitor structure is transmitted to the outside through the first metal contact salient point and the second metal contact salient point, so that the continuous and stable output of the energy is realized, and the nano capacitor structure can be externally connected with different loads for use.
The invention also provides a preparation method of the three-dimensional integrated system, which comprises the following steps:
selecting an etching substrate, etching a plurality of silicon nano holes on the surface of the etching substrate, and preparing to obtain a nano capacitor structure;
preparing a nano generator with a common electrode on the surface of the nano capacitor structure;
processing two sides of the top of the nano generator to obtain a first silicon through hole structure and a second silicon through hole structure;
and carrying out metal wiring in the first silicon through hole structure and the second silicon through hole structure, and connecting the nano capacitor structure and the nano generator in a conduction manner to obtain a final integrated system.
The invention has the beneficial effects that: by the preparation method, the nano generator and the nano capacitor structure are integrated together, one electrode is shared, and the nano generator and the nano capacitor structure are integrated through the first silicon through hole structure and the second silicon through hole structure, so that the system volume is reduced, the integration level is improved, and the nano capacitor structure can continuously output stable energy.
Further, the specific process of etching a plurality of silicon nanopores on the surface of the silicon substrate and preparing the nano-capacitor structure includes:
selecting an etching substrate and determining a pattern structure of the silicon nano-holes on the etching substrate structure;
etching the etching substrate according to the pattern structure to obtain a plurality of silicon nano holes so as to form an array;
depositing on the inner surface of the silicon nano-hole and the top end surface of the etching substrate to obtain a first isolation medium;
and depositing on the surface of the first isolation medium to obtain a first bottom metal electrode layer, a first insulating medium and a first top metal electrode layer.
The beneficial effects are that: the first isolation medium, the first bottom metal electrode layer, the first insulation medium and the first top metal electrode layer are integrated together through the process, and the obtained nano capacitor structure is stable in structure.
Further, the first isolation medium comprises SiO2、Si3N4、SiON、At least one of SiCOH and SiCOFH, wherein the thickness of the first isolation medium is 100-200 nm.
Further, the first bottom metal electrode layer and the first top metal electrode layer comprise at least one of TaN, TiN, WN, MoN, Ni and Ru, the thickness of the first bottom metal electrode layer is 50-150 nm, and the thickness of the first top metal electrode layer is 100-300 nm.
Further, the first insulating medium comprises Al2O3、ZrO2、TiO2、HfO2、La2O3At least one of HfZrO, HfAlO and HfTiO, wherein the thickness of the first insulating medium is 10-50 nm.
Further, the etching method of the silicon nanopore includes at least one of dry etching such as ion mill etching, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or wet etching by using an etchant solution.
Further, the deposition method for obtaining the first isolation medium, the first bottom metal electrode layer, the first insulation medium and the first top metal electrode layer comprises at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and pulsed laser deposition.
Further, the process of preparing the nanogenerator with the common electrode on the surface of the nanocapacitor structure comprises the following steps:
preparing a piezoelectric material, and coating the piezoelectric material on the surface of the first top metal electrode layer to form a second insulating medium;
and depositing a second top metal electrode layer on the surface of the second insulating medium.
The beneficial effects are that: according to the nano generator obtained in the manner, the first top metal electrode layer of the nano capacitor structure is used as the second bottom metal electrode, the second top metal electrode layer is matched with the working action between the second top metal electrode layers, two electrodes of the nano generator are respectively formed, the coated second insulating medium not only plays an insulating role, but also is used as a piezoelectric material of the nano generator to generate a piezoelectric effect so as to generate electric power when the nano generator is used.
Further, the second insulating medium comprises at least one of ZnO, ZnS, GaN, InN, PZT, PVDF and PVDF-TrFE, and the thickness of the second insulating medium is 1-10 μm.
Further, the piezoelectric material is at least one of a planar structure, a nanopore structure and a nanowire structure.
Further, the second top metal electrode layer comprises at least one of Au, Ag, Al, TiN and TaN, and the thickness of the second top metal electrode layer is 100-200 nm.
Further, the process of processing the two sides of the top of the nano generator to obtain the first through silicon via structure and the second through silicon via structure includes:
spin-coating photoresist and defining the position and the pattern of the polycrystalline silicon through exposure and development processes;
etching the surfaces of the left side and the right side of the second top metal electrode layer and the second insulating medium according to the position and the pattern of the polycrystalline silicon to obtain ports;
depositing a layer of second isolation medium on the surface of the port and the surface of the second top metal electrode layer;
depositing a layer of polycrystalline silicon on the surface of the second isolation medium by adopting a vapor deposition process, and removing the polycrystalline silicon right above the surface of the second isolation medium by adopting photoetching and etching processes to enable the surfaces of the polycrystalline silicon in the ports at two sides to be flush with the surface of the second isolation medium;
spin-coating photoresist and defining the figures and positions of the first silicon through hole structure and the second silicon through hole structure through exposure and development processes;
etching the polysilicon on the left side and the second isolation medium until the polysilicon is contacted with the first top metal electrode layer, so as to obtain a first silicon through hole structure;
and etching the polysilicon on the right side, the second isolation medium, the first top metal electrode layer and the first insulation medium until the polysilicon is contacted with the first bottom metal electrode layer, so as to obtain a second silicon through hole structure.
The beneficial effects are that: the first silicon through hole structure and the second silicon through hole structure are obtained through the mode, the nano capacitor structure and the nano generator are integrated together, the system volume is reduced, the system integration level is improved, and meanwhile the first silicon through hole structure and the second silicon through hole structure obtained through the method are distributed on two sides of the top of the nano generator, so that the influence on the work of the nano generator is small.
Further, the second isolation medium comprises SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH.
Further, the etching method in the above process includes at least one of ion milling etching, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or wet etching process by using etchant solution.
Further, the process of performing metal wiring inside the first through silicon via structure and the second through silicon via structure, and conductively connecting the nanocapacitor structure and the nanogenerator to obtain a final integrated system includes:
depositing a layer of third isolation medium on the surfaces of the first through silicon via structure, the second through silicon via structure and the second isolation medium positioned in the middle position by adopting a deposition process;
etching the surfaces of the third isolation medium and the second isolation medium until the second top metal electrode layer is exposed to obtain a groove structure, etching the third isolation medium at the bottoms of the first silicon through hole structure and the second silicon through hole structure, and respectively exposing the first top metal electrode layer at the left side and the first bottom metal electrode layer at the right side;
sequentially depositing a copper diffusion barrier layer and a copper seed crystal layer on the first silicon through hole structure, the second silicon through hole structure and the groove structure;
electroplating a copper metal layer on the copper seed crystal layer;
removing the topmost copper metal layer by a polishing process until the topmost end of the copper metal layer is flush with the height of the copper seed crystal layer;
etching the copper seed crystal layer and the copper diffusion layer between the first silicon through hole structure and the groove structure by adopting an etching process until the third isolation medium is completely exposed;
and depositing a film of the same material as the third isolation medium on the surface of the exposed third isolation medium to thicken the third isolation medium, and etching and removing the film on the top until the third isolation medium is flush with the topmost surface of the copper metal layer.
The beneficial effects are that: by the method, metal wiring is carried out on the first silicon through hole structure and the second silicon through hole structure, and when the nano capacitor structure and the nano generator are electrically connected, energy accumulated in the nano capacitor structure can be conveniently and stably output to the outside.
Further, the third isolation medium comprises SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH.
Further, the copper diffusion impervious layer comprises TaN, TiN, ZrN and MnSiO3At least one of (1).
Further, the copper seed layer includes at least one of Cu, Ru, Co, RuCo, CuRu, and CuCo.
Furthermore, the third isolation medium, the copper diffusion barrier layer and the copper seed layer are grown by at least one of physical vapor deposition, chemical vapor deposition and atomic layer deposition.
Further, still include one deck copper product material of electroplating is regarded as first metal contact bump on first through-silicon-via structure top the groove structure with electroplate one deck copper product material as second metal contact bump between the second through-silicon-via structure.
Further, the first metal contact bump is in electrical contact with the copper metal layer in the first through-silicon-via structure, and the second metal contact bump is in electrical contact with the copper metal layer in the trench structure and the second through-silicon-via structure. The beneficial effects are that: the first metal contact salient point and the second metal contact salient point are respectively and electrically connected with the two electrodes of the nano capacitor structure through the copper metal layer, so that power output is realized.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a three-dimensional integrated system according to the present invention;
FIG. 2 is a schematic view of the overall working flow of the manufacturing method of the present invention;
FIG. 3 is a schematic diagram of the structure of an etched substrate according to the present invention;
fig. 4 is a schematic structural view obtained after step S1 is completed in the manufacturing method of the present invention;
fig. 5 is a schematic structural view obtained after step S2 is completed in the manufacturing method of the present invention;
fig. 6 is a schematic structural view obtained after step S32 is completed in the manufacturing method of the present invention;
fig. 7 is a schematic structural view obtained after step S33 is completed in the production method of the present invention;
fig. 8 is a schematic structural view of the production method of the present invention after completion of step S34;
fig. 9 is a schematic structural view obtained after the preparation method of the present invention completes step S37;
fig. 10 is a schematic structural view obtained after the preparation method of the present invention completes step S41;
fig. 11 is a schematic structural view obtained after completion of step S42 in the production method of the present invention;
fig. 12 is a schematic structural view obtained after the preparation method of the present invention completes step S44;
fig. 13 is a schematic structural view obtained after completion of step S46 in the production method of the present invention;
FIG. 14 is a schematic view of the overall structure of a three-dimensional integrated system obtained after completion of the manufacturing method of the present invention;
FIG. 15 is a schematic view of the overall structure of a three-dimensional integrated system obtained by electroplating a first metal contact bump and a second metal contact bump after the fabrication method of the present invention is completed;
FIG. 16 is a schematic view of the operation of step S1 of the preparation method of the present invention;
FIG. 17 is a schematic view of the operation of step S2 of the preparation method of the present invention;
FIG. 18 is a schematic view of the operation of step S3 of the preparation method of the present invention;
fig. 19 is a schematic flow chart of step S4 of the preparation method of the present invention.
Reference numbers in the figures:
101-a nanocapacitive structure; 102-a nano-generator; 103-a first through-silicon-via structure; 104-a second through-silicon-via structure; 105-a trench structure;
200-etching the substrate; 201-a first isolation medium; 202-a first bottom metal electrode layer; 203-a first insulating medium; 204-a first top metal electrode layer; 205-a second insulating dielectric layer; 206-a second top metal electrode layer; 207-a second release medium; 208-polysilicon; 209-a third isolation medium; 210-a copper diffusion barrier layer; 211-a copper seed layer; 212-copper metal layer; 213-first metal contact bump; 214-second metal contact bump.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, as shown in fig. 1, an embodiment of the present invention provides a three-dimensional integrated system, which includes a nanogenerator 102, a nanocapacitive structure 101, a first through-silicon-via structure 103, and a second through-silicon-via structure 104;
the nano capacitor structure 101 is installed at the bottom end of the nano generator 102, the first through-silicon-via structure 103 and the second through-silicon-via structure 104 are respectively disposed at the left and right sides of the top of the nano generator 102, and the nano generator 102 and the nano capacitor structure 101 are integrated together and electrically connected through the first through-silicon-via structure 103 and the second through-silicon-via structure 104, so that the nano generator 102 stores the generated electric energy inside the nano capacitor structure 101, and the nano capacitor structure 101 and the nano generator 102 share one electrode.
In the integrated system, the nano generator 102 and the nano capacitor structure 101 are integrated together, so that not only one electrode is shared, but also electric energy generated by the nano generator 102 can be transmitted to the nano capacitor structure 101 for storage, thereby realizing continuous and stable output of the electric energy and meeting different use requirements, on the other hand, the integrated system integrates the nano capacitor structure 101 and the nano generator 102 together through the first through silicon via structure 103 and the second through silicon via structure 104, improves the system integration level, reduces the whole area, and simultaneously, the first through silicon via structure 103 and the second through silicon via structure 104 are distributed at the local positions on two sides of the nano generator 102, so that the influence on the power generation work of the nano generator 102 is small.
In a possible implementation manner, the nano-capacitor structure 101 includes an etching substrate 200, a plurality of silicon nano-holes are disposed on the etching substrate 200, a first isolation medium 201, a first bottom metal electrode layer 202, a first insulating medium 203, and a first top metal electrode layer 204 are sequentially disposed on the surface of the etching substrate 200 and the surface of the silicon nano-holes from bottom to top, and the insides of the silicon nano-holes are completely filled.
The nano-capacitor structure 101 uses the first bottom metal electrode layer 202 and the first top metal electrode layer 204 as two electrodes, the first isolation medium 201 isolates the etching substrate 200 from the first bottom metal electrode layer 202, and the first bottom metal electrode layer 202 and the first top metal electrode layer 204 are insulated and protected by the first insulation medium 203, so as to avoid mutual influence between the electrodes.
Further, the nano-generator 102 includes a second insulating medium layer 205 and a second top metal electrode layer 206, a second isolation medium 207 is disposed on an outer wall of the second top metal electrode layer 206, the second isolation medium 207 further covers the surface of the first top metal electrode layer 204, the first top metal electrode layer 204 and the second top metal electrode layer 206 are respectively used as two electrodes of the nano-generator 102, ports are disposed at two ends of the second isolation medium 207, and a polysilicon 208 is disposed on the ports.
The nanometer generator 102 uses the first top metal electrode layer 204 of the nanometer capacitor structure 101 as the second bottom metal electrode layer, and uses the second top metal electrode layer 206 on the top of the second insulating medium 205 as two electrodes of the nanometer generator 102, respectively, and shares one electrode with the nanometer capacitor structure 101, thereby not only improving the system integration level, but also reducing the system area.
The second insulating medium 205 is not only an insulating material but also a piezoelectric material, and generates electric energy by a piezoelectric effect, and transmits the electric energy to the outside through the first top metal electrode layer 204 and the second top metal electrode layer 206 as two electrodes, thereby realizing piezoelectric power generation.
Furthermore, the first tsv structure 103 penetrates the polysilicon 208 and contacts the first top metal electrode layer 204, the second tsv structure 104 penetrates the polysilicon 208, the second isolation medium 207, the first top metal electrode layer 204 and the first insulation medium 201, and contacts the first bottom metal electrode layer 202, and third isolation media 209 are disposed on the sidewalls, the upper surface of the first tsv structure 103 and the second tsv structure 104, and the upper surface of the second isolation medium 207.
In a possible implementation, a trench structure 105 is further disposed inside the third isolation medium 209, the trench structure 105 is disposed adjacent to the second tsv structure 104, the trench structure 105 is separated from the first tsv structure 104 by the third isolation medium 209, and the third isolation medium 209 isolates the first tsv structure 103 from the trench structure 105 to avoid an interference effect.
In a possible implementation manner, a copper diffusion barrier layer 210 is disposed on the surfaces of the first through silicon via structure 103, the second through silicon via structure 104, and the trench structure 105, the copper diffusion barrier layer 210 electrically connects the first bottom metal electrode layer 202 and the second top metal electrode layer 206, a copper seed layer 211 is disposed on the surface of the copper diffusion barrier layer 210, a copper metal layer 212 is disposed on the surface of the copper seed layer 211, and the interiors of the first through silicon via structure 103, the second through silicon via structure 104, and the trench structure 105 are completely filled with a structure composed of the copper diffusion barrier layer 210, the copper seed layer 211, and the copper metal layer 212.
Through copper diffusion barrier layer 210, copper seed layer 211, copper metal layer 212 in first through-silicon-via structure 103 and the second through-silicon-via structure 104 for can electric connection together between nanometer capacitor structure 101 and nanometer generator 102, thereby be convenient for nanometer generator 102 can transmit the electric energy that produces inside nanometer capacitor structure 101, thereby be convenient for nanometer capacitor structure 101 can continuously export stable energy.
In a possible embodiment, the height of the third isolation medium 209 between the trench structure 105 and the first through-silicon-via structure 103 is the same as the height of the copper metal layer 212, so that the integrated system surface structure is flat, thereby facilitating the nanogenerator 102 to generate electric energy through the piezoelectric effect.
In a possible implementation manner, a first metal contact bump 213 is disposed on the top of the first through silicon via structure 103, a second metal contact bump 204 is disposed on the top of the second through silicon via structure 104, the first metal contact bump 213 is electrically connected to the first top metal electrode layer 204 through the first through silicon via structure 103, the second metal contact bump 214 is electrically connected to the first bottom metal electrode layer 202 through the second through silicon via structure 104, and the first metal contact bump 213 and the second metal contact bump 214 are both in contact connection with the copper metal layer 212.
After the electric energy generated by the nanogenerator 102 is transmitted into the nano-capacitor structure 101 for storage, the electric energy is transmitted to the outside through the first through silicon via structure 103 and the second through silicon via structure 104, and is specifically connected with an external load, such as an LED lamp, through the first metal contact bump 213 and the second metal contact bump 214.
In specific operation, for the electric energy stored in the nano-capacitor structure 101, the first top metal electrode layer 204 of the nano-capacitor structure 101 is electrically connected to the first metal contact bump 213 through the copper diffusion barrier layer 210, the copper seed layer 211 and the copper metal layer 212 in the first through-silicon-via structure 103, and the first bottom metal electrode layer 202 is electrically connected to the second metal contact bump 214 through the copper diffusion barrier layer 210, the copper seed layer 211 and the copper metal layer 212 in the second through-silicon-via structure 104, so that the nano-capacitor structure 101 can continuously and stably output the electric energy to the outside.
As shown in fig. 2, the present invention further provides a method for preparing a three-dimensional integrated system, comprising the following steps:
s1, selecting the etching substrate 200, etching a plurality of silicon nano holes on the surface of the etching substrate 200, and preparing to obtain the nano capacitor structure 101.
In a possible implementation, as shown in fig. 16, the specific process of the above steps includes:
s11, selecting the etching substrate 200 and determining the pattern structure of the silicon nano holes on the etching substrate structure.
Specifically, the image structure of the silicon nanopore is defined by spin-coating a photoresist and through exposure and development processes.
And S12, etching the etching substrate 200 according to the pattern structure to obtain a plurality of silicon nano holes to form an array.
The specific resulting structure is shown in fig. 3.
S13, depositing on the inner surface of the silicon nanopore and the top surface of the etching substrate 200 to obtain a first isolation medium 201;
s14, depositing a first bottom metal electrode layer 202, a first insulating medium 203 and a first top metal electrode layer 204 on the surface of the first isolation medium 201.
After the above process is completed, the resultant structure is shown in fig. 4.
In one possible embodiment, the first isolation medium 201 comprises SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH, wherein the first isolation dielectric 201 has a thickness of 100 to 200 nm.
Preferably, the first isolation medium 201 selected in this embodiment is SiO2Deposited SiO2The resulting thickness of the first isolation dielectric 201 is 150 nm.
In one possible embodiment, the first bottom metal electrode layer 202 and the first top metal electrode layer 204 comprise at least one of TaN, TiN, WN, MoN, Ni and Ru, the thickness of the first bottom metal electrode layer 202 is 50 to 150nm, and the thickness of the first top metal electrode layer 204 is 100 to 300 nm.
Preferably, the material selected for the first bottom metal electrode layer 202 and the first top metal electrode layer 204 in this embodiment is TiN, wherein the thickness of the first bottom metal electrode layer 202 and the first top metal electrode layer 204 is 200 nm.
In one possible embodiment, the first insulating medium 203 comprises Al2O3、ZrO2、TiO2、HfO2、La2O3At least one of HfZrO, HfAlO and HfTiO, wherein the thickness of the first insulating medium 203 is 10-50 nm.
Preferably, the material of the first insulating medium 203 is selected to be Al in this embodiment2O3Wherein the thickness of the first insulating medium 203 is 30 nm.
In one possible embodiment, the etching method of the silicon nanopore includes at least one of dry etching such as ion mill etching, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or wet etching by using an etchant solution.
Preferably, the etching method selected in this embodiment is deep reactive ion etching.
It should be noted that, when etching the etching substrate 200, the plasma is CF4、SF6At least one of, particularly CF4。
In one possible embodiment, the deposition method for obtaining the first isolation medium 201, the first bottom metal electrode layer 202, the first insulating medium 203 and the first top metal electrode layer 204 comprises at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and pulsed laser deposition.
And S2, preparing a nanometer generator 102 with a common electrode on the surface of the nanometer capacitor structure 101.
In a possible implementation, as shown in fig. 17, the specific process of the above steps includes:
s21, preparing a piezoelectric material, and coating the piezoelectric material on the surface of the first top metal electrode layer 204 to form a second insulating medium 205.
The second insulating medium 205 is not only an insulating material, but also a piezoelectric material itself used for the insulating material has a piezoelectric effect, and can generate electric energy by the piezoelectric effect to realize piezoelectric power generation.
And S22, depositing a second top metal electrode layer 206 on the surface of the second insulating medium 205.
After coating, deposition of the second insulating medium 205 and the second top metal electrode layer 206, the structure obtained is shown in fig. 5.
In one possible embodiment, the second insulating medium 205 comprises at least one of ZnO, ZnS, GaN, InN, PZT, PVDF and PVDF-TrFE, and the thickness of the second insulating medium 205 is 1 to 10 μm.
Preferably, the material of the second insulating medium 205 is PVDF, and the specific manufacturing method is to dissolve PVDF powder in diethyl carbonate solution to obtain PVDF solution, and the thickness of the finally obtained second insulating medium 205 is 5.5 μm.
In one possible embodiment, the piezoelectric material is at least one of a planar structure, a nanopore structure, and a nanowire structure.
Specifically, the PVDF material having a planar structure is used as the piezoelectric material, and the PVDF material having a three-dimensional structure, such as a PVDF nanopore or nanowire structure, may also be used; but also other piezoelectric materials with three-dimensional structures, such as ZnO nanowires, ZnS nanowires or GaN nanowires.
In one possible embodiment, the second top metal electrode layer 206 comprises at least one of Au, Ag, Al, TiN, TaN, and the thickness of the second top metal electrode layer 206 is 100-200 nm.
Preferably, the material of the second top metal electrode layer 206 selected by the present invention is Au, and the thickness thereof is 150 nm.
And S3, processing two sides of the top of the nano generator 102 to obtain a first through silicon via structure 103 and a second through silicon via structure 104.
In a possible implementation, as shown in fig. 18, the specific process of the above steps includes:
s31, spin-coating photoresist and defining the position and the pattern of the polysilicon 208 through exposure and development processes;
and S32, etching the surfaces of the left side and the right side of the second top metal electrode layer 206 and the second insulating medium 205 according to the position and the pattern of the polysilicon 208 to obtain ports.
After etching the left and right sides of the second top metal electrode layer 206 and the second insulating medium 205 by the above method, the resulting structure diagram is shown in fig. 6.
S33, depositing a second isolation medium 207 on the surface of the port and the surface of the second top metal electrode layer 206.
After deposition of the second isolation dielectric 207, the resulting structure is shown in fig. 7.
S34, depositing a layer of polysilicon 208 on the surface of the second isolation medium 207 by adopting a vapor deposition process, and removing the polysilicon 208 right above the surface of the second isolation medium 207 by adopting a photoetching and etching process, so that the surfaces of the polysilicon 208 in the ports on both sides are flush with the surface of the second isolation medium 207.
The resulting structure is shown in FIG. 8.
S35, spin-coating photoresist, and defining the patterns and positions of the first through-silicon-via structure 103 and the second through-silicon-via structure 104 through exposure and development processes;
s36, etching the polysilicon 208 and the second isolation medium 207 on the left side until contacting the first top metal electrode layer 204, so as to obtain the first through silicon via structure 103;
s37, etching the polysilicon 208, the second isolation medium 207, the first top metal electrode layer 204, and the first insulation medium 203 on the right side until contacting the first bottom metal electrode layer 202, thereby obtaining the second tsv structure 104.
After the above-described processing, the resultant structure is shown in fig. 9.
In one possible embodiment, the second isolation medium 207 comprises SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH, wherein SiO is specifically selected in the scheme2。
In a possible embodiment, the etching method in the above process includes at least one of ion mill etching, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or wet etching process by using etchant solution.
S4, metal wiring is performed inside the first through silicon via structure 103 and the second through silicon via structure 104, and the nanocapacitive structure 101 and the nanogenerator 102 are conductively connected to obtain a final integrated system.
In a possible implementation, as shown in fig. 19, the specific process of the above steps includes:
and S41, depositing a layer of third isolation medium 209 on the surfaces of the first through silicon via structure 103, the second through silicon via structure 104 and the second isolation medium 207 in the middle position by using a deposition process.
After deposition of the third isolation dielectric 209, the resulting structure is shown in fig. 10.
S42, etching the surfaces of the third isolation medium 209 and the second isolation medium 207 until the second top metal electrode layer 206 is exposed to obtain the trench structure 105, etching the third isolation medium 209 at the bottom of the first through-silicon via structure 103 and the second through-silicon via structure 104 to expose the first top metal electrode layer 204 on the left side and the first bottom metal electrode layer 202 on the right side, respectively.
The resulting structure is shown in FIG. 11.
S43, sequentially depositing a copper diffusion barrier layer 210 and a copper seed layer 211 on the first through-silicon-via structure 103, the second through-silicon-via structure 104 and the trench structure 105.
S44, a copper metal layer 212 is electroplated on the copper seed layer 211.
After the copper diffusion barrier layer 210, the copper seed layer 211 and the copper metal layer 212 are sequentially deposited, the resulting structure is shown in fig. 12.
S45, removing the topmost copper metal layer 212 by a polishing process until the topmost copper metal layer 212 is flush with the copper seed layer 211.
S46, etching the copper seed layer 210 and the copper diffusion layer 211 between the first through-silicon-via structure 103 and the trench structure 105 by using an etching process until the third isolation medium 209 is completely exposed.
After the third insulating medium 209 is exposed, the resulting structure is shown in fig. 13.
S47, depositing a film of the same material as that of one layer of the third isolation medium 209 on the exposed surface of the third isolation medium 209 to thicken the third isolation medium 209, and etching to remove the top film until the third isolation medium 209 is flush with the topmost surface of the copper metal layer 212.
After the above steps are completed, the resulting structure is shown in fig. 14.
In one possible embodiment, the third isolation dielectric 209 comprises SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH, wherein SiO is selected in the scheme2。
In one possible embodiment, the copper diffusion barrier layer 210 comprises at least one of TaN, TiN, ZrN, MnSiO3, with TaN being particularly preferred in this embodiment.
In one possible embodiment, the copper seed layer 211 comprises at least one of Cu, Ru, Co, RuCo, CuRu, CuCo, Co being selected in the present embodiment.
In one possible embodiment, the third isolation medium 209, the copper diffusion barrier layer 210 and the copper seed layer 211 are grown by at least one of physical vapor deposition, chemical vapor deposition and atomic layer deposition, and the scheme selects a chemical vapor deposition process.
In a possible implementation manner, a layer of copper material is electroplated on the top of the first through-silicon-via structure 103 as a first metal contact bump 213, a layer of copper material is electroplated between the trench structure 105 and the second through-silicon-via structure 104 as a second metal contact bump 214, and after the first metal contact bump 213 and the second metal contact bump 214 are obtained by electroplating, the structural diagram of the whole integrated system is shown in fig. 15.
It should be noted that the etching process, the deposition process, the electroplating process, the coating process, and the like adopted in the present solution are all mature processes in the prior art, the present solution does not relate to improvement of a specific process, and any related process capable of realizing the function of the corresponding process in the present solution can be applied to the technical solution of the present application, which is not particularly limited thereto.
In one possible implementation, the first metal contact bump 213 is in electrical contact with the copper metal layer 214 in the first through silicon via structure 214, and the second metal contact bump 214 is in electrical contact with the copper metal layer 212 in the trench structure 105 and the second through silicon via structure 104.
The invention has the beneficial effects that: the integrated system obtained by the processing technology stores the electric energy collected by the nano generator in the nano capacitor structure, and can obtain stable energy output; meanwhile, the nanometer generator and the nanometer capacitor structure are integrated through the first silicon through hole structure and the second silicon through hole structure, so that the occupied area of the system is reduced, and the reduction of the system area and the improvement of the integration level are facilitated; meanwhile, the materials adopted by the nano generator and the nano capacitor structure are easy to shrink in size, and the size of the whole system is easy to shrink; and the first silicon through hole structure and the second silicon through hole structure are distributed in local areas on two sides of the nano generator, so that the influence on the energy collection area during piezoelectric power generation of the nano generator is small.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (29)
1. A three-dimensional integrated system is characterized by comprising a nanometer generator, a nanometer capacitor structure, a first through silicon via structure and a second through silicon via structure;
the nanometer capacitor structure is installed the nanometer generator bottom, first through-silicon via structure with the second through-silicon via structure sets up respectively the top left and right sides of nanometer generator, the nanometer generator with pass through between the nanometer capacitor structure first through-silicon via structure, the integration of second through-silicon via structure is in the same place and electric connection, makes the electric energy that the nanometer generator will produce is stored inside the nanometer capacitor structure, just the nanometer capacitor structure with an electrode is shared to the nanometer generator.
2. The three-dimensional integrated system according to claim 1, wherein the nano-capacitor structure comprises an etched substrate, a plurality of silicon nano-holes are formed in the etched substrate, a first isolation medium, a first bottom metal electrode layer, a first insulation medium and a first top metal electrode layer are sequentially formed on the surface of the etched substrate and the surface of the silicon nano-holes from bottom to top, and the insides of the silicon nano-holes are completely filled.
3. The three-dimensional integrated system according to claim 2, wherein the nano-generator comprises a second insulating medium layer and a second top metal electrode layer, a second isolation medium is disposed on an outer wall of the second top metal electrode layer, the second isolation medium further covers a surface of the first top metal electrode layer, the first top metal electrode layer and the second top metal electrode layer are respectively used as two electrodes of the nano-generator, two ends of the second isolation medium are both provided with ports, and polysilicon is disposed on the ports.
4. The three-dimensional integrated system according to claim 3, wherein the first through-silicon-via structure penetrates the polysilicon and contacts the first top metal electrode layer, the second through-silicon-via structure penetrates the polysilicon, a second isolation medium, a first top metal electrode layer and the first insulation medium and contacts the first bottom metal electrode layer, and a third isolation medium is disposed on sidewalls, an upper surface of the first through-silicon-via structure and sidewalls, an upper surface of the second through-silicon-via structure and an upper surface of the second isolation medium.
5. The three-dimensional integrated system according to claim 4, wherein a trench structure is further disposed inside the third isolation medium, the trench structure is disposed adjacent to the second through-silicon-via structure, and the trench structure is separated from the first through-silicon-via structure by the third isolation medium.
6. The three-dimensional integrated system according to claim 5, wherein a copper diffusion barrier layer is disposed on the surface of each of the first through-silicon-via structure, the second through-silicon-via structure, and the trench structure, the copper diffusion barrier layer electrically connects the first bottom metal electrode layer and the second top metal electrode layer, a copper seed layer is disposed on the surface of the copper diffusion barrier layer, a copper metal layer is disposed on the surface of the copper seed layer, and the first through-silicon-via structure, the second through-silicon-via structure, and the trench structure are completely filled with the structure consisting of the copper diffusion barrier layer, the copper seed layer, and the copper metal layer.
7. The three-dimensional integrated system according to claim 6, wherein a height of the third isolation medium between the trench structure and the first through-silicon-via structure is the same as a height of the copper metal layer.
8. The three-dimensional integrated system according to claim 6, wherein a first metal contact bump is disposed on top of the first through-silicon-via structure, a second metal contact bump is disposed on top of the second through-silicon-via structure, the first metal contact bump is conductively connected to the first top metal electrode layer through the first through-silicon-via structure, the second metal contact bump is conductively connected to the first bottom metal electrode layer through the second through-silicon-via structure, and the first metal contact bump and the second metal contact bump are both in contact connection with the copper metal layer.
9. A method for preparing a three-dimensional integrated system is characterized by comprising the following steps:
selecting an etching substrate, etching a plurality of silicon nano holes on the surface of the etching substrate, and preparing to obtain a nano capacitor structure;
preparing a nano generator with a common electrode on the surface of the nano capacitor structure;
processing two sides of the top of the nano generator to obtain a first silicon through hole structure and a second silicon through hole structure;
and carrying out metal wiring in the first silicon through hole structure and the second silicon through hole structure, and connecting the nano capacitor structure and the nano generator in a conduction manner to obtain a final integrated system.
10. The method for preparing the three-dimensional integrated system according to claim 9, wherein the specific process of etching a plurality of silicon nanopores on the surface of the silicon substrate and preparing the nano-capacitor structure comprises:
selecting an etching substrate and determining a pattern structure of the silicon nano-holes on the etching substrate structure;
etching the etching substrate according to the pattern structure to obtain a plurality of silicon nano holes so as to form an array;
depositing on the inner surface of the silicon nano-hole and the top end surface of the etching substrate to obtain a first isolation medium;
and depositing on the surface of the first isolation medium to obtain a first bottom metal electrode layer, a first insulating medium and a first top metal electrode layer.
11. The method of claim 10, wherein the first isolation medium comprises SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH, wherein the thickness of the first isolation medium is 100-200 nm.
12. The method for manufacturing a three-dimensional integrated system according to claim 10, wherein the first bottom metal electrode layer and the first top metal electrode layer comprise at least one of TaN, TiN, WN, MoN, Ni and Ru, the thickness of the first bottom metal electrode layer is 50 to 150nm, and the thickness of the first top metal electrode layer is 100 to 300 nm.
13. The method of claim 10, wherein the first insulating medium comprises Al2O3、ZrO2、TiO2、HfO2、La2O3At least one of HfZrO, HfAlO and HfTiO, wherein the thickness of the first insulating medium is 10-50 nm.
14. The method of claim 10, wherein the etching method of the silicon nanopore comprises at least one of dry etching such as ion mill etching, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or wet etching by using an etchant solution.
15. The method of claim 10, wherein the deposition process to obtain the first isolation medium, the first bottom metal electrode layer, the first insulating medium, and the first top metal electrode layer comprises at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, and pulsed laser deposition.
16. The method of claim 10, wherein the step of preparing the nanogenerator having a common electrode on the surface of the nanocapacitive structure comprises:
preparing a piezoelectric material, and coating the piezoelectric material on the surface of the first top metal electrode layer to form a second insulating medium;
and depositing a second top metal electrode layer on the surface of the second insulating medium.
17. The method for manufacturing a three-dimensional integrated system according to claim 16, wherein the second insulating medium comprises at least one of ZnO, ZnS, GaN, InN, PZT, PVDF, and PVDF-TrFE, and has a thickness of 1 to 10 μm.
18. The method of claim 17, wherein the piezoelectric material is at least one of a planar structure, a nanopore structure, and a nanowire structure.
19. The method for manufacturing a three-dimensional integrated system according to claim 16, wherein the second top metal electrode layer comprises at least one of Au, Ag, Al, TiN, TaN, and the thickness of the second top metal electrode layer is 100-200 nm.
20. The method for preparing the three-dimensional integrated system according to claim 16, wherein the step of processing the two sides of the top of the nanogenerator to obtain the first through silicon via structure and the second through silicon via structure comprises:
spin-coating photoresist and defining the position and the pattern of the polycrystalline silicon through exposure and development processes;
etching the surfaces of the left side and the right side of the second top metal electrode layer and the second insulating medium according to the position and the pattern of the polycrystalline silicon to obtain ports;
depositing a layer of second isolation medium on the surface of the port and the surface of the second top metal electrode layer;
depositing a layer of polycrystalline silicon on the surface of the second isolation medium by adopting a vapor deposition process, and removing the polycrystalline silicon right above the surface of the second isolation medium by adopting photoetching and etching processes to enable the surfaces of the polycrystalline silicon in the ports at two sides to be flush with the surface of the second isolation medium;
spin-coating photoresist and defining the figures and positions of the first silicon through hole structure and the second silicon through hole structure through exposure and development processes;
etching the polysilicon on the left side and the second isolation medium until the polysilicon is contacted with the first top metal electrode layer, so as to obtain a first silicon through hole structure;
and etching the polysilicon on the right side, the second isolation medium, the first top metal electrode layer and the first insulation medium until the polysilicon is contacted with the first bottom metal electrode layer, so as to obtain a second silicon through hole structure.
21. The method of claim 20, wherein the second isolation medium comprises SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH.
22. The method of claim 20, wherein the etching process comprises at least one of ion milling, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or wet etching process using an etchant solution.
23. The method for preparing a three-dimensional integrated system according to claim 20, wherein the step of conducting metal wiring inside the first through-silicon-via structure and the second through-silicon-via structure to conductively connect the nanocapacitor structure and the nanogenerator to obtain a final integrated system comprises:
depositing a layer of third isolation medium on the surfaces of the first through silicon via structure, the second through silicon via structure and the second isolation medium positioned in the middle position by adopting a deposition process;
etching the surfaces of the third isolation medium and the second isolation medium until the second top metal electrode layer is exposed to obtain a groove structure, etching the third isolation medium at the bottoms of the first silicon through hole structure and the second silicon through hole structure, and respectively exposing the first top metal electrode layer at the left side and the first bottom metal electrode layer at the right side;
sequentially depositing a copper diffusion barrier layer and a copper seed crystal layer on the first silicon through hole structure, the second silicon through hole structure and the groove structure;
electroplating a copper metal layer on the copper seed crystal layer;
removing the topmost copper metal layer by a polishing process until the topmost end of the copper metal layer is flush with the height of the copper seed crystal layer;
etching the copper seed crystal layer and the copper diffusion layer between the first silicon through hole structure and the groove structure by adopting an etching process until the third isolation medium is completely exposed;
and depositing a film of the same material as the third isolation medium on the surface of the exposed third isolation medium to thicken the third isolation medium, and etching and removing the film on the top until the third isolation medium is flush with the topmost surface of the copper metal layer.
24. The method of claim 23, wherein the third isolation medium comprises SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH.
25. The method of claim 23, wherein the copper diffusion barrier layer comprises TaN, TiN, ZrN, MnSiO3At least one of (1).
26. The method of claim 23, wherein the copper seed layer comprises at least one of Cu, Ru, Co, RuCo, CuRu, CuCo.
27. The method of claim 23, wherein the third isolation dielectric, the copper diffusion barrier layer, and the copper seed layer are grown by at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.
28. The method of claim 23, further comprising electroplating a layer of copper material on top of the first through-silicon-via structure as a first metal contact bump and electroplating a layer of copper material between the trench structure and the second through-silicon-via structure as a second metal contact bump.
29. The method of claim 28, wherein the first metal contact bump is in electrical contact with the copper metal layer in the first through-silicon-via structure, and wherein the second metal contact bump is in electrical contact with the copper metal layer in the trench structure and the second through-silicon-via structure.
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| US20040036051A1 (en) * | 2002-05-01 | 2004-02-26 | Ofer Sneh | Integrated capacitor with enhanced capacitance density and method of fabricating same |
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| CN102800734A (en) * | 2012-09-04 | 2012-11-28 | 上海中科高等研究院 | Solar power generation and storage integrated device |
| CN111446083A (en) * | 2020-03-12 | 2020-07-24 | 复旦大学 | Silicon-based super capacitor and preparation method thereof |
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| US6797608B1 (en) * | 2000-06-05 | 2004-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming multilayer diffusion barrier for copper interconnections |
| US20040036051A1 (en) * | 2002-05-01 | 2004-02-26 | Ofer Sneh | Integrated capacitor with enhanced capacitance density and method of fabricating same |
| CN102103979A (en) * | 2009-12-16 | 2011-06-22 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional silicon-based passive circuit consisting of through silicon vias |
| CN102800734A (en) * | 2012-09-04 | 2012-11-28 | 上海中科高等研究院 | Solar power generation and storage integrated device |
| CN111446083A (en) * | 2020-03-12 | 2020-07-24 | 复旦大学 | Silicon-based super capacitor and preparation method thereof |
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