CN112071844B - Mask plate of flash memory device and manufacturing method - Google Patents
Mask plate of flash memory device and manufacturing method Download PDFInfo
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- CN112071844B CN112071844B CN202010986500.2A CN202010986500A CN112071844B CN 112071844 B CN112071844 B CN 112071844B CN 202010986500 A CN202010986500 A CN 202010986500A CN 112071844 B CN112071844 B CN 112071844B
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- 238000000034 method Methods 0.000 claims abstract description 31
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/88—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof prepared by photographic processes for production of originals simulating relief
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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Abstract
The invention provides a mask plate of a flash memory device and a manufacturing method thereof, wherein the mask plate of the flash memory device comprises an active region mask plate and a floating gate mask plate, and the active region mask plate comprises: in the manufacturing method of the flash memory device, the first active area pattern is arranged at the junction of the storage mask area and the peripheral mask area, the first active area can be defined at the junction of the storage area and the peripheral area through the active area mask, and when the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the peripheral area are etched, the first active area is defined at the junction of the storage area and the peripheral area, and in the etching process, if overetching occurs, the etching object of the overetching is the semiconductor substrate of the first active area, compared with the prior art, the selection ratio of the etching can be improved, thereby avoiding generating defects and further improving the performance of the flash memory device.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a mask plate of a flash memory device and a manufacturing method thereof.
Background
Currently, flash memory devices (Flash memory), also called Flash memory, have become the mainstream of nonvolatile memory, and the memory cells are formed by adding a Floating Gate (FG) and a Tunnel Oxide (Tunnel Oxide) on the basis of a conventional MOS transistor structure, and the Flash memory devices of the present invention also prepare isolation regions by a shallow trench isolation (STI, shallow Trench Isolation).
As shown in fig. 1, it is a schematic structural diagram formed by a method of manufacturing a flash memory device according to the prior art. The manufacturing method of the typical flash memory device in the prior art generally comprises the following steps: a first step of providing a semiconductor substrate 10, forming a floating gate oxide layer 20 and a floating gate layer 30 on the semiconductor substrate 10 in sequence, and etching the floating gate layer 30, the floating gate oxide layer 20 and the semiconductor substrate 10 to form a shallow trench, and filling an insulating dielectric material (i.e., STI HDPDE process) in the shallow trench to form a shallow trench isolation Structure (STI) 40, wherein the shallow trench isolation structure can define an active region of a memory region I and a peripheral region II; then, a second step is performed of forming a control gate layer (not shown) on the floating gate layer 30 and forming a dielectric layer 50 on the control gate layer, and then etching the dielectric layer 50, the control gate layer, the floating gate layer 30 and the floating gate oxide layer 20 of the storage region I to form openings and depositing a material layer 60 in the openings; next, as shown in fig. 2, a third step is performed to etch the dielectric layer 50, the control gate layer, the floating gate layer 30 and the floating gate oxide layer 20 of the peripheral region II. However, in this step, over etching is usually caused, and the over etching forms a deeper groove at the interface between the peripheral region and the storage region, so that the groove is more prone to forming defects in the subsequent process, for example, the process layer peels into the groove, thereby degrading the performance of the flash memory device. Accordingly, it would be desirable to provide an improved method of manufacturing a flash memory device.
Disclosure of Invention
The invention aims to provide a mask plate of a flash memory device and a manufacturing method thereof, which are used for solving the defect problem caused by a groove at the junction of a peripheral area and a storage area.
In order to solve the above technical problems, the present invention provides a mask for a flash memory device, the mask for a flash memory device comprising:
the active region mask comprises a storage mask region and a peripheral mask region, and a first active region pattern is formed at the junction of the storage mask region and the peripheral mask region;
the floating gate mask comprises a plurality of floating gate patterns which are arranged in parallel along a first direction and cross the first active region patterns along a second direction.
Optionally, in the mask of the flash memory device, a plurality of second active region patterns are formed in the storage mask region and the peripheral mask region, and the plurality of second active region patterns in the storage mask region and the peripheral mask region are arranged in parallel along the second direction; wherein the first direction is perpendicular to the second direction.
Optionally, in the mask of the flash memory device, the plurality of floating gate patterns cross the plurality of second active region patterns along the second direction.
Optionally, in the mask of the flash memory device, the floating gate pattern includes a curve pattern and two straight stripe patterns respectively connected to two ends of the curve pattern, the curve pattern includes two curved portions with opposite concave directions and connected into a whole, and the curved portion has a notch.
Optionally, in the mask of the flash memory device, the mask of the flash memory device further includes a word line contact hole mask, the word line contact hole mask includes a plurality of contact hole patterns, and the plurality of contact hole patterns respectively correspond to the plurality of recesses of the bending portion.
Based on the same inventive concept, the invention also provides a manufacturing method of the flash memory device, and the mask plate of the flash memory device comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage area and a peripheral area, and a floating gate oxide layer and a floating gate layer are sequentially formed on the semiconductor substrate;
an active region mask is adopted to define a first active region at the junction of the storage region and the peripheral region, and a plurality of second active regions are defined in the semiconductor substrate of the storage region and the peripheral region;
forming a control gate layer and a dielectric layer in sequence, wherein the control gate layer covers the floating gate layer;
etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the storage area by adopting a floating gate mask plate to form an opening, wherein part of the surface of the semiconductor substrate is exposed by the opening;
sequentially forming a tunneling oxide layer and a word line layer in the opening, wherein the tunneling oxide layer covers the inner wall of the opening, and the word line layer covers the tunneling oxide layer and fills the opening;
and etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer in the peripheral region, and stopping etching on the surface of the semiconductor substrate.
Optionally, in the method for manufacturing a flash memory device, the method for defining a first active region at an interface between the memory region and the peripheral region, and defining a plurality of second active regions in the semiconductor substrate of the memory region and the peripheral region includes:
etching the floating gate layer, the floating gate oxide layer and the semiconductor substrate by adopting the floating gate mask plate to form a shallow trench;
forming an isolation layer, wherein the isolation layer fills the shallow trenches to form shallow trench isolation structures, and the shallow trench isolation structures define the first active regions and the plurality of second active regions; the control gate layer also covers the shallow trench isolation structure.
Optionally, in the method for manufacturing a flash memory device, the method for etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the storage area to form an opening includes:
etching the dielectric layer by adopting the floating gate mask plate to form a first penetrating opening in the dielectric layer, wherein part of the control gate layer is exposed out of the first opening;
forming a first side wall, wherein the first side wall covers the side wall of the first opening;
etching the exposed control gate layer by taking the first side wall as a mask to form a penetrating second opening in the control gate layer and expose part of the floating gate layer;
forming a second side wall, wherein the second side wall covers the side wall of the second opening and extends to cover the first side wall;
etching the exposed floating gate layer by taking the second side wall as a mask to form a third opening, wherein the third opening extends into the floating gate oxide layer; wherein the third opening communicates with the second opening and the first opening and constitutes the opening.
Optionally, in the method for manufacturing a flash memory device, after etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer in the peripheral region, the method for manufacturing a flash memory device further includes:
removing the dielectric layer to expose the control gate layer covered by the dielectric layer;
and etching the exposed control gate layer, floating gate layer and floating gate oxide layer, and stopping etching on the surface of the semiconductor substrate to form a memory cell.
Optionally, in the method for manufacturing a flash memory device, after the memory cell is formed, the method for manufacturing a flash memory device further includes:
forming an interlayer film layer, wherein the interlayer film layer covers the memory cell;
and etching the interlayer film layer by using a word line contact hole mask plate to form a word line contact hole, wherein the word line contact hole is aligned to the word line layer.
In the mask plate of the flash memory device and the manufacturing method thereof provided by the invention, the mask plate of the flash memory device comprises an active region mask plate and a floating gate mask plate, and the active region mask plate comprises: the method comprises the steps of storing a mask plate area and a peripheral mask plate area, wherein a first active area pattern is arranged at the junction of the storing mask plate area and the peripheral mask plate area, a first active area is defined at the junction of the storing area and the peripheral area through the active area mask plate, and when etching a dielectric layer, a control gate layer, a floating gate layer and a floating gate oxide layer of the peripheral area, etching is stopped on the surface of a semiconductor substrate, because the first active area is defined at the junction of the storing area and the peripheral area, in the etching process, if over etching is generated, the etching object of the over etching is the semiconductor substrate of the first active area, compared with the prior art, the etching selection ratio can be improved, and therefore grooves on the side wall of a storage unit can be avoided, defects are avoided, and the performance of a flash memory device is improved.
Drawings
FIGS. 1-2 are schematic diagrams of prior art flash memory devices;
FIG. 3 is a schematic diagram of a mask of a flash memory device according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for manufacturing a flash memory device according to an embodiment of the present invention;
fig. 5 to 13 are schematic structural views formed by a method for manufacturing a flash memory device according to an embodiment of the present invention;
wherein, the reference numerals are as follows:
10-a semiconductor substrate; 20-floating gate oxide layer; 30-a floating gate layer; 40-shallow trench isolation structure; 50-a dielectric layer;
101-a mask of a flash memory device; 102-storing a mask region; 103-peripheral mask region; 104-a first active area pattern; 105-a second active area pattern; 106-floating gate patterns; 1041-curve graph; 1042-straight bar pattern; 107-contact hole patterns; 100-a semiconductor substrate; a 111-storage area; 112-peripheral region; 113-shallow trenches; 120-shallow trench isolation structures; 130-a floating gate oxide layer; 140-a floating gate layer; 150-a control gate layer; 160-a dielectric layer; 171-a first opening; 172-a first side wall; 173-a second opening; 174-a second side wall; 175-a third opening; 180-tunneling an oxide layer; 190-word line layer.
Detailed Description
The mask plate and the manufacturing method of the flash memory device provided by the invention are further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The inventor researches have found that the reason why the deep groove is formed at the boundary between the peripheral region and the storage region in the prior art is that when the shallow trench isolation structure is defined as the active region, the shallow trench isolation structure is generally formed between the storage region and the peripheral region, that is, the boundary between the storage region and the peripheral region is formed with the shallow trench isolation structure, and due to the existence of the shallow trench isolation structure, etching is stopped on the surface of the shallow trench isolation structure when the process layer between the storage region and the peripheral region is etched later (for example, when the storage unit is formed). Because the material of the shallow trench isolation structure is usually an oxide layer, the etching process has a low etching selectivity to the shallow trench isolation structure, and thus a large over-etching is caused, so that a deeper groove is formed at the junction of the storage region and the peripheral region, and the groove is easier to form defects. Based on the above, the invention provides a mask plate of a flash memory device and a manufacturing method thereof, so as to solve the defect problem caused by a groove at the junction of a peripheral region and a storage region of the flash memory device.
Next, a mask and a manufacturing method of the flash memory device provided by the present invention will be described in more detail with reference to embodiments and drawings.
Please refer to fig. 3, which is a schematic diagram of a mask structure of a flash memory device according to an embodiment of the present invention. As shown in fig. 3, the mask 101 of the flash memory device includes an active region mask, a floating gate mask, and a word line contact hole mask.
The active region mask comprises a storage mask region 102 and a peripheral mask region 103, a first active region graph 104 is formed at the junction of the storage mask region 102 and the peripheral mask region 103, and the first active region graph 104 extends along a first direction and is in a straight strip shape.
Specifically, a plurality of second active region patterns 105 are formed in the storage mask region 120 and the peripheral mask region 103, the plurality of second active region patterns 105 in the storage mask region 102 and the peripheral mask region 103 are arranged in parallel along the second direction, and spaces exist between the plurality of second active region patterns 105. Wherein the first direction is perpendicular to the second direction. The second active region patterns 105 may define an active region in the semiconductor substrate, a region between two adjacent second active region patterns 105, or a region between the second active region patterns 105 and the first active region patterns 104 may define an isolation region of the semiconductor substrate, for example, a shallow trench isolation structure of the isolation region. Here, the first active region pattern 104 and the second active region pattern 105 have the same size.
The floating gate mask is used for defining a floating gate on a semiconductor substrate. Specifically, the floating gate mask includes a plurality of floating gate patterns 106, where the plurality of floating gate patterns 106 are arranged in parallel along a first direction and cross the first active region pattern 104 along the second direction; further, the plurality of floating gate patterns 106 cross the plurality of second active region patterns 105 in the second direction.
Specifically, the floating gate pattern 106 includes a curved pattern 1014 and two straight stripe patterns 1042 connected to two ends of the curved pattern 1014, and the curved pattern 1014 includes two curved portions with opposite concave directions and integrally connected. Further, the curved pattern 1014 is S-shaped, and the process window of the contact hole can be increased by the S-shape of the curved pattern 1014. Here, the curved patterns 1014 of the adjacent two floating gate patterns 106 may be provided in a staggered manner, and the curved portions of the curved patterns 1014 of the adjacent two floating gate patterns 106 may be provided in a staggered manner.
The word line contact hole mask plate is used for forming a word line contact hole. Specifically, the word line contact hole mask includes a plurality of contact hole patterns 107, where the plurality of contact hole patterns 107 respectively correspond to the notches of the plurality of curved portions, that is, one contact hole pattern 107 corresponds to one notch of the curved portion, or, the projection of each contact hole pattern 107 is located in each notch of the curved portion.
Fig. 4 is a flowchart illustrating a method for manufacturing a flash memory device according to an embodiment of the invention. Based on the same inventive concept, the invention also provides a manufacturing method of the flash memory device, wherein the manufacturing method of the flash memory device adopts the mask plate of the flash memory device. As shown in fig. 4, the method for manufacturing the flash memory device includes:
step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage area and a peripheral area, and a floating gate oxide layer and a floating gate layer are sequentially formed on the semiconductor substrate;
step S2: an active region mask is adopted to define a first active region at the junction of the storage region and the peripheral region, and a plurality of second active regions are defined in the semiconductor substrate of the storage region and the peripheral region;
step S3: forming a control gate layer and a dielectric layer in sequence, wherein the control gate layer covers the floating gate layer;
step S4: etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the storage area by adopting a floating gate mask plate to form an opening, wherein part of the surface of the semiconductor substrate is exposed by the opening;
step S5, a tunneling oxide layer and a word line layer are sequentially formed in the opening, wherein the tunneling oxide layer covers the inner wall of the opening, and the word line layer covers the tunneling oxide layer and fills the opening;
and S6, etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the peripheral region, and stopping etching on the surface of the semiconductor substrate.
Next, the above steps will be described in more detail with reference to fig. 5 to 13, and fig. 5 to 13 are schematic structural views formed by the method for manufacturing a flash memory device according to the present invention.
First, as shown in fig. 5, step S1 is performed to provide a semiconductor substrate 100, the semiconductor substrate 100 including a memory region 111 and a peripheral region 112; the semiconductor substrate 100 is sequentially formed with a floating gate oxide layer 130 and a floating gate layer 140, the semiconductor substrate 100 provides an operation platform for the subsequent process, and the semiconductor substrate 100 may be made of silicon. Next, a floating gate oxide layer 130 may be formed on the surface of the semiconductor substrate 100 using low pressure chemical vapor deposition, atomic layer deposition, thermal oxidation, or molecular beam epitaxy, etc., and the material of the floating gate oxide layer 130 may be silicon oxide, for example, silicon dioxide, preferably silicon dioxide, to enhance interface adhesion between layers and for isolation between the semiconductor substrate 100 and the floating gate layer 140.
Next, a floating gate layer 140 may be formed on the floating gate oxide layer 130 by using a deposition method, and a material of the floating gate layer 140 may be polysilicon, which is used to form a floating gate, and electrons may be trapped or lost, so that the finally formed flash memory device has functions of storage and erasure.
Next, step S2 is performed, using an active area mask, to define a first active area at the interface between the storage area and the peripheral area, and define a plurality of second active areas in the semiconductor substrate of the storage area and the peripheral area.
Specifically, the method for defining a first active region at the juncture of the storage region and the peripheral region, and defining a plurality of second active regions in the semiconductor substrate of the storage region and the peripheral region comprises: the floating gate mask is used to etch the floating gate layer 140, the floating gate oxide layer 130 and the semiconductor substrate 100 to form the shallow trench 113. Further, the method for forming the shallow trench 113 includes: forming a pad silicon nitride layer (not shown) on the floating gate layer 140; then, forming a patterned photoresist layer on the pad nitride layer through the active region mask; next, the pad nitride layer, the floating gate layer 140, the floating gate oxide layer 130 and the semiconductor substrate 100 are etched by using the patterned photoresist layer as a mask, so as to form the shallow trench 113, i.e., the shallow trench 113 is located in the pad nitride layer, the floating gate layer 140, the floating gate oxide layer 130 and the semiconductor substrate 100. That is, the shallow trench 113 penetrates the pad nitride layer, the floating gate layer 140, and the floating gate oxide layer 130. The patterned photoresist layer is then removed.
Next, as shown in fig. 6, an isolation layer is formed, the isolation layer fills the shallow trench 113 to form a shallow trench isolation structure 120, and the shallow trench isolation structure 120 defines the first active region and the plurality of second active regions; and removing the pad nitride layer. Wherein the first active region and the second active region are the same size and are different in position.
Next, as shown in fig. 7, step S3 is performed, where a control gate layer 150 and a dielectric layer 160 are sequentially formed, and the control gate layer 150 covers the floating gate layer 140 and the shallow trench isolation structure 120; the control gate layer 150 may be a polysilicon layer for subsequent formation of control gates, and the dielectric layer 160 may be a nitride layer, for example, a silicon nitride layer. Preferably, an inter-gate dielectric layer is further formed between the floating gate layer 140 and the control gate layer 150, and the inter-gate dielectric layer may be silicon oxide or a stacked structure of first silicon oxide, silicon nitride and second silicon oxide (ONO), which is used for isolation between the floating gate layer 140 and the control gate layer 150. In this embodiment, for better understanding of the gist of the present invention, descriptions of variations of the inter-gate dielectric layer in each step are omitted, and illustration of the inter-gate dielectric layer is omitted in fig. 5 to 13.
Next, step S4 is performed, as shown in fig. 8 to fig. 9, to etch the dielectric layer 160, the control gate layer 150, the floating gate layer 140 and the floating gate oxide layer 130 of the storage region 111 by using a floating gate mask, so as to form an opening, where a portion of the surface of the semiconductor substrate 100 is exposed.
Specifically, the method for etching the dielectric layer 160, the control gate layer 150, the floating gate layer 140 and the floating gate oxide layer 130 of the storage region 11 to form the opening 160 includes: as shown in fig. 8, the floating gate mask is used to implement etching of the dielectric layer 160, so as to form a first opening 171 penetrating through the dielectric layer 160, where the first opening 171 exposes a portion of the control gate layer 150.
Then, as shown in fig. 9, a first sidewall layer 172 is formed, where the first sidewall layer 172 covers the sidewall of the first opening 171; then, etching the exposed control gate layer 150 with the first sidewall layer 172 as a mask to form a second opening 173 penetrating the control gate layer 150 and exposing a portion of the floating gate layer; next, a second sidewall layer 174 is formed, where the second sidewall covers the sidewall of the second opening 173 and extends to cover the first sidewall; then, as shown in fig. 10, the exposed floating gate layer is etched with the second sidewall 172 as a mask, so as to form a third opening 175, where the third opening 175 extends into the floating gate oxide layer 130; wherein the third opening 175 communicates with the second opening 173 and the first opening 171 and constitutes the openings, i.e., the openings include the first opening 171, the second opening 173, and the third opening 175. The material of the first sidewall 172 may be silicon oxide, and the material of the second sidewall 174 may be silicon nitride.
Next, as shown in fig. 11, step S5 is performed, and a tunnel oxide layer 180 and a word line layer 190 are sequentially formed in the opening 173, wherein the tunnel oxide layer 180 covers the inner walls of the opening (i.e., the side walls and the bottom wall of the opening), and the word line layer 190 covers the tunnel oxide layer 180 and fills the opening. The tunnel oxide layer 180 is used for isolation between the word line layer 190 and the floating gate layer 140, the control gate layer 150 and the semiconductor substrate 100.
Then, step S6 is performed, as shown in fig. 12, to etch the dielectric layer 160, the control gate layer 150, the floating gate layer 140 and the floating gate oxide layer 130 of the peripheral region 112, and stop on the surface of the semiconductor substrate 100 of the active region. Specifically, a patterned photoresist layer is formed, where the patterned photoresist layer covers the semiconductor substrate 100 in the storage region 111, i.e., the patterned photoresist layer covers the dielectric layer 160 and the word line layer 190 in the storage region 111. Then, the dielectric layer 160, the control gate layer 150, the floating gate layer 140 and the floating gate oxide layer 130 of the peripheral region 112 are etched using the patterned photoresist layer as a mask, and stopped on the surface of the semiconductor substrate 100 of the active region. Since the interface between the storage region 111 and the peripheral region 112 defines the first active region, etching can be stopped on the surface of the semiconductor substrate 100 in the first active region during etching. Because the material of the semiconductor substrate 100 is silicon, when overetching occurs in the etching process, the damage of the overetching to the semiconductor substrate 100 is small, compared with the prior art, the etching selection ratio of the etching process can be improved, so that the occurrence of grooves at the junction of the storage area 111 and the peripheral area 112 is avoided, further, the defect caused by the grooves is avoided, and the performance of the flash memory device is improved.
Next, as shown in fig. 13, the dielectric layer 160 is removed; then, the control gate layer 150 covered by the dielectric layer is exposed; next, the exposed control gate layer 150, floating gate layer 140 and floating gate oxide layer 130 are etched, and the etching is stopped on the surface of the semiconductor substrate 100 to form a memory cell.
Finally, forming an interlayer film layer, wherein the interlayer film layer covers the memory cell; then, a word line contact hole mask is used to etch the interlayer film layer to form a word line contact hole, and the word line contact hole is aligned to the word line layer 190. The word line contact hole exposes the surface of the word line layer 190, and then a conductive layer may be filled in the word line contact hole to form a word line contact structure, so that the word line is electrically connected to an external circuit through the word line contact structure, where the conductive layer may be made of metal, such as tungsten or copper.
In summary, in the mask and the manufacturing method of the flash memory device provided by the invention, the first active region can be defined at the junction of the storage region and the peripheral region through the active region mask, and when the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer in the peripheral region are etched and the etching is stopped on the surface of the semiconductor substrate, the first active region is defined at the junction of the storage region and the peripheral region, so that the etching is stopped on the surface of the semiconductor substrate in the first active region, and in the etching process, if overetching occurs, the etched object of the overetching is the semiconductor substrate in the first active region, compared with the prior art, the etching selection ratio can be improved, thereby avoiding the defects generated by the grooves and further improving the performance of the flash memory device.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (9)
1. A mask for a flash memory device, comprising:
the active region mask comprises a storage mask region and a peripheral mask region, and a first active region pattern is formed at the junction of the storage mask region and the peripheral mask region;
the floating gate mask plate comprises a plurality of floating gate patterns which are arranged in parallel along a first direction and cross the first active region pattern along a second direction, the floating gate patterns comprise a curve pattern and two straight strip patterns which are respectively connected with two ends of the curve pattern, the curve pattern comprises two curved portions which are concave oppositely and are connected into a whole, and the curved portion is provided with a notch.
2. The mask of claim 1, wherein a plurality of second active region patterns are formed in each of the storage mask region and the peripheral mask region, the plurality of second active region patterns in the storage mask region and the peripheral mask region being arranged in parallel along the second direction; wherein the first direction is perpendicular to the second direction.
3. The reticle of a flash memory device of claim 2, wherein the plurality of floating gate patterns span the plurality of second active region patterns along the second direction.
4. The mask of claim 1, further comprising a wordline contact mask, the wordline contact mask comprising a plurality of contact hole patterns, the plurality of contact hole patterns corresponding to the plurality of recesses of the flexure, respectively.
5. A method for manufacturing a flash memory device, using the mask of the flash memory device according to claim 1, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage area and a peripheral area, and a floating gate oxide layer and a floating gate layer are sequentially formed on the semiconductor substrate;
an active region mask is adopted to define a first active region at the junction of the storage region and the peripheral region, and a plurality of second active regions are defined in the semiconductor substrate of the storage region and the peripheral region;
forming a control gate layer and a dielectric layer in sequence, wherein the control gate layer covers the floating gate layer;
etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the storage area by adopting a floating gate mask plate to form an opening, wherein part of the surface of the semiconductor substrate is exposed by the opening;
sequentially forming a tunneling oxide layer and a word line layer in the opening, wherein the tunneling oxide layer covers the inner wall of the opening, and the word line layer covers the tunneling oxide layer and fills the opening;
and etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer in the peripheral region, and stopping etching on the surface of the semiconductor substrate.
6. The method of manufacturing a flash memory device of claim 5, wherein a first active region is defined at an interface of the memory region and the peripheral region, and wherein the method of defining a plurality of second active regions in the semiconductor substrate of the memory region and the peripheral region comprises:
etching the floating gate layer, the floating gate oxide layer and the semiconductor substrate by adopting the floating gate mask plate to form a shallow trench;
forming an isolation layer, wherein the isolation layer fills the shallow trenches to form shallow trench isolation structures, and the shallow trench isolation structures define the first active regions and the plurality of second active regions; the control gate layer also covers the shallow trench isolation structure.
7. The method of manufacturing a flash memory device of claim 5, wherein etching the dielectric layer, the control gate layer, the floating gate layer, and the floating gate oxide layer of the memory region to form openings comprises:
etching the dielectric layer by adopting the floating gate mask plate to form a first penetrating opening in the dielectric layer, wherein part of the control gate layer is exposed out of the first opening;
forming a first side wall, wherein the first side wall covers the side wall of the first opening;
etching the exposed control gate layer by taking the first side wall as a mask to form a penetrating second opening in the control gate layer and expose part of the floating gate layer;
forming a second side wall, wherein the second side wall covers the side wall of the second opening and extends to cover the first side wall;
etching the exposed floating gate layer by taking the second side wall as a mask to form a third opening, wherein the third opening extends into the floating gate oxide layer; wherein the third opening communicates with the second opening and the first opening and constitutes the opening.
8. The method of manufacturing a flash memory device of claim 5, wherein after etching the dielectric layer, the control gate layer, the floating gate layer, and the floating gate oxide layer of the peripheral region, the method of manufacturing a flash memory device further comprises:
removing the dielectric layer to expose the control gate layer covered by the dielectric layer;
and etching the exposed control gate layer, floating gate layer and floating gate oxide layer, and stopping etching on the surface of the semiconductor substrate to form a memory cell.
9. The method of manufacturing a flash memory device of claim 8, wherein after forming the memory cell, the method of manufacturing a flash memory device further comprises:
forming an interlayer film layer, wherein the interlayer film layer covers the memory cell;
and etching the interlayer film layer by using a word line contact hole mask plate to form a word line contact hole, wherein the word line contact hole is aligned to the word line layer.
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| CN1862820A (en) * | 2005-05-11 | 2006-11-15 | 海力士半导体有限公司 | Flash memory device and method of manufacturing the same |
| CN1913160A (en) * | 2005-08-08 | 2007-02-14 | 海力士半导体有限公司 | Flash memory device and method of fabricating the same |
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| CN1862820A (en) * | 2005-05-11 | 2006-11-15 | 海力士半导体有限公司 | Flash memory device and method of manufacturing the same |
| CN1913160A (en) * | 2005-08-08 | 2007-02-14 | 海力士半导体有限公司 | Flash memory device and method of fabricating the same |
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