CN112071252B - Source electrode driving circuit and display device - Google Patents
Source electrode driving circuit and display device Download PDFInfo
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- CN112071252B CN112071252B CN202010965768.8A CN202010965768A CN112071252B CN 112071252 B CN112071252 B CN 112071252B CN 202010965768 A CN202010965768 A CN 202010965768A CN 112071252 B CN112071252 B CN 112071252B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The invention provides a source electrode driving circuit and a display device, comprising a plurality of control switch elements and a time sequence control signal generating module; a first path end of each control switch element receives a source electrode driving signal, a control end of each control switch element receives a time sequence control signal, and a second path end of each control switch element is connected with a corresponding data line; the timing control signal has at least two falling edges or two rising edges in one period, each control switch element is turned on when the timing control signal is at an on potential, so that the source driving signal is transmitted to the corresponding data line through the turned-on control switch element, and each control switch element is turned off when the timing control signal is at an off potential. The source driving circuit and the time sequence control signal in the display device have at least two falling edges or two rising edges in one period, so that the conduction time of the control switch element is more similar, and the uniformity of the brightness of a display picture is improved.
Description
Technical Field
The present invention relates to the field of display, and in particular, to a source driving circuit and a display device.
Background
Because the display device has many advantages of lightness, thinness, energy saving, no radiation and the like, the display device is widely applied to electronic equipment such as televisions, personal computers, tablet computers, personal Digital Assistants (PDAs), mobile phones, digital cameras and the like. A display device generally includes a gate driving circuit, a source driving circuit, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units formed by crossing the plurality of scan lines and the plurality of data lines. The plurality of scanning lines are connected to a gate driving circuit, and the gate driving circuit provides gate driving signals for the plurality of pixel units through the plurality of scanning lines. The plurality of data lines are connected to a source driving circuit, and the source driving circuit provides source driving signals, namely display signals, for the plurality of pixel units through the plurality of data lines.
Specifically, the source driving circuit controls the on and off of the switching element through the timing control signal, so as to control whether to output the source driving signal to the corresponding pixel unit, i.e., control the charging time of the pixel unit.
However, due to the influence of the resistance and capacitance of the circuit, the waveform of the conventional timing control signal at the far end is more and more distorted, so that the conduction time lengths of the control switch element at the near end and the control switch element at the far end are different, and further, the charging time lengths of the pixel units at the near end and the far end are different, namely, the brightness difference exists, and the uniformity of the brightness of a display picture is influenced.
Disclosure of Invention
The present invention provides a source driving circuit to solve the problem of poor uniformity of image brightness caused by different on-time of the control switch element in the source driving circuit in the prior art.
The invention provides a source electrode driving circuit, which comprises a plurality of control switch elements and a time sequence control signal generation module; the first path end of each control switch element receives a source electrode driving signal, the control end of each control switch element receives the time sequence control signal generated by the time sequence control signal generating module, and the second path end of each control switch element is connected with the corresponding data line; the timing control signal has at least two falling edges or two rising edges in one period, each control switch element is turned on when the timing control signal is at an on potential, so that the source driving signal is transmitted to the corresponding data line through the turned-on control switch element, each control switch element is turned off when the timing control signal is at an off potential, and the off potentials are at least two.
In one embodiment, the plurality of control switching elements are divided into odd-numbered control switching elements and even-numbered control switching elements, the timing control signal is divided into an odd-numbered timing control signal and an even-numbered timing control signal, the control terminal of the odd-numbered control switching element receives the odd-numbered timing control signal, and the control terminal of the even-numbered control switching element receives the even-numbered timing control signal.
In one embodiment, the odd bit timing control signal and the even bit timing control signal are inverse signals.
In one embodiment, the first pass terminals of every two adjacent control switch elements are connected to the same signal output port of the source driver chip.
In one embodiment, the plurality of control switch elements are all N-type MOS transistors.
In one embodiment, the on potential is a high potential and the off potential is a low potential.
In one embodiment, the timing control signal generation module is configured to output the timing control signal, and the timing control signal generation module includes: a first switch element, a first resistor and a first diode; the control end of the first switch element receives a first control signal, the first path end of the first switch element receives an initial timing signal, and the second path end of the first switch element is connected with the cathode of the first diode and used for outputting the timing control signal; a first end of the first resistor is connected with a first direct-current voltage source, and a second end of the first resistor is connected with a second path end of the first switching element; the anode of the first diode is grounded.
In one embodiment, the timing control signal generating module includes: the circuit comprises a second switching element, a third switching element, a voltage follower, a second resistor, a third resistor and a fourth resistor; the control end of the second switch element receives a first control signal, the first path end of the second switch element receives an initial timing signal through the second resistor, and the second path end of the second switch element is grounded; a control end of the third switching element receives the first control signal, a first path end of the third switching element receives an initial timing signal through the third resistor and the fourth resistor, and a second path end of the third switching element is connected with a first path end of the second switching element; the first input end of the voltage follower is connected with the common end of the third resistor and the fourth resistor, the second input end of the voltage follower is connected with the output end of the voltage follower, and the output end of the voltage follower is used for outputting the sequential control signal.
The invention also provides a display device which comprises the source electrode driving circuit.
The source driving circuit and the time sequence control signal in the display device have at least two falling edges or two rising edges in one period, so that the conduction time of the control switch element is more similar, and the uniformity of the brightness of a display picture is improved.
Drawings
Fig. 1 is a schematic structural diagram of a source driver circuit according to an embodiment of the invention.
FIG. 2 is a timing diagram of a timing control signal according to an embodiment of the present invention and a timing control signal according to the prior art.
Fig. 3 is a circuit diagram of a timing control signal generating module according to an embodiment of the invention.
Fig. 4 is a circuit diagram of a timing control signal generating module according to another embodiment of the invention.
FIG. 5 is a timing diagram of signals in the timing control signal generating module according to an embodiment of the invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of embodiments, methods, steps, structures, features and effects of the source driving circuit and the display device according to the present invention will be made with reference to the accompanying drawings and preferred embodiments.
The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. While the present invention has been described in connection with the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications, equivalent arrangements, and specific embodiments thereof.
Fig. 1 is a schematic structural diagram of a source driver circuit according to an embodiment of the invention. As shown in fig. 1, the present invention provides a source driving circuit, which includes a plurality of control switch elements, and specifically, the control switch elements may be all N-type MOS transistors. The first path end of each control switch element receives a source driving signal, the control end of each control switch element receives a timing control signal SW, and the second path end of each control switch element is connected with a corresponding data line Sn. The timing control signal SW has at least two falling edges or two rising edges in one period, each control switch element is turned on when the timing control signal SW is at an on potential, so that the source driving signal is transmitted to the corresponding data line Sn through the turned-on control switch element, and each control switch element is turned off when the timing control signal SW is at an off potential, the on potential is, for example, a first potential, and the off potential includes at least 2 potentials, for example, a second potential and a third potential.
FIG. 2 is a timing diagram of timing control signals according to an embodiment of the invention. Referring to fig. 1 and fig. 2, the timing control signal SW has at least two falling edges in one period. Each control switch element T is turned on when the timing control signal SW is at a first high potential, so that the source driving signal is transmitted to the corresponding data line Sn through the turned-on control switch element T1, and each control switch element T is turned off when the timing control signal SW is at a first low potential and a second low potential. Of course, in other embodiments, the timing control signal has three falling edges in one period, i.e. correspondingly, the off-potential includes three potentials.
In one embodiment, the plurality of control switch elements T are divided into odd-numbered control switch elements T1 and even-numbered control switch elements T2, the timing control signal SW is divided into odd-numbered timing control signals SW1 and even-numbered timing control signals SW2, a control terminal of the odd-numbered control switch element T1 receives the odd-numbered timing control signal SW1, and a control terminal of the even-numbered control switch element T2 receives the even-numbered timing control signal SW2. In addition, the source driving signals received by the first path terminals of every two adjacent control switching elements T1, T2 are the same (the source driving signals are provided by a source driving chip (source IC)). In other embodiments, every adjacent three control switch elements of the plurality of control switch elements T are grouped into one group, the control switch elements of the odd group receive the odd bit timing control signal SW1, and the control switch elements of the even group receive the odd bit timing control signal SW2. The source driving signals received by the first path end of each group of control switch elements are the same.
In one embodiment, the odd bit timing control signal SW1 and the even bit timing control signal SW2 are inverse signals. In other embodiments, the odd bit timing control signal SW1 and the even bit timing control signal SW2 may be in-phase signals.
Since the timing control signal SW received by the control switch element T in the source driving circuit of this embodiment has at least two falling edges in one period, each control switch element T is turned on when the timing control signal SW is at a first high potential, so that the source driving signal is transmitted to the corresponding data line Sn through the turned-on control switch element T1, and each control switch element T is turned off when the timing control signal SW is at a first low potential and a second low potential, the problem of uneven picture brightness caused by different charging durations of the pixel units due to distortion of a waveform SW 'of the remote timing control signal (a waveform SW' is slowly gradually changed from a high level to a low level instead of an ideal falling edge) in the prior art is avoided.
Fig. 3 is a circuit diagram of a timing control signal generating module according to an embodiment of the invention. As shown in fig. 3, the first timing control signal generating module is configured to output a timing control signal, and the first timing control signal generating module includes: the circuit includes a first switching element Q1, a first resistor R1, and a first diode D1.
Specifically, a control terminal of the first switch element Q1 receives the first control signal GPIO, a first path terminal of the first switch element Q1 receives the initial timing signal VCC1, and a second path terminal of the first switch element Q1 is connected to a cathode of the first diode D1 and is configured to output the timing control signal SW. A first end of the first resistor R1 is connected to the first dc voltage source VCC2, and a second end of the first resistor R2 is connected to the second path end of the first switching element Q1. The anode of the first diode D1 is grounded.
The voltage value of the first high potential of the timing control signal SW is determined by the voltage value of the high potential of the initial timing signal VCC1, the voltage value of the first low potential of the timing control signal SW is determined by the voltage value of the first direct-current voltage source VCC2, and the duration of the timing control signal SW maintained at the first low potential is the same as the duration of the first control signal GPIO maintained at the high potential. Fig. 5 is a timing diagram of signals in the timing control signal generation module according to an embodiment of the invention. Referring to fig. 3 and fig. 5, the operation principle of the timing control signal generating module shown in fig. 3 can be, but is not limited to, the following:
1. when the first control signal GPIO is at a low level, the initial timing signal VCC1 is at a high level, the first switch element Q1 is turned on, and the timing control signal SW is pulled up by the initial timing signal VCC1 through the turned-on first switch element Q1 (the voltage of the timing control signal SW follows the voltage of the initial timing signal VCC 1).
2. When the first control signal GPIO changes from low level to high level, the first switch element Q1 is turned off, and the timing control signal SW is pulled down by the first dc voltage source VCC2 (the voltage of the timing control signal SW follows the voltage of the first dc voltage source VCC 2).
3. When the first control signal GPIO changes from high level to low level, the initial timing signal VCC1 changes from high level to low level, the first switch element Q1 is turned on, and the timing control signal SW is further pulled down by the initial timing signal VCC1 through the turned-on first switch element Q1 (the voltage of the timing control signal SW follows the voltage of the initial timing signal VCC 1).
Fig. 4 is a circuit diagram of a timing control signal generating module according to another embodiment of the invention. As shown in fig. 4, the timing control signal generating module includes: a second switching element Q2, a third switching element Q3, a voltage follower U1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The control terminal of the second switching element Q2 receives the first control signal GPIO, the first path terminal of the second switching element Q2 receives the initial timing signal VCC1 through the second resistor R2, and the second path terminal of the second switching element Q2 is grounded. A control terminal of the third switching element Q3 receives the first control signal GPIO, a first path terminal of the third switching element Q3 receives the initial timing signal VCC1 through the third resistor R3 and the fourth resistor R4, and a second path terminal of the third switching element Q3 is connected to a first path terminal of the second switching element Q2. The first input end of the voltage follower U1 is connected with the common end of the third resistor R3 and the fourth resistor R4, the second input end of the voltage follower U1 is connected with the output end of the voltage follower U2, and the output end of the voltage follower U2 is used for outputting a time sequence control signal SW.
Referring to fig. 4 and fig. 5, the operation principle of the timing control signal generating module shown in fig. 4 can be, but is not limited to, the following:
1. when the first control signal GPIO is at a low level, the initial timing signal VCC1 is at a high level, the second switching element Q2 and the third switching element Q3 are turned off, and the timing control signal SW is pulled up by the initial timing signal VCC1 (the voltage of the timing control signal SW follows the voltage of the initial timing signal VCC 1).
2. When the first control signal GPIO changes from low level to high level, the second switch element Q2 and the third switch element Q3 are turned on, and the timing control signal SW is pulled low.
3. When the first control signal GPIO changes from high level to low level, the initial timing signal VCC1 is low level, the second switch element Q2 and the third switch element Q3 are turned off, and the timing control signal SW is further pulled down by the initial timing signal VCC1 (the voltage of the timing control signal SW follows the voltage of the initial timing signal VCC 1).
The source driving circuit and the time sequence control signal in the display device have at least two falling edges or two rising edges in one period, so that the conduction time of the control switch element is more similar, and the uniformity of the brightness of a display picture is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A source driving circuit comprises a plurality of control switch elements and a timing control signal generating module;
the first path end of each control switch element receives a source electrode driving signal, the control end of each control switch element receives the time sequence control signal generated by the time sequence control signal generating module, and the second path end of each control switch element is connected with the corresponding data line;
the timing control signal has at least two falling edges or two rising edges in one period, each control switch element is turned on when the timing control signal is at an on potential, so that the source driving signal is transmitted to the corresponding data line through the turned-on control switch element, each control switch element is turned off when the timing control signal is at an off potential, the number of the off potentials is at least two, and the number of the off potentials is the same as the number of the falling edges or the rising edges in one period.
2. The source driving circuit of claim 1, wherein the plurality of control switching elements are divided into odd-numbered bit control switching elements and even-numbered bit control switching elements, the timing control signals are divided into odd-numbered bit timing control signals and even-numbered bit timing control signals, the control terminals of the odd-numbered bit control switching elements receive the odd-numbered bit timing control signals, and the control terminals of the even-numbered bit control switching elements receive the even-numbered bit timing control signals.
3. The source driving circuit of claim 2, wherein the odd bit timing control signal and the even bit timing control signal are inverse signals.
4. The source driver circuit according to claim 1, wherein the source driver circuit further comprises a source driver chip;
the first path ends of every two adjacent control switch elements are connected with the same signal output port of the source driving chip.
5. The source driver circuit as claimed in claim 1, wherein the plurality of control switching elements are all N-type MOS transistors.
6. The source driver circuit according to claim 5, wherein the on potential is a high potential, and the off potential is a low potential.
7. The source driver circuit of claim 6, wherein the timing control signal has three falling edges in the one period, and the off potential comprises three potentials.
8. The source driving circuit of claim 6, wherein the timing control signal generation module is configured to output the timing control signal, and the timing control signal generation module comprises: a first switch element, a first resistor and a first diode;
the control end of the first switch element receives a first control signal, the first path end of the first switch element receives an initial timing signal, and the second path end of the first switch element is connected with the cathode of the first diode and used for outputting the timing control signal;
a first end of the first resistor is connected with a first direct-current voltage source, and a second end of the first resistor is connected with a second path end of the first switching element;
the anode of the first diode is grounded.
9. The source driving circuit of claim 6, further comprising a second timing control signal generation module, the timing control signal generation module being configured to output the timing control signal, the timing control signal generation module comprising: the circuit comprises a second switching element, a third switching element, a voltage follower, a second resistor, a third resistor and a fourth resistor;
the control end of the second switch element receives a first control signal, the first path end of the second switch element receives an initial timing signal through the second resistor, and the second path end of the second switch element is grounded;
a control end of the third switching element receives the first control signal, a first pass end of the third switching element receives an initial timing signal through the third resistor and the fourth resistor, and a second pass end of the third switching element is connected with a first pass end of the second switching element;
the first input end of the voltage follower is connected with the common end of the third resistor and the fourth resistor, the second input end of the voltage follower is connected with the output end of the voltage follower, and the output end of the voltage follower is used for outputting the sequential control signal.
10. A display device, characterized in that the display device comprises the source driver circuit according to any one of claims 1 to 9.
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| CN202010965768.8A CN112071252B (en) | 2020-09-15 | 2020-09-15 | Source electrode driving circuit and display device |
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| CN202010965768.8A CN112071252B (en) | 2020-09-15 | 2020-09-15 | Source electrode driving circuit and display device |
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| CN101510398A (en) * | 2008-02-15 | 2009-08-19 | 中华映管股份有限公司 | Source electrode drive circuit |
| CN101944344B (en) * | 2010-09-09 | 2012-12-26 | 昆山龙腾光电有限公司 | Grid drive circuit |
| TWI512380B (en) * | 2013-03-21 | 2015-12-11 | Au Optronics Corp | Display apparatus and method for operating that |
| CN103855192B (en) * | 2014-02-20 | 2016-04-13 | 深圳市华星光电技术有限公司 | A kind of AMOLED display device and image element driving method thereof |
| CN107146587A (en) * | 2017-06-21 | 2017-09-08 | 昆山龙腾光电有限公司 | Source electrode drive circuit and display panel |
| CN107831614A (en) * | 2017-11-07 | 2018-03-23 | 深圳市华星光电半导体显示技术有限公司 | Pixel driving framework and display device |
| CN107767809B (en) * | 2017-11-15 | 2019-11-26 | 鄂尔多斯市源盛光电有限责任公司 | Drive element of the grid, driving method and gate driving circuit |
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