CN112068781A - Data reading and writing method of memory and related equipment - Google Patents
Data reading and writing method of memory and related equipment Download PDFInfo
- Publication number
- CN112068781A CN112068781A CN202010947859.9A CN202010947859A CN112068781A CN 112068781 A CN112068781 A CN 112068781A CN 202010947859 A CN202010947859 A CN 202010947859A CN 112068781 A CN112068781 A CN 112068781A
- Authority
- CN
- China
- Prior art keywords
- bad column
- memory
- data
- bit
- byte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 192
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000012360 testing method Methods 0.000 claims description 17
- 238000012545 processing Methods 0.000 claims description 12
- 238000005215 recombination Methods 0.000 claims description 6
- 230000006798 recombination Effects 0.000 claims description 6
- 230000004044 response Effects 0.000 claims description 5
- 238000012937 correction Methods 0.000 abstract description 18
- 230000008569 process Effects 0.000 description 9
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 238000004590 computer program Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000005291 magnetic effect Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 210000000707 wrist Anatomy 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 239000013598 vector Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The application provides a data reading and writing method of a memory and related equipment, which can maximize the utilization of the NandFlash capacity, can contain more ECC redundant data, improve the error correction capability and enhance the NandFlash data stability. The method comprises the following steps: acquiring a read instruction or a write instruction for a memory, wherein the read instruction or the write instruction corresponds to target data; determining bad column position information of the memory, wherein the bad column position information of the memory indicates position information of a bit bad column in the memory; and responding to the reading instruction or the writing instruction, and performing reading operation or writing operation on the target data according to the bad column position information.
Description
Technical Field
The present application relates to the field of storage, and in particular, to a data reading and writing method for a memory and a related device.
Background
The Nand-Flash memory is one of Flash memories, and a nonlinear macro-unit mode is adopted in the Nand-Flash memory, so that a cheap and effective solution is provided for realizing a solid-state large-capacity memory. The Nand-Flash memory has the advantages of large capacity, high rewriting speed and the like, and is suitable for storing a large amount of data, so that the Nand-Flash memory is more and more widely applied in the industry, for example, embedded products comprise a digital camera, an MP3 walkman memory card, a small-sized U disk and the like.
NandFlash has physical characteristics that errors occur with a certain probability in the data read-write process, so that an ECC (Error correction Code, which is a technology capable of realizing Error check and correction) is provided for detecting and Correcting data errors only by a corresponding Error detection and correction mechanism. And if the number of bad columns in the NandFlash exceeds the error correction capability of an error correction algorithm, the error correction is carried out by increasing the ECC error correction capability.
However, if the ECC error correction capability is increased to perform error correction, the complexity of the ECC module is increased dramatically, which not only results in slower frequency of the ECC module, but also significantly increases the chip area. More extra capacity is needed to store redundant data, and the length of one page of NandFlash is fixed and cannot be increased at will.
Disclosure of Invention
The application provides a data reading and writing method of a memory and related equipment, which can maximize the utilization of the NandFlash capacity, can contain more ECC redundant data, improve the error correction capability and enhance the NandFlash data stability.
A first aspect of the present application provides a data reading and writing method for a memory, including:
acquiring a read instruction or a write instruction for a memory, wherein the read instruction or the write instruction corresponds to target data;
determining bad column position information of the memory, wherein the bad column position information of the memory indicates position information of a bit bad column in the memory;
and responding to the reading instruction or the writing instruction, and performing reading operation or writing operation on the target data according to the bad column position information.
Optionally, the determining the bad column location information of the memory includes:
writing test data to the memory;
reading data from the memory to obtain first data;
comparing the first data with the test data to determine a bit bad column position of each page in the memory;
and determining position information corresponding to a target bit position as bad column position information of the memory, wherein the target bit position is a bit position with the same bit bad column position in a plurality of pages in the memory.
Optionally, the method further comprises:
determining a byte bad column set of the memory and a bit bad column corresponding to each byte bad column in the byte bad column set according to the bad column position information;
generating a byte bad column template corresponding to the memory according to the byte bad column set of the memory;
and generating a bit bad column template corresponding to the memory according to the bit bad column corresponding to each byte bad column in the byte bad column set.
Optionally, the writing the target data according to the bad column position information in response to the write instruction includes:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a first bit bad column corresponding to each byte bad column in the byte bad column set;
inserting invalid data into the first bit bad column to obtain a second bit bad column;
and recombining the target data and the data corresponding to the second bit bad column and writing the recombined data into the memory.
Optionally, the reading, in response to the read instruction, the target data according to the bad column position information includes:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a third bit bad column corresponding to each byte bad column in the byte bad column set;
reading the target data according to the reading instruction, wherein the target data is data which is stored in the memory and corresponds to the reading instruction;
and performing data recombination on data except the data corresponding to the third bit bad column in the target data to finish the reading operation of the target data.
A second aspect of the present application provides a data reading and writing apparatus for a memory, including:
an acquisition unit configured to acquire a read instruction or a write instruction for a memory, the read instruction or the write instruction corresponding to target data;
the determining unit is used for determining the bad column position information of the memory, and the bad column position information of the memory indicates the position information of the bit bad column in the memory;
and the processing unit is used for responding to the reading instruction or the writing instruction and performing reading operation or writing operation on the target data according to the bad column position information.
Optionally, the determining unit is specifically configured to:
writing test data to the memory;
reading data from the memory to obtain first data;
comparing the first data with the test data to determine a bit bad column position of each page in the memory;
and determining position information corresponding to a target bit position as bad column position information of the memory, wherein the target bit position is a bit position with the same bit bad column position in a plurality of pages in the memory.
Optionally, the apparatus further comprises:
a template generation unit to:
determining a byte bad column set of the memory and a bit bad column corresponding to each byte bad column in the byte bad column set according to the bad column position information;
generating a byte bad column template corresponding to the memory according to the byte bad column set of the memory;
and generating a bit bad column template corresponding to the memory according to the bit bad column corresponding to each byte bad column in the byte bad column set.
Optionally, the processing unit is specifically configured to:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a first bit bad column corresponding to each byte bad column in the byte bad column set;
inserting invalid data into the first bit bad column to obtain a second bit bad column;
and recombining the target data and the data corresponding to the second bit bad column and writing the recombined data into the memory.
Optionally, the processing unit is further specifically configured to:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a third bit bad column corresponding to each byte bad column in the byte bad column set;
reading the target data according to the reading instruction, wherein the target data is data which is stored in the memory and corresponds to the reading instruction;
and performing data recombination on data except the data corresponding to the third bit bad column in the target data to finish the reading operation of the target data.
A third aspect of the present application provides a computer apparatus, which includes at least one connected processor and a memory, where the memory is used to store a program code, and the program code is loaded and executed by the processor to implement the steps of the data reading and writing method of the memory described above.
A fourth aspect of the present application provides a computer-readable storage medium, which includes instructions that, when executed on a computer, cause the computer to perform the steps of the method for reading and writing data of the memory described above.
To sum up, in the embodiment provided by the application, the bit bad column position information in the NandFlash is determined, and then the data read-write operation is performed according to the bit bad column position information, so that the NandFlash capacity can be maximally utilized, and meanwhile, when error correction is performed through the ECC, more ECC redundant data can be accommodated, the error correction capability is improved, and the NandFlash data stability is enhanced.
Drawings
FIG. 1 is a block diagram of a byte bad column template and a bit bad column template according to an embodiment of the present disclosure;
FIG. 2 is a flowchart illustrating a data reading/writing method of a memory according to an embodiment of the present disclosure;
fig. 3 is a schematic view of a virtual structure of a data read/write apparatus of a memory according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a server according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprise," "include," and "have," and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules expressly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus, the division of modules presented herein is merely a logical division that may be implemented in a practical application in a further manner, such that a plurality of modules may be combined or integrated into another system, or some feature vectors may be omitted, or not implemented, and such that couplings or direct couplings or communicative coupling between each other as shown or discussed may be through some interfaces, indirect couplings or communicative coupling between modules may be electrical or other similar, this application is not intended to be limiting. The modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in a plurality of circuit modules, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present disclosure.
Referring to fig. 1, fig. 1 is a schematic flow chart of a data reading and writing method of a memory provided in an embodiment of the present application, including:
101. a read instruction or a write instruction directed to the memory is fetched.
In this embodiment, the data read/write device of the memory obtains a read instruction or a write instruction for the memory, where the read instruction or the write instruction corresponds to the target data, that is, the read instruction is an instruction to read the target data from the memory, and the write instruction is an instruction to write the target data into the memory. The reading instruction or the writing instruction for the memory is not limited to be obtained specifically here, for example, when a user needs to read data from the memory or write data into the memory, the memory may receive the reading instruction or the writing instruction corresponding to the user. It is understood that the memory may be NandFlash.
In one embodiment, the operation of generating the read command or the write command includes at least one of a gesture operation, a sliding operation, a clicking operation, and a voice control operation, for example, when a user performs a clicking operation, the data read/write device of the memory may receive the clicking operation, and at this time, the clicking operation generates the read command or the write command, that is, the operation command may be defined in advance, for example, the sliding operation is defined in advance as an operation of reading corresponding data from the memory or writing corresponding data (e.g., a left-sliding operation, a right-sliding operation, a top-sliding operation, a bottom-sliding operation, and the like), or the clicking operation is defined as an operation of reading corresponding data from the memory or writing corresponding data (e.g., a double-clicking operation, a mouse-sliding operation, a long-pressing operation, a single-clicking operation, a simultaneous pressing operation of left and right keys of the mouse, a middle key of the scroll wheel mouse, and the Swinging the wrist or arm, swinging the wrist or arm to the right, such as a four-finger pinch operation or a three-finger slide-up operation, etc.), or defining a voice control operation as an operation of displaying an image display area and/or an attribute display area (such as receiving a sound of reading or writing data, and a sound of specific data to be read or written), which are merely examples and do not represent a limitation on the operation of generating a read instruction or a write instruction. Of course, the read instruction or the write instruction may also be generated by setting a corresponding shortcut key on an input device, for example, the input device is a keyboard, and the "CTRL + a key" on the keyboard is set as an operation for generating the read instruction or the write instruction, which is not limited specifically.
102. Bad column location information of the memory is determined.
In this embodiment, the data reading and writing device of the memory may determine to fetch the bad column position information of the memory, that is, the data reading and writing device of the memory may determine the bad column position information of the memory in a manner of writing data into the memory and reading the data in advance, and store the bad column position information. The memory stores the corresponding bad column position information, namely the position information corresponding to the bit bad column in the memory.
In one embodiment, the determining the bad column position information of the memory by the data reading and writing device of the memory comprises:
writing the test data to the memory;
reading data from a memory to obtain first data;
comparing the first data with the test data to determine the bit bad column position of each page in the memory;
and determining the position information corresponding to the target bit position as the bad column position information of the memory, wherein the target bit position is the bit position with the same bit bad column position in a plurality of pages in the memory.
In this embodiment, the data reading and writing device of the memory may write test data into the memory, then read data from the memory to obtain first data, then compare the first data with the test data to determine a bit bad column position of each page in the memory, and determine position information corresponding to a target bit position as bad column position information of the memory, where the target bit position is a bit position with the same bit bad column position in multiple pages in the memory. The memory is described as NandFlash as an example, when the NandFlash is scanned, test data is written into the NandFlash, and then the test data is read out, and the abnormality between the written test data and the read-out data is compared, so that the position information of the bad column with the error is found out. The data of the NandFlash is stored in a memory cell in a bit mode, and generally, only one bit can be stored in one cell. These cells are connected into bit lines in units of 8 or 16 cells, forming the bit width of the NAND Device. These lines will be grouped into pages, each 528Byte, each 32 pages form a Block, and NandFlash reads and writes data in Page units and erases data in Block units. For NandFlash, the bad column position information of different pages is slightly different, and here, the position with a higher bad column probability is found by combining the bad column position information in all pages in the block (that is, one Flash block has multiple pages, which can be analyzed by data writing and reading, and which positions in each page have errors, if an error occurs in the same position of multiple different pages, the position is considered to be a true bad column, the multiple pages may be, for example, 5 pages, of course, it may also be set according to actual conditions, and it is specifically not limited, for example, the memory includes 100 pages, where 20 pages have errors in the same a position, the position information corresponding to the a position is the bad column position information corresponding to the memory, which is described above by way of example only and does not represent a limitation thereto), and the position is determined to be a true bad column, so that the bad column position information of the memory is obtained.
In one embodiment, after determining the bad column location information of the memory, the data reading and writing device of the memory further performs the following operations:
determining a byte bad column set of a memory and a bit bad column corresponding to each byte bad column in the byte bad column set according to the bad column position information;
generating a byte bad column template corresponding to the memory according to the byte bad column set of the memory;
and generating a bit bad column template corresponding to the memory according to the bit bad column corresponding to each byte bad column in the byte bad column set.
In this embodiment, the data reading and writing device of the memory may determine the byte bad column set of the memory and the bit bad column corresponding to each byte bad column in the byte bad column set according to the bad column position information of the memory, that is, after knowing the bad column position information in the memory, it may be known that the byte in the memory to which the bad column position information belongs has an error and the bit in the byte has an error, and then may generate the byte bad column template corresponding to the memory according to the byte bad column set of the memory, and generate the bit bad column template corresponding to the memory according to the bit bad column corresponding to each byte bad column in the byte bad column set.
Referring to fig. 2, fig. 2 is a schematic diagram of a byte bad column template and a bit bad column template according to an embodiment of the present application, where 201 in fig. 2 is the byte bad column template, and 202 is the bit bad column template. For each byte in the memory, if one or more bits are bad, the byte is marked as a byte bad column, thereby forming a level byte bad column template. Each element in this byte bad column template is represented by a 0 for a non-bad column and a 1 for a bad column, such as 201 in FIG. 2. And for each byte bad column in the memory, writing the information of each bit bad column in the byte into a new table to form a secondary bit bad column template. Each bit bad column data needs to represent 8 bits of information, such as 202 in fig. 2, but the bit bad column regularity of NandFlash generally differs according to the rule, and 1/2/4/8 bits can be used to form each element in the secondary bit bad column template. That is, how many byte bad column templates are generated as many byte bad columns exist in the memory, and each byte bad column template corresponds to one bit bad column template.
103. And responding to the reading instruction or the writing instruction, and performing reading operation or writing operation on the target data according to the bad column position information.
In this embodiment, the data reading and writing device of the memory may perform a reading operation or a writing operation on the target data according to the bad column position information in response to the reading instruction or the writing instruction. The following is a detailed description of the read or write operation:
1. and (3) writing operation:
the data reading and writing device of the memory responds to the writing instruction, and the writing operation of the target data according to the bad column position information comprises the following steps:
searching a byte bad column template to determine a byte bad column set in a memory;
searching a bit bad column template to determine a first bit bad column corresponding to each byte bad column in a byte bad column set;
inserting the first bit bad column into invalid data to obtain a second bit bad column;
and recombining the target data and the data corresponding to the second bit bad column and writing the recombined data into the memory.
In this embodiment, when writing data, the data reading and writing device of the memory may determine a bit-bad column by detecting the byte-bad column template and the bit-bad column template, insert invalid data into the bit-bad column, and write the target data and the data of the bit-bad column into which the invalid data is inserted into the memory after being recombined, thereby completing writing the data. It can be understood that, when the data read-write device of the memory searches the bad column template, firstly, data is read from the first-level byte bad column template, whether each byte is a bad column is judged, if the byte is a bad column, data is sequentially read from the second-level bit bad column template, which bits of the byte are bad columns is judged, finally, a bit bad column corresponding to each byte bad column in the byte bad column set and the byte bad column combination is determined, then, invalid data is inserted into all bad column positions, and after being recombined with valid data to be written, NandFlash is written, for example, when the true valid data to be written, such as NandFlash, is 0xff, but the bit 7 position is a bad column, dummy data (such as 0) is required to be recombined at the bit 7 position, and the data actually written into the NandFlash after being recombined is 0x7 f.
2. Reading operation:
the data read-write device of the memory responds to the reading instruction, and the reading operation of the target data according to the bad column position information comprises the following steps:
searching a byte bad column template to determine a byte bad column set in a memory;
searching a bit bad column template to determine a third bit bad column corresponding to each byte bad column in the byte bad column set;
reading target data according to the reading instruction, wherein the target data is data which is stored in a memory and corresponds to the reading instruction;
and performing data recombination on data except the data corresponding to the third bit bad column in the target data to finish the reading operation of the target data.
In this embodiment, when the data reading and writing device of the memory reads data from the memory, the data reading and writing device may determine the bit bad column by detecting the byte bad column template and the bit bad column template, insert the invalid data into the bit bad column, recombine the target data and the data of the bit bad column into which the invalid data is inserted, and write the target data and the data of the bit bad column into the memory, thereby completing writing the data. It can be understood that when the data read-write device of the memory searches the bad column template, firstly reading data from the first-level byte bad column template, judging whether each byte is a bad column, if so, sequentially reading data from the second-level bit bad column template, judging which bits of the byte are bad columns, finally determining the bit bad columns corresponding to each byte bad column in the byte bad column set and the byte bad column combination, reading the target data from the NandFlash, then discarding the data at the read bit bad column positions, and recombining the rest data to form complete effective data. For example, if the data 0x7f is read from NandFlash, but the bit 7 position is a bad column, the data (here, 0) at the bit 7 position needs to be discarded to form valid data of 7 bits, and the valid data at the 7 bits is combined with the valid data at other positions to form final data completely composed of the valid data, and then the final data is subjected to ECC error correction. It is understood that the target data is the data written by the write operation in step 1, and the target data includes invalid data at the bit fail column position corresponding to the memory.
To sum up, in the embodiment provided by the application, the bit bad column position information in the NandFlash is determined, and then the data read-write operation is performed according to the bit bad column position information, so that the NandFlash capacity can be maximally utilized, and meanwhile, when error correction is performed through the ECC, more ECC redundant data can be accommodated, the error correction capability is improved, and the NandFlash data stability is enhanced.
The present application is described above from the viewpoint of a data read/write method of a memory, and the present application is described below from the viewpoint of a data read/write apparatus of a memory.
Referring to fig. 2, fig. 2 is a schematic view of a virtual structure of a data read/write apparatus of a memory according to an embodiment of the present disclosure, including:
an obtaining unit 201, configured to obtain a read instruction or a write instruction for a memory, where the read instruction or the write instruction corresponds to target data;
a determining unit 202, configured to determine bad column location information of the memory, where the bad column location information of the memory indicates location information of a bit bad column in the memory;
and the processing unit 203 is configured to respond to the read instruction or the write instruction, and perform a read operation or a write operation on the target data according to the bad column position information.
Optionally, the determining unit 202 is specifically configured to:
writing test data to the memory;
reading data from the memory to obtain first data;
comparing the first data with the test data to determine a bit bad column position of each page in the memory;
and determining position information corresponding to a target bit position as bad column position information of the memory, wherein the target bit position is a bit position with the same bit bad column position in a plurality of pages in the memory.
Optionally, the apparatus further comprises:
a template generation unit 204 for:
determining a byte bad column set of the memory and a bit bad column corresponding to each byte bad column in the byte bad column set according to the bad column position information;
generating a byte bad column template corresponding to the memory according to the byte bad column set of the memory;
and generating a bit bad column template corresponding to the memory according to the bit bad column corresponding to each byte bad column in the byte bad column set.
Optionally, the processing unit 203 is specifically configured to:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a first bit bad column corresponding to each byte bad column in the byte bad column set;
inserting invalid data into the first bit bad column to obtain a second bit bad column;
and recombining the target data and the data corresponding to the second bit bad column and writing the recombined data into the memory.
Optionally, the processing unit 203 is further specifically configured to:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a third bit bad column corresponding to each byte bad column in the byte bad column set;
reading the target data according to the reading instruction, wherein the target data is data which is stored in the memory and corresponds to the reading instruction;
and performing data recombination on data except the data corresponding to the third bit bad column in the target data to finish the reading operation of the target data.
To sum up, in the embodiment provided by the application, the bit bad column position information in the NandFlash is determined, and then the data read-write operation is performed according to the bit bad column position information, so that the NandFlash capacity can be maximally utilized, and meanwhile, when error correction is performed through the ECC, more ECC redundant data can be accommodated, the error correction capability is improved, and the NandFlash data stability is enhanced.
Fig. 4 is a schematic diagram of a server 400 according to an embodiment of the present disclosure, where the server 400 may have a relatively large difference due to different configurations or performances, and may include one or more Central Processing Units (CPUs) 422 (e.g., one or more processors) and a memory 432, and one or more storage media 430 (e.g., one or more mass storage devices) for storing applications 442 or data 444. Wherein the memory 432 and storage medium 430 may be transient or persistent storage. The program stored on the storage medium 430 may include one or more modules (not shown), each of which may include a series of instruction operations for the server. Still further, the central processor 422 may be arranged to communicate with the storage medium 430, and execute a series of instruction operations in the storage medium 430 on the server 400.
The server 400 may also include one or more power supplies 426, one or more wired or wireless network interfaces 450, one or more input-output interfaces 458, and/or one or more operating systems 441, such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, and so forth.
The steps performed by the defect detection apparatus of ferromagnetic members in the above-described embodiment may be based on the server structure shown in fig. 4.
According to the method provided by the embodiment of the present application, the present application further provides a computer program product, which includes: computer program code which, when run on a computer, causes the computer to perform a method for reading and writing data from and to a memory as provided by one or more embodiments of the present application.
According to the method provided by the embodiment of the present application, the present application further provides a computer-readable storage medium, which stores program codes, and when the program codes are run on a computer, the computer is caused to execute the data reading and writing method of the memory provided by one or more embodiments of the present application.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.
The network device in the foregoing various apparatus embodiments corresponds to the terminal device or the network device in the terminal device and method embodiments, and the corresponding module or unit executes the corresponding steps, for example, the communication unit (transceiver) executes the steps of receiving or transmitting in the method embodiments, and other steps besides transmitting and receiving may be executed by the processing unit (processor). The functions of the specific elements may be referred to in the respective method embodiments. The number of the processors may be one or more.
As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps (step) described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A data read-write method of a memory is characterized by comprising the following steps:
acquiring a read instruction or a write instruction for a memory, wherein the read instruction or the write instruction corresponds to target data;
determining bad column position information of the memory, wherein the bad column position information of the memory indicates position information of a bit bad column in the memory;
and responding to the reading instruction or the writing instruction, and performing reading operation or writing operation on the target data according to the bad column position information.
2. The method of claim 1, wherein the determining bad column location information for the memory comprises:
writing test data to the memory;
reading data from the memory to obtain first data;
comparing the first data with the test data to determine a bit bad column position of each page in the memory;
and determining position information corresponding to a target bit position as bad column position information of the memory, wherein the target bit position is a bit position with the same bit bad column position in a plurality of pages in the memory.
3. The method according to claim 1 or 2, characterized in that the method further comprises:
determining a byte bad column set of the memory and a bit bad column corresponding to each byte bad column in the byte bad column set according to the bad column position information;
generating a byte bad column template corresponding to the memory according to the byte bad column set of the memory;
and generating a bit bad column template corresponding to the memory according to the bit bad column corresponding to each byte bad column in the byte bad column set.
4. The method of claim 3, wherein the writing the target data according to the bad column location information in response to the write command comprises:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a first bit bad column corresponding to each byte bad column in the byte bad column set;
inserting invalid data into the first bit bad column to obtain a second bit bad column;
and recombining the target data and the data corresponding to the second bit bad column and writing the recombined data into the memory.
5. The method of claim 3, wherein the performing a read operation on the target data according to the bad column location information in response to the read instruction comprises:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a third bit bad column corresponding to each byte bad column in the byte bad column set;
reading the target data according to the reading instruction, wherein the target data is data which is stored in the memory and corresponds to the reading instruction;
and performing data recombination on data except the data corresponding to the third bit bad column in the target data to finish the reading operation of the target data.
6. A data reading/writing apparatus for a memory, comprising:
an acquisition unit configured to acquire a read instruction or a write instruction for a memory, the read instruction or the write instruction corresponding to target data;
the determining unit is used for determining the bad column position information of the memory, and the bad column position information of the memory indicates the position information of the bit bad column in the memory;
and the processing unit is used for responding to the reading instruction or the writing instruction and performing reading operation or writing operation on the target data according to the bad column position information.
7. The apparatus according to claim 6, wherein the determining unit is specifically configured to:
writing test data to the memory;
reading data from the memory to obtain first data;
comparing the first data with the test data to determine a bit bad column position of each page in the memory;
and determining position information corresponding to a target bit position as bad column position information of the memory, wherein the target bit position is a bit position with the same bit bad column position in a plurality of pages in the memory.
8. The apparatus of claim 6 or 7, further comprising:
a template generation unit to:
determining a byte bad column set of the memory and a bit bad column corresponding to each byte bad column in the byte bad column set according to the bad column position information;
generating a byte bad column template corresponding to the memory according to the byte bad column set of the memory;
and generating a bit bad column template corresponding to the memory according to the bit bad column corresponding to each byte bad column in the byte bad column set.
9. The apparatus according to claim 8, wherein the processing unit is specifically configured to:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a first bit bad column corresponding to each byte bad column in the byte bad column set;
inserting invalid data into the first bit bad column to obtain a second bit bad column;
and writing the target data and the second bit bad column data into the memory after recombining the target data and the second bit bad column data.
10. The method of claim 8, wherein the processing unit is further specifically configured to:
retrieving the byte bad column template to determine a byte bad column set in the memory;
searching the bit bad column template to determine a third bit bad column corresponding to each byte bad column in the byte bad column set;
reading the target data according to the reading instruction, wherein the target data is data which is stored in the memory and corresponds to the reading instruction;
and performing data recombination on data except the data corresponding to the third bit bad column in the target data to finish the reading operation of the target data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010947859.9A CN112068781B (en) | 2020-09-10 | 2020-09-10 | Data reading and writing method of memory and related equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010947859.9A CN112068781B (en) | 2020-09-10 | 2020-09-10 | Data reading and writing method of memory and related equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112068781A true CN112068781A (en) | 2020-12-11 |
| CN112068781B CN112068781B (en) | 2024-03-22 |
Family
ID=73663508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010947859.9A Active CN112068781B (en) | 2020-09-10 | 2020-09-10 | Data reading and writing method of memory and related equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112068781B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113625964A (en) * | 2021-07-16 | 2021-11-09 | 浙江鸿泉电子科技有限公司 | NandFlash-based sequential storage method, electronic equipment and storage medium |
| CN113688067A (en) * | 2021-08-30 | 2021-11-23 | 上海汉图科技有限公司 | Data writing method, data reading method and device |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008234714A (en) * | 2007-03-16 | 2008-10-02 | Toshiba Corp | Write control method of nonvolatile semiconductor storage device and memory system |
| US20090323942A1 (en) * | 2008-06-30 | 2009-12-31 | Eran Sharon | Method for page- and block based scrambling in non-volatile memory |
| CN102543208A (en) * | 2010-12-30 | 2012-07-04 | 深圳市硅格半导体有限公司 | Method and device for quickly determining distribution of flash errors |
| CN103279424A (en) * | 2013-05-15 | 2013-09-04 | 建荣集成电路科技(珠海)有限公司 | Damaged queue management device and method of Nand Flash |
| CN104658612A (en) * | 2013-11-15 | 2015-05-27 | 慧荣科技股份有限公司 | Method for accessing storage unit in flash memory and device using the same |
| US9348694B1 (en) * | 2013-10-09 | 2016-05-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Detecting and managing bad columns |
| CN105677246A (en) * | 2015-12-31 | 2016-06-15 | 北京兆易创新科技股份有限公司 | NAND flash memory data reading method and device and NAND flash memory |
| CN105786719A (en) * | 2016-03-03 | 2016-07-20 | 北京兆易创新科技股份有限公司 | NAND Flash memorizer and processing method of bad blocks in memorizer |
| CN105788648A (en) * | 2014-12-25 | 2016-07-20 | 研祥智能科技股份有限公司 | NVM bad block recognition processing and error correcting method and system based on heterogeneous mixing memory |
| US20170062076A1 (en) * | 2015-08-27 | 2017-03-02 | Kabushiki Kaisha Toshiba | Memory system that handles access to bad blocks |
| CN106776106A (en) * | 2016-11-11 | 2017-05-31 | 南京南瑞集团公司 | A kind of date storage method based on NandFlash |
| CN108829347A (en) * | 2018-05-29 | 2018-11-16 | 深圳市华星光电技术有限公司 | A kind of hardware control, control method and the liquid crystal display of Nand equipment |
| CN110546709A (en) * | 2019-07-12 | 2019-12-06 | 长江存储科技有限责任公司 | Memory device providing bad column repair and method of operating the same |
-
2020
- 2020-09-10 CN CN202010947859.9A patent/CN112068781B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008234714A (en) * | 2007-03-16 | 2008-10-02 | Toshiba Corp | Write control method of nonvolatile semiconductor storage device and memory system |
| US20090323942A1 (en) * | 2008-06-30 | 2009-12-31 | Eran Sharon | Method for page- and block based scrambling in non-volatile memory |
| CN102543208A (en) * | 2010-12-30 | 2012-07-04 | 深圳市硅格半导体有限公司 | Method and device for quickly determining distribution of flash errors |
| CN103279424A (en) * | 2013-05-15 | 2013-09-04 | 建荣集成电路科技(珠海)有限公司 | Damaged queue management device and method of Nand Flash |
| US9348694B1 (en) * | 2013-10-09 | 2016-05-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Detecting and managing bad columns |
| CN104658612A (en) * | 2013-11-15 | 2015-05-27 | 慧荣科技股份有限公司 | Method for accessing storage unit in flash memory and device using the same |
| CN105788648A (en) * | 2014-12-25 | 2016-07-20 | 研祥智能科技股份有限公司 | NVM bad block recognition processing and error correcting method and system based on heterogeneous mixing memory |
| US20170062076A1 (en) * | 2015-08-27 | 2017-03-02 | Kabushiki Kaisha Toshiba | Memory system that handles access to bad blocks |
| CN105677246A (en) * | 2015-12-31 | 2016-06-15 | 北京兆易创新科技股份有限公司 | NAND flash memory data reading method and device and NAND flash memory |
| CN105786719A (en) * | 2016-03-03 | 2016-07-20 | 北京兆易创新科技股份有限公司 | NAND Flash memorizer and processing method of bad blocks in memorizer |
| CN106776106A (en) * | 2016-11-11 | 2017-05-31 | 南京南瑞集团公司 | A kind of date storage method based on NandFlash |
| CN108829347A (en) * | 2018-05-29 | 2018-11-16 | 深圳市华星光电技术有限公司 | A kind of hardware control, control method and the liquid crystal display of Nand equipment |
| CN110546709A (en) * | 2019-07-12 | 2019-12-06 | 长江存储科技有限责任公司 | Memory device providing bad column repair and method of operating the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113625964A (en) * | 2021-07-16 | 2021-11-09 | 浙江鸿泉电子科技有限公司 | NandFlash-based sequential storage method, electronic equipment and storage medium |
| CN113625964B (en) * | 2021-07-16 | 2024-01-26 | 浙江鸿泉电子科技有限公司 | NandFlash-based sequential storage method, electronic device and storage medium |
| CN113688067A (en) * | 2021-08-30 | 2021-11-23 | 上海汉图科技有限公司 | Data writing method, data reading method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112068781B (en) | 2024-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9262283B2 (en) | Method for reading kernel log upon kernel panic in operating system | |
| US10475517B2 (en) | Characterizing and operating a non-volatile memory device | |
| KR20060051898A (en) | System and method of reading non-volatile computer memory | |
| US20190004829A1 (en) | Method, device and user terminal for loading application | |
| KR20120064462A (en) | Memory controller and method for correcting error the same, and memory system having the same | |
| US11209986B2 (en) | Memory operations on data | |
| CN112068781B (en) | Data reading and writing method of memory and related equipment | |
| US8566689B2 (en) | Data integrity units in nonvolatile memory | |
| CN113643746A (en) | Flash memory data analysis method and device, terminal equipment and storage medium | |
| CN112181479A (en) | Method and device for determining difference between code file versions and electronic equipment | |
| US20170031630A1 (en) | Handling shingled magnetic recording (smr) drives in a tiered storage system | |
| CN114328062B (en) | Method, device and storage medium for checking cache consistency | |
| US20220188221A1 (en) | Regression testing method and regression testing apparatus | |
| CN115470738A (en) | Function verification method and device, electronic equipment and storage medium | |
| CN107291628A (en) | The method and apparatus of accessing data storage devices | |
| CN114822675A (en) | Memory detection method and device, electronic equipment and storage medium | |
| US10579470B1 (en) | Address failure detection for memory devices having inline storage configurations | |
| CN107515828B (en) | Data reading and writing method and mobile terminal | |
| CN112216333A (en) | Chip testing method and device | |
| CN109491870A (en) | A kind of detection method and device of the access state of sensor | |
| CN114127770A (en) | Sample incremental monitoring | |
| CN112653595B (en) | Chip network function testing method and device, storage medium and equipment | |
| US20220180152A1 (en) | Information processing apparatus and method for analyzing errors of neural network processing device therein | |
| US20240184454A1 (en) | Storage device and operating method of the same | |
| CN113806310A (en) | Comparison method and related product |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |