CN112054670A - Microphone and charge pump circuit thereof - Google Patents

Microphone and charge pump circuit thereof Download PDF

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Publication number
CN112054670A
CN112054670A CN202010786732.3A CN202010786732A CN112054670A CN 112054670 A CN112054670 A CN 112054670A CN 202010786732 A CN202010786732 A CN 202010786732A CN 112054670 A CN112054670 A CN 112054670A
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capacitor
transistor
charge pump
terminal
switch
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CN202010786732.3A
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CN112054670B (en
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王龙伟
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Suzhou Novosense Microelectronics Co ltd
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Haojun Technology Beijing Co ltd
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0067Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007Plural converter units in cascade

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The microphone comprises a first transistor, a second transistor, a first capacitor, a second capacitor and a third capacitor, wherein the first transistor and the second transistor are connected in series in a forward direction between a supply voltage input end and an output voltage output end, the second ends of the first capacitor and the second capacitor are connected through a first switch, the third capacitor is connected between the output voltage output end and the ground, the second end of the first capacitor is connected with a charge source, the second end of the second capacitor is connected to the ground through a second switch, and the first switch and the second switch are switched on or off in a time sharing mode. The charge pump circuit controls the on and off of the first switch and the second switch to control the parallel relation of the first capacitor and the second capacitor and the connection state of the first capacitor and the second capacitor and the charge source to control the capacitance value of the charge extraction capacitor, further control the increment of the output voltage and adjust the value of the output voltage. The microphone of the invention takes the charge pump circuit as a bias circuit, and the bias voltage is adjustable, so as to meet the requirement of sensitivity fluctuation of the microphone and optimize the consistency of the microphone.

Description

Microphone and charge pump circuit thereof
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a microphone and a charge pump circuit thereof.
Background
The charge pump is a core circuit of a MEMS (Micro-Electro-Mechanical System) microphone, and is equivalent to a bias circuit of the MEMS, the sensitivity of the microphone is determined by the level of the output voltage of the charge pump, and the noise of the output voltage of the charge pump directly affects the noise performance of the microphone.
The traditional dickson charge pump has the advantages of simple structure and good performance. With the technical progress, the requirements on the sensitivity of the microphone by the terminal are higher and higher, and the fluctuation of the sensitivity of the microphone is required to be smaller and smaller. The MEMS process stability cannot meet the requirement of sensitivity fluctuation, so that a circuit is required to adjust bias voltage to meet the fluctuation of the overall sensitivity of the microphone.
At its simplest, the number of stages of the charge pump can be adjusted to adjust the output voltage. As shown in fig. 1, the charge pump circuit 100 of the prior art has a multi-stage charge pump unit 110 connected in series between an input terminal providing an input voltage VIN and an output terminal outputting a voltage VOUT.
The charge pump unit 110 includes a diode D1 and a diode D2 connected in series in the forward direction between the input terminal and the output terminal, one end of a capacitor C1 is connected to the intermediate node of the diode D1 and the diode D2, and the other end receives a clock signal CLK 1; one end of the capacitor C2 is connected to the output end of the charge pump unit 110, and the other end receives the clock signal CLK 2. The clock signal CLK1 and the clock signal CLK2 have opposite phases, and the input voltage VIN is provided by the voltage regulator.
By charging and discharging the capacitor C1, charge is drawn from the charge source of the clock signal CLK1 to the capacitor C2, and the charge of the capacitor C2 is limited by the diode D2 and can only be used as an output coupling capacitor to couple the supply voltage VIN and the voltage raised by the capacitor C1 to an output voltage.
The charge pump circuit 100 uses the output voltage of the voltage regulator as the input voltage VIN, the regulation step of the output voltage VOUT is equal to the input voltage VIN, and the input voltage VIN is the supply voltage of the charge pump circuit 100, if the supply voltage is too low, the effect of the charge pump is affected, and the performance of the microphone is affected.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a microphone and a charge pump circuit thereof, which provide finer output voltage adjustment and finer sensitivity adjustment for the microphone.
According to an aspect of the present invention, there is provided a charge pump circuit comprising a supply voltage input, a charge source input, an output voltage output and a charge pump assembly, wherein the charge pump assembly comprises:
the first transistor and the second transistor are connected in series between the power supply voltage input end and the output voltage output end in a forward direction in sequence, and the first transistor and the second transistor are conducted in the forward direction and cut off in the reverse direction between the power supply voltage input end and the output voltage output end;
a first capacitor including a first terminal and a second terminal, the first terminal of the first capacitor being connected to an intermediate node between the first transistor and the second transistor, the second terminal of the first capacitor being connected to the charge source input terminal;
the first end of the second capacitor is connected to the middle node of the first transistor and the second transistor, and the second end of the second capacitor is grounded through a second switch;
the first end of the third capacitor is connected to the output voltage output end, and the second end of the third capacitor is connected to the charge source input end; a first switch connected between the second terminal of the first capacitor and the second terminal of the second capacitor; the first switch and the second switch are switched on or off in a time-sharing mode.
Optionally, at least one of the first transistor and the second transistor is a metal oxide semiconductor device, or both the first transistor and the second transistor are diodes.
Optionally, the charge pump assemblies are at least one group and are cascaded in series.
Optionally, the charge pump assembly further comprises:
a fourth capacitor having a first terminal and a second terminal, the first terminal of the fourth capacitor being connected to the second transistor at a terminal opposite to the intermediate node of the first transistor and the second transistor, the second terminal of the second capacitor being connected to the charge source input terminal;
a third switch connected in series between a second terminal of the third capacitor and ground;
a fourth switch connected between the second terminal of the third capacitor and the second terminal of the fourth capacitor;
and the charge source signal of the second end of the fourth capacitor is opposite to the charge source signal of the second end of the first capacitor, and the third switch and the fourth switch are switched on or off in a time-sharing manner.
According to another aspect of the present invention, there is provided a microphone including:
the charge pump circuit provided by the invention.
Optionally, the method further comprises:
and the band-gap reference circuit comprises a band-gap reference voltage output end, and the band-gap reference voltage output end is connected with a power supply voltage input end of the charge pump circuit.
Optionally, the method further comprises:
and the oscillator is connected with the band-gap reference circuit so as to receive the band-gap reference voltage as a power supply voltage and provide a first clock signal and a second clock signal which are in opposite phases as a charge source signal of the second end of the fourth capacitor and a charge source signal of the second end of the first capacitor.
The charge pump circuit provided by the invention designs the charge extraction capacitor connected to the middle node of the first diode and the second diode into the parallel connection of the first capacitor and the second capacitor, wherein when the first switch is switched on, the capacitance value of the charge extraction capacitor is the parallel connection capacitor of the first capacitor and the second capacitor, when the first switch is switched off, the second switch is switched on, the second capacitor is grounded, the capacitance value of the charge extraction capacitor is the capacitance value of the first capacitor, the parallel connection state of the second capacitor and the first capacitor is controlled through the first switch, the capacitance value of the charge extraction capacitor is adjusted, and further the increase value of the output voltage of the charge pump circuit relative to the power supply voltage is adjusted, the output voltage is adjusted, and the adjustment is more precise.
The cascade connection of the charge pump assembly is designed, so that the step number of the adjustable steps of the output voltage can be increased, and the adjusting range is expanded.
The cascaded charge pump assembly is provided with a plurality of stages of diodes, capacitors connected to the middle node of every two diodes are designed into two capacitors which are controllable in parallel, and charge source signals of two adjacent charge extraction capacitors are in opposite phases, so that hardware resources can be fully utilized, each group of capacitors can be used for the charge extraction capacitors, and non-part capacitors can only serve as coupling capacitors to output voltage. Moreover, the proportion of each group of capacitors which can form a parallel relation can be different, namely the step length of each adjusting step is different, and the charge pump circuit with more adjusting steps and finer adjustment can be obtained through the combination of increasing voltages with different step lengths.
The microphone provided by the invention adopts the charge pump circuit as the bias circuit, obtains the bias voltage with high adjustment precision under the condition of not changing the power supply voltage of the charge pump circuit, reduces the fluctuation of the sensitivity range of a microphone finished product under the condition of the technological fluctuation of the sensor, can meet the requirement of the sensitivity fluctuation of the microphone, and optimizes the sensitivity of the microphone.
The band-gap reference voltage provided by the band-gap reference circuit is used as the power supply voltage of the microphone system, so that a good temperature coefficient can be obtained.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic diagram of a charge pump circuit according to the prior art;
FIG. 2 is a circuit diagram of a low dropout linear regulator according to the prior art;
FIG. 3 shows a schematic diagram of a biasing circuit according to the prior art;
FIG. 4 shows a schematic diagram of a bandgap reference circuit according to the prior art;
fig. 5 shows a schematic diagram of a charge pump circuit according to an embodiment of the invention.
Fig. 6 shows a timing diagram of a charge source signal of a charge pump circuit according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 2 shows a schematic circuit diagram of a low dropout linear regulator according to the prior art. As shown, the related art low dropout linear regulator 200 includes a first current path and a second current path between a voltage source providing a voltage VDD and a ground, the first current path includes a current source a1, a transistor M3 and a resistor R1 connected in series in a forward direction, and the second current path includes a transistor M1, a transistor M2 and a resistor R1 connected in series in a forward direction. The gate of the transistor M1 is connected to the positive output terminal of the current source a1, the gate of the transistor M2 is connected to the bandgap voltage Vbg, the gate of the transistor M3 is connected to the gate bias voltage VB, and the intermediate node of the transistor M1 and the transistor M2 outputs the voltage Vreg.
In the present embodiment, the transistor M1 and the transistor M2 are P-type transistors.
Fig. 3 shows a schematic diagram of a bias circuit according to the prior art. As shown in the figure, the bias circuit 300 includes two current paths between the voltage source and the ground, one current path is connected in series with the transistor PM1 and the transistor NM1 in sequence, and the other current path is connected in series with the transistor PM2, the transistor NM2 and the resistor R1 in sequence.
Wherein, the transistor PM1 and the transistor PM2 are P-type Metal Oxide Semiconductor (PMOS) devices, and gates are interconnected; the gate and drain of transistor PM2 are connected. The transistor NM1 and the transistor NM2 are N-Metal-Oxide-Semiconductor (NMOS) devices, a gate of the transistor NM1 is connected to an intermediate node between the transistor NM2 and the resistor R1, and a gate of the transistor NM2 is connected to an intermediate node between the transistor PM1 and the transistor NM 1. The voltage at the intermediate node between the transistors PM1 and NM1 is the bias voltage VB.
Fig. 4 shows a schematic diagram of a bandgap reference circuit according to the prior art. As shown, the bandgap reference circuit 400 includes a transistor PM3, a transistor PM4, a transistor PM5, a resistor R2, a resistor R3, a transistor Q1, a transistor Q2, a transistor Q3, and an operational amplifier 401.
The transistors PM3, PM4, PM5 are PMOS devices, and the gates are interconnected. The transistor PM3 and the transistor PM4 constitute a current mirror. The transistor PM3 and the transistor Q1 are sequentially connected in series between a voltage source and the ground, the transistor PM4, the resistor R2 and the transistor Q2 are sequentially connected in series between the voltage source and the ground, and the gates of the transistor Q1 and the transistor Q2 are connected to the ground. The non-inverting input terminal of the operational amplifier 401 is connected to the intermediate node between the transistor PM4 and the resistor R2, the inverting input terminal is connected to the intermediate node between the transistor PM3 and the transistor Q1, and the output terminal is connected to the gates of the transistor PM3 and the transistor PM 4.
The transistor PM5, the resistor R3 and the transistor Q3 are sequentially connected in series between a voltage source and the ground, and the middle node of the transistor PM5 and the resistor R3 outputs the band gap voltage Vbg.
The threshold voltages of Q1, Q2 and Q3 are negative temperature coefficients, and the currents flowing through Q1, Q2 and Q3 are positive temperature coefficients, so that the stable band gap voltage Vbg can be obtained to be used as a reference by adjusting the ratio of the positive temperature coefficient and the negative temperature coefficient.
The reference voltage Vbg is connected to the gate of M2 in fig. 2, and constitutes a regulator. As a voltage stabilizer, in order to realize better temperature coefficient of a charge pump, the stable band gap voltage provided by the voltage stabilizer is not adjustable and cannot be used for realizing fine adjustment of the charge pump, so the invention is designed from a charge pump unit of the charge pump.
Fig. 5 shows a schematic diagram of a charge pump circuit according to an embodiment of the invention. As shown, the charge pump circuit 500 of the embodiment of the present invention includes a plurality of stages of charge pump units 510 connected in series between an input terminal (a supply voltage input terminal) providing a supply voltage VIN of the charge pump circuit 500 and an output terminal (an output voltage output terminal) providing an output voltage VOUT of the charge pump circuit.
Each charge pump cell 510 comprises a diode D1 and a diode D2 connected in series in the forward direction between an input terminal and an output terminal, a first terminal of a capacitor C1 is connected to an intermediate node V1 of a transistor D1 and a transistor D2, a second terminal receives a clock signal CLK1, a first terminal of a capacitor C11 is connected to a node V1, a second terminal is grounded through a switch K11, and a switch K1 is connected between a second terminal of a capacitor C1 and a second terminal of the capacitor C11; a first terminal of the capacitor C2 is connected to the output node V2 of the charge pump unit 510, a second terminal thereof receives the clock signal CLK2, a first terminal of the capacitor C21 is connected to the node V2, a second terminal thereof is grounded via a switch K21, and a switch K2 is connected between the second terminal of the capacitor C2 and the second terminal of the capacitor C21. The clock signals CLK1 and CLK2 are charge source signals.
The supply voltage VIN may be provided by a voltage regulator, the clock signal CLK1 and the clock signal CLK2 with opposite phases may be provided by an oscillator, the power supply of the oscillator is also provided by the voltage regulator, the diode D1 and the diode D2 may be replaced by Metal Oxide Semiconductor (MOS) devices or other transistors to improve the product applicability, and the MOS devices have higher reverse breakdown voltage to improve the product reliability. The voltage stabilizer can adopt a band-gap reference circuit as a reference voltage so as to obtain a better temperature coefficient.
The switch K1 and the switch K11 are controlled to be closed and opened by a first switch control signal and a second switch control signal which are opposite in phase, and the switch K2 and the switch K21 are also controlled to be closed and opened by the first switch control signal and the second switch control signal. Namely, when the system works, the capacitor C11 only has two states of parallel connection of the capacitor C1 and grounding, the capacitor C21 only has two states of parallel connection of the capacitor C2 and grounding, and the capacitor C1 and the capacitor C2 are connected with charge source signals.
When the first switch control signal is 1, the switch K1 is turned on, and the switch K11 is turned off, so that a double charge pump is formed, and the voltage increased by the first stage charge pump is ideally the supply voltage VIN of the charge pump circuit 500.
When the first switch control signal is 0, the switch K1 is turned off, the switch K11 is turned on, and under the ideal condition, the voltage Δ V increased by the first-stage charge pumpout=VIN*(C1/(C1+C11))。
Therefore, the switch K1 and the switch K11 are controlled by the switch control signal, and the capacitor C1 and the capacitor C are controlled according to requirements11, the increasing voltage delta V of the single-stage charge pump can be adjustedoutThe output voltage of the single-stage charge pump is regulated, and the regulation mode can realize smaller regulation step length and improve regulation precision, and simultaneously does not influence other parts (such as a voltage stabilizer) of the microphone system and is not influenced by other parts of the microphone system.
Meanwhile, the multi-stage charge pump units 510 are designed to be connected in series, the adjusting step length of each stage of charge pump unit is further adjusted and controlled, the adjustable step lengths with the number of stages larger than that of the charge pump units can be combined, the adjusting precision of the charge pump circuit is further improved, and the sensitivity of a microphone using the charge pump circuit is improved. Meanwhile, by adjusting the capacitance proportion of each stage of the combined charge pump, more accurate adjustment can be obtained under a certain output voltage. The design of the cascade connection of the multi-stage charge pump units improves the voltage lifting capability of the charge pump circuit, and the performance of the charge pump circuit can be guaranteed under the lower power supply voltage.
The cascade number of the multistage charge pump units connected in series is related to the final output voltage, the adjustable quantity of each stage of charge pump unit corresponds to one adjusting step length, and the more the stages are, the higher the precision of the selectable adjusting step length of the final output voltage is.
Fig. 6 shows a timing diagram of a charge source signal of the charge pump circuit of an embodiment of the present invention. As shown, the clock signals CLK1 and CLK2 are timing diagrams of two charge source signals of the charge pump circuit 500 according to the embodiment of the invention, and their timings are inverted, for example, the timing of the clock signal CLK1 shown in fig. 6 is 0101010, and the timing of the clock signal CLK2 is 1010101.
The charge pump circuit 500 of the embodiment of the present invention has the inverse charge source signal, when the capacitor C1 and the capacitor C11 are used as the charge pumping devices, the capacitor C2 and the capacitor C21 are used as the coupling capacitors to output voltages, otherwise, the capacitor C2 and the capacitor C21 are used as the charge pumping devices, which form a charge pump together with the corresponding capacitors of the next stage of charge pump unit, and the ratio of the capacitor C1 to the capacitor C11 and the ratio of the capacitor C2 to the capacitor C21 are designed to be different, so that two types of charge pump circuits with adjustable accuracies can be obtained under the condition of saving system resources, and the adjustable accuracy of the charge pump circuit is improved by combining the two types of charge pump circuits, thereby improving the practical value. If the two inverted clock signals CLK1 and CLK2 are not used, the capacitor C21 and the switches K2 and K21 can be eliminated, and the second terminal of the capacitor C2 is grounded. Meanwhile, two groups of capacitors connected to two ends of one diode can be used as charge extraction capacitors or output voltage coupling capacitors.
The charge pump circuit of the invention designs the charge source extracting capacitor as a first capacitor and a second capacitor, the first ends of the first capacitor and the second capacitor are connected between a first diode and a second diode, the second ends are connected through a first switch, the second ends of the first capacitor and the second capacitor are respectively connected to the charge source and the ground through a second switch, the first switch and the second switch are conducted in a time-sharing way, when the first switch is conducted, the charge extracting capacitor is a parallel equivalent capacitor of the first capacitor and the second capacitor, when the first switch is disconnected, the charge extracting capacitor is the first capacitor, thereby controlling the output voltage increasing value of the single-stage charge pump according to the state of the first switch and the second switch, regulating the output voltage of the charge pump, further regulating the microphone applying the charge pump, regulating the output voltage of the charge pump circuit, and regulating the sensitivity of the microphone applying the charge pump, the output voltage is adjusted by optimizing the charge pump circuit, so that the sensitivity batch stability of the microphone is optimized.
By adjusting the charge pump circuit to optimize the fluctuation of the sensitivity of the microphone, the regulator providing the power supply voltage can be adjusted without the need, and the feasibility and the applicability of the system are improved.
The power supply voltage does not need to be adjusted, and meanwhile, the band gap reference voltage with good temperature coefficient is provided by the band gap reference circuit and serves as the power supply voltage, so that the good temperature coefficient of the power supply voltage is guaranteed, the temperature coefficient of the charge pump circuit is guaranteed, and the sensitivity fluctuation of the microphone is smaller.
The cascade connection of the multi-stage charge pump units is designed, the variable range and the minimum variation value of the output voltage of the charge pump circuit can be improved, the precision is improved, the multi-stage charge pumps with different lifting multiplying powers are obtained by regulating and controlling the capacitance values of the charge pumping capacitors of the charge pump units at all stages, and higher adjusting precision and more adjustable points are obtained by combining the multi-stage charge pumps with different lifting multiplying powers.
The clock signal provided by the second end of the charge pumping capacitor of each stage of the charge pump is a charge source, the clock signal is provided for the charge source of each stage of the charge pump at intervals, namely the clock signal of the charge pump of the adjacent stage is in opposite phase, and the proportion of the first capacitor and the second capacitor of the charge pump of the adjacent stage is different, namely the adjustment accuracy is different, so that higher adjustment accuracy is obtained under limited hardware resources.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (7)

1. A charge pump circuit comprising a supply voltage input, a charge source input, an output voltage output, and a charge pump assembly, wherein the charge pump assembly comprises:
the first transistor and the second transistor are connected in series between the power supply voltage input end and the output voltage output end in a forward direction in sequence, and the first transistor and the second transistor are conducted in the forward direction and cut off in the reverse direction between the power supply voltage input end and the output voltage output end;
a first capacitor including a first terminal and a second terminal, the first terminal of the first capacitor being connected to an intermediate node between the first transistor and the second transistor, the second terminal of the first capacitor being connected to the charge source input terminal;
the first end of the second capacitor is connected to the middle node of the first transistor and the second transistor, and the second end of the second capacitor is grounded through a second switch;
the first end of the third capacitor is connected to the output voltage output end, and the second end of the third capacitor is connected to the charge source input end; a first switch connected between the second terminal of the first capacitor and the second terminal of the second capacitor; the first switch and the second switch are switched on or off in a time-sharing mode.
2. The charge pump circuit of claim 1,
at least one of the first transistor and the second transistor is a metal oxide semiconductor device, or both the first transistor and the second transistor are diodes.
3. The charge pump circuit of claim 1,
the charge pump assemblies are at least one group and are cascaded in series.
4. The charge pump circuit of claim 3, wherein the charge pump assembly further comprises:
a fourth capacitor having a first terminal and a second terminal, the first terminal of the fourth capacitor being connected to the second transistor at a terminal opposite to the intermediate node of the first transistor and the second transistor, the second terminal of the second capacitor being connected to the charge source input terminal;
a third switch connected in series between a second terminal of the third capacitor and ground;
a fourth switch connected between the second terminal of the third capacitor and the second terminal of the fourth capacitor;
and the charge source signal of the second end of the fourth capacitor is opposite to the charge source signal of the second end of the first capacitor, and the third switch and the fourth switch are switched on or off in a time-sharing manner.
5. A microphone, comprising:
a charge pump circuit according to any one of claims 1 to 4.
6. The microphone of claim 5, further comprising:
and the band-gap reference circuit comprises a band-gap reference voltage output end, and the band-gap reference voltage output end is connected with a power supply voltage input end of the charge pump circuit.
7. The microphone of claim 6, further comprising:
and the oscillator is connected with the band-gap reference circuit so as to receive the band-gap reference voltage as a power supply voltage and provide a first clock signal and a second clock signal which are in opposite phases as a charge source signal of the second end of the fourth capacitor and a charge source signal of the second end of the first capacitor.
CN202010786732.3A 2020-08-07 2020-08-07 Microphone and charge pump circuit thereof Active CN112054670B (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010103677A (en) * 2000-05-10 2001-11-23 다카노 야스아키 Charge pump circuit and method for controlling the same
JP2002034235A (en) * 2000-05-10 2002-01-31 Sanyo Electric Co Ltd Charge pump circuit and its controlling method
CN101056104A (en) * 2006-04-12 2007-10-17 国际商业机器公司 Delay locked loop having charge pump gain independent of operating frequency
CN101483420A (en) * 2008-01-08 2009-07-15 弥亚微电子(上海)有限公司 Switch capacitor band-pass filter and continuous time band-pass filter
CN101662208A (en) * 2008-08-26 2010-03-03 天利半导体(深圳)有限公司 Charge pump circuit capable of realizing positive and negative high voltages
CN101847988A (en) * 2009-03-25 2010-09-29 承景科技股份有限公司 Signal converter
CN101989457A (en) * 2009-08-04 2011-03-23 上海华虹Nec电子有限公司 Nonrolatile storage system capable of reducing filter capacitor
CN205008738U (en) * 2015-08-28 2016-02-03 玄兆丰 Quick spot welder circuit with thyristor on -off control

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010103677A (en) * 2000-05-10 2001-11-23 다카노 야스아키 Charge pump circuit and method for controlling the same
JP2002034235A (en) * 2000-05-10 2002-01-31 Sanyo Electric Co Ltd Charge pump circuit and its controlling method
CN101056104A (en) * 2006-04-12 2007-10-17 国际商业机器公司 Delay locked loop having charge pump gain independent of operating frequency
CN101483420A (en) * 2008-01-08 2009-07-15 弥亚微电子(上海)有限公司 Switch capacitor band-pass filter and continuous time band-pass filter
CN101662208A (en) * 2008-08-26 2010-03-03 天利半导体(深圳)有限公司 Charge pump circuit capable of realizing positive and negative high voltages
CN101847988A (en) * 2009-03-25 2010-09-29 承景科技股份有限公司 Signal converter
CN101989457A (en) * 2009-08-04 2011-03-23 上海华虹Nec电子有限公司 Nonrolatile storage system capable of reducing filter capacitor
CN205008738U (en) * 2015-08-28 2016-02-03 玄兆丰 Quick spot welder circuit with thyristor on -off control

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