CN112053936B - Wafer back roughening control method and power device manufacturing method - Google Patents
Wafer back roughening control method and power device manufacturing method Download PDFInfo
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- CN112053936B CN112053936B CN202011004603.0A CN202011004603A CN112053936B CN 112053936 B CN112053936 B CN 112053936B CN 202011004603 A CN202011004603 A CN 202011004603A CN 112053936 B CN112053936 B CN 112053936B
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- 238000000034 method Methods 0.000 title claims abstract description 103
- 238000007788 roughening Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 116
- 230000008569 process Effects 0.000 claims abstract description 72
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000007788 liquid Substances 0.000 claims abstract description 21
- 239000000243 solution Substances 0.000 claims description 21
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 10
- 229910017604 nitric acid Inorganic materials 0.000 claims description 10
- 239000011259 mixed solution Substances 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000003814 drug Substances 0.000 abstract description 6
- 238000009499 grossing Methods 0.000 abstract description 5
- 238000001465 metallisation Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 238000001878 scanning electron micrograph Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- XLYOFNOQVPJJNP-ZSJDYOACSA-N heavy water Substances [2H]O[2H] XLYOFNOQVPJJNP-ZSJDYOACSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000010943 off-gassing Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 229910003638 H2SiF6 Inorganic materials 0.000 description 1
- 229910020479 SiO2+6HF Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- ZEFWRWWINDLIIV-UHFFFAOYSA-N tetrafluorosilane;dihydrofluoride Chemical compound F.F.F[Si](F)(F)F ZEFWRWWINDLIIV-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02035—Shaping
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Weting (AREA)
Abstract
The invention provides a wafer back roughening control method and a power device manufacturing method, wherein the wafer back roughening control method comprises the following steps: performing a first etching process on the back of the wafer to reduce cracks on the back of the wafer, performing a second etching process on the back of the wafer to enable the back of the wafer to have roughness, and performing a third etching process on the back of the wafer to reduce or eliminate peaks on the back of the wafer; the power device manufacturing method comprises the wafer back roughening control method, and then metal deposition is carried out on the wafer back. By adopting the scheme of the invention, the sharp wave crest and the sharp edge angle on the back of the wafer are slightly etched by the liquid medicine and are incompletely smoothed, so that the purpose of smoothing the wave crest and the sharp edge angle is achieved, and the technical problem of falling caused by poor metal adhesion is solved.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to a wafer back roughening method and a power device manufacturing method.
Background
Most semiconductor power devices need to work under the conditions of high current and high voltage, the born voltage is usually from tens to thousands of volts, if a planar structure is adopted, the occupied chip area is larger, and the on-resistance, the parasitic inductance and the parasitic capacitance are large, so that the longitudinal structure is adopted in the industry, the source electrode and the grid electrode are arranged on the front surface of the chip, and the drain electrode is arranged on the back surface of the chip, so that the area of the chip can be reduced while the on-resistance and the parasitic inductance are reduced, and the production cost is reduced. In the semiconductor power device manufacturing process, the wafer back surface needs to be roughened before back surface metal sputtering to increase the contact area. The current common formula is to etch the silicon surface by using etching liquid (mixed liquid of H 2SO4、HNO3 and HF), and the treated interface can obtain good roughness. However, the existing method is poor in metal adhesion and easy to fall off.
Disclosure of Invention
The invention aims to provide a wafer back roughening control method and a power device manufacturing method, which are used for solving the problem of poor metal adhesion.
In order to solve the technical problems, the invention provides a wafer back surface roughening control method, which comprises the following steps:
Performing a first etching process on the back of the wafer to reduce cracks on the back of the wafer;
performing a second etching process on the back surface of the wafer so as to enable the back surface of the wafer to have roughness; and
And performing a third etching process on the back surface of the wafer to reduce the peak of the back surface of the wafer.
Optionally, in the third etching process, the etching solution is a mixed solution of HNO 3 and HF.
Optionally, in the third etching process, the volume ratio of HNO 3 to HF is 5:1 to 200:1.
Optionally, in the third etching process, the temperature of the etching solution is 20-65 ℃.
Optionally, in the third etching process, etching time is less than 120 seconds.
Optionally, in the third etching process, 70% hno 3 solution and 49% hf solution are mixed according to a volume ratio of 9:1, and the etching temperature is 25 ℃, and the etching time is 3 seconds.
Optionally, in the first etching process, the etching solution is a mixed solution of H 2SO4、H3PO4、HNO3 and HF, the temperature of the etching solution is 25-35 ℃, and the etching time is 30-80 seconds.
Optionally, in the second etching process, the etching solution is a mixed solution of H 2SO4、HNO3 and HF, the temperature of the etching solution is 30-40 ℃, and the etching time is 50-80 seconds.
Based on the same inventive concept, the invention also provides a power device manufacturing method, comprising the following steps:
The wafer back roughening control method.
Optionally, the method further comprises:
and depositing metal on the back of the wafer.
Compared with the prior art, the application has the beneficial effects that:
The invention provides a wafer back roughening control method and a power device manufacturing method, wherein the wafer back roughening control method comprises the following steps: performing a first etching process on the back of the wafer to reduce cracks on the back of the wafer, performing a second etching process on the back of the wafer to enable the back of the wafer to have roughness, and performing a third etching process on the back of the wafer to reduce or eliminate peaks on the back of the wafer; the power device manufacturing method comprises the wafer back roughening control method, and then metal deposition is carried out on the wafer back. By adopting the scheme of the invention, the sharp wave crest and the sharp edge angle on the back of the wafer are slightly etched by the liquid medicine and are incompletely smoothed, so that the purpose of smoothing the wave crest and the sharp edge angle is achieved, and the technical problem of falling caused by poor metal adhesion is solved.
Drawings
FIG. 1 is a flow chart of a wafer backside roughening control method in an embodiment of the invention;
FIG. 2 is a schematic diagram of a second etching process performed on the back surface of a wafer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a third etching process performed on the back surface of a wafer according to an embodiment of the present invention;
FIG. 4 is a SEM image of the back surface of a wafer after a second etching process is performed in accordance with one embodiment of the present invention;
FIG. 5 is an SEM image of a wafer after a third etching process is performed on the wafer back side in accordance with one embodiment of the present invention;
Wherein,
10-Wafer, 100-wafer substrate, 101-wafer back interface after performing the second etching process, 102-wafer back interface after performing the third etching process, 101 a-wafer back interface spike after performing the second etching process, 102 a-wafer back interface spike slightly etched after performing the third etching process.
Detailed Description
In the wafer back side metal process, when the wafer back side is polished to below 200 microns, a special chemical mixture etchant (typically a mixture of H 2SO4、HNO3 and HF) is used to etch the surface of the silicon wafer, providing a matte and roughened surface of the back side metal. However, the inventors have found that oxidation and outgassing (out-gassing) occur while the silicon wafer is etched, thereby creating roughness on the surface of the silicon wafer.
Wet chemical etching can provide a uniform roughness of the wafer surface of between 0.44 microns and 1.77 microns. The roughening of the wafer surface may be accomplished by using different chemical etchants and temperatures to provide optimized backside metal adhesion. Because the surface is chemically treated, damage resulting from back grinding can be removed by chemical reaction to obtain the optimal back metal roughness surface.
The surface roughness is expressed in terms of total index deviation (total indicator run-out, TIR) which is estimated from the maximum peak height value subtracted by the minimum peak value between the lengths of the line scans by the scan test device. A roughness average (Ra) is also calculated, which represents the average of roughness between the lengths of the line scans. Surface roughness provides additional contact area and is therefore a very important parameter for improving wafer surface adhesion.
The conventional formula is that etching liquid (mixed liquid of H 2SO4、HNO3 and HF) is used for etching the silicon surface, and the treated interface can obtain good roughness, but the formula has randomness due to the influence of the roughness, cracks and the like of the polished wafer surface caused by chemical reaction, so that relatively sharp wave peaks and edges exist on the surface. In a power device, metal is deposited on the back of a wafer to serve as a drain end of the device, a peak with too sharp contact interface between silicon and metal is easy to cause charge aggregation, current at the peak is higher than that at a smooth position, heat load is too high, and metal adhesion is poor, so that the drop is caused.
Based on the above findings, the present invention provides a wafer back surface roughening control method, which comprises performing a first etching process on the wafer back surface to reduce cracks on the wafer back surface, performing a second etching process on the wafer back surface to enable the wafer back surface to have roughness, and performing a third etching process on the wafer back surface to reduce or eliminate peaks on the wafer back surface. By adopting the scheme of the invention, the sharp wave crest and the sharp edge angle on the back of the wafer are slightly etched by the liquid medicine and are incompletely smoothed, so that the purpose of smoothing the wave crest and the sharp edge angle is achieved, and the technical problem of falling caused by poor metal adhesion is solved.
The following describes a method for controlling the roughening of the back surface of a wafer according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
Fig. 1 is a flowchart of a wafer back surface roughening control method according to an embodiment of the present invention, as shown in fig. 1, specifically including the following steps:
step S11: performing a first etching process on the back of the wafer to reduce cracks on the back of the wafer; the etching solution of the first etching process is mixed solution of H 2SO4、H3PO4、HNO3 and HF, the temperature of the etching solution of the first etching process is 25-35 ℃ for example, the etching time of the back surface of the wafer in the etching solution of the first etching process is 30-80 seconds for example, and the thickness of the back surface of the wafer is thinned by 7-15 mu m.
The etching temperature of the first etching process in the embodiment of the present invention may be 28 ℃, which is not limited by the present invention.
For example, in the embodiment of the present invention, the etching time of the first etching process may be 34 seconds, where the etching time may reduce the thickness of the back surface of the wafer by 8 μm; in the embodiment of the invention, the etching time of the first etching process can be 70 seconds, and the thickness of the back surface of the wafer can be thinned by 14 mu m; the invention is not limited.
Step S12: performing a second etching process on the back surface of the wafer so that the back surface of the wafer can have roughness; the etching liquid of the second etching process is mixed liquid of H 2SO4、HNO3 and HF, the temperature of the etching liquid of the second etching process is 30-40 ℃ for example, the etching time of the back surface of the wafer in the etching liquid of the second etching process is 50-80 seconds for example, and the thickness of the back surface of the wafer is thinned by 3-6 mu m.
Fig. 2 is a schematic diagram of the wafer 10 including the semiconductor substrate 100 and the interface 101 of the wafer on the semiconductor substrate 100 after the second etching process is performed, as shown in fig. 2, after the second etching process is performed on the wafer back in the embodiment of the present invention.
The Active Area (AA) may be formed on the front surface of the semiconductor substrate 100, and in addition, an isolation structure, such as a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, may be formed on the front surface of the semiconductor substrate 100, which is not limited by the present invention.
It should be noted that, the present embodiment mainly provides a method for controlling the roughening of the back surface of the wafer, so that the following description is facilitated, the corresponding drawing portions only show a part of the wafer, and other structures and devices on the wafer are omitted, but those skilled in the art will know how to implement the present invention according to the disclosure of the present invention and with the common knowledge of those skilled in the art.
Steps S11 and S12 are performed, where the first etching process and the second etching process are performed on the back surface of the wafer, so as to obtain roughening treatment on the back surface of the wafer, so as to obtain etching of the silicon surface, and the treated interface may obtain good roughness, so as to obtain the interface 101 after the second etching process is performed on the back surface of the wafer, as shown in fig. 2.
Step S13: and performing a third etching process on the back surface of the wafer to eliminate the peak of the back surface of the wafer. The etching liquid of the third etching process is the mixed liquid of HNO 3 and HF, the mixed liquid is formed by mixing HNO 3 with the concentration of 70% and HF with the concentration of 49% according to the volume ratio of the etching liquid of the third etching process is 5:1-200:1, the temperature range of the etching liquid of the third etching process is adjustable within the range of 20-65 ℃, and the etching time of the etching liquid of the third etching process is less than 120 seconds.
The etching solution of the third etching process in the embodiment of the present invention is a mixed solution of HNO3 and HF, specifically, a 70% HNO 3 solution and a 49% HF solution are mixed according to a volume ratio of 9:1, the etching temperature is 25 ℃, and the etching time is 3 seconds, which is not limited by the present invention.
Fig. 3 is a schematic diagram of a third etching process performed on the back surface of the wafer according to an embodiment of the present invention. As shown in fig. 3, the wafer 10 includes a semiconductor substrate 100, and an interface 102 on the semiconductor substrate 100 after a third etching process is performed on the wafer backside.
The inventor researches that the wafer is made of monocrystalline silicon material, the sharp peaks and edges on the back are also monocrystalline silicon, and the HNO 3 and HF mixed solution can react with the monocrystalline silicon on the surface of the wafer. Wherein HNO 3 oxidizes Si to SiO 2, and HF reacts with SiO 2 to generate soluble silicic acid which is dissolved in the liquid medicine. Under proper conditions, the sharp peaks and corners are slightly etched by the liquid medicine, and are not completely smoothed, so that the purpose of smoothing the peaks and corners is achieved, such as the interface 102 of the wafer back surface subjected to the third etching process shown in fig. 3.
The reaction equation is:
Si+4HNO3→SiO2+4NO2+2H2O (1)
SiO2+6HF→H2SiF6+2H2O (2)
Fig. 4 is an SEM image of the back surface of a wafer after performing the second etching process according to the method of the embodiment of the invention, and fig. 5 is an SEM image of the back surface of a wafer after performing the third etching process according to the method of the embodiment of the invention. In fig. 4, 101a is an SEM image of a peak of the interface 101 after the second etching process is performed on the back surface of the wafer, and in fig. 5, 102a is an SEM image of a slightly etched peak of the interface 102 after the third etching process is performed on the back surface of the wafer, as can be seen by comparing fig. 4 and 5, the wafer back surface roughening control method provided in the embodiment can significantly reduce or eliminate the peak on the back surface of the wafer.
The invention also provides a method for manufacturing the power device, which is characterized in that the corresponding power device is obtained by adopting the wafer back roughening control method, and the step S13 of performing the third etching process on the wafer back further comprises the following steps:
step S14: and carrying out metal deposition on the back of the wafer.
In this embodiment, the wafer is subjected to metal sputtering, where metal sputtering is performed on the back surface of the wafer, and the back surface of the wafer is generally used as the Drain (Drain) of the device, and the sputtered metal is used to reduce the resistance of the back surface. In the preferred embodiment of the invention, ti, ni and Ag metals or Ti, ni and Au metals are plated on the back of the wafer in sequence. The Ti metal and the wafer can form metal silicide, so that contact resistance can be reduced, the Ni metal can well connect the Ti metal and Ag or Au metal together, the buffer layer is equivalent to a buffer layer between the two layers of metals, and the Ag or Au is a very good conductor and has relatively high conductivity.
In summary, the wafer back roughening control method of the invention processes the wafer back by adding the third etching process, and under proper conditions, sharp peaks and edges of the wafer back are slightly etched by the liquid medicine and incompletely smoothed, thereby achieving the purpose of smoothing the peaks and the edges, and solving the technical problems that the deposition metal on the wafer back is used as the drain end of the device, the peak with too sharp contact interface between silicon and metal is easy to cause charge aggregation, the current at the peak is higher than that at the smooth position, the heat load is too high, and the metal adhesion is not good, so that the shedding is caused. The power device obtained after the wafer back roughening control method is used for processing has the advantages that the thermal load of the contact interface of silicon and metal is uniform, the metal adhesiveness is good, and the silicon and metal are not easy to fall off.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (6)
1. The wafer back roughening control method is characterized by comprising the following steps of:
Performing a first etching process on the back of the wafer to reduce cracks on the back of the wafer;
performing a second etching process on the back surface of the wafer so as to enable the back surface of the wafer to have roughness; and
Performing a third etching process on the back surface of the wafer to reduce peaks on the back surface of the wafer;
in the first etching process, the etching solution is a mixed solution of H 2SO4、H3PO4、HNO3 and HF, in the second etching process, the etching solution is a mixed solution of H 2SO4、HNO3 and HF, and in the third etching process, the etching solution is a mixed solution of HNO 3 and HF; in the third etching process, the volume ratio of HNO 3 to HF is 5:1-200:1, the temperature of etching liquid in the third etching process is 20-65 ℃, and the etching time in the third etching process is less than 120 seconds.
2. The method according to claim 1, wherein in the third etching process, a 70% hno 3 solution and a 49% hf solution are mixed according to a volume ratio of 9:1, and the etching temperature is 25 ℃ and the etching time is 3 seconds.
3. The method of claim 1, wherein the etching solution of the first etching process has a temperature of 25 ℃ to 35 ℃ and an etching time of 30 seconds to 80 seconds.
4. The method of claim 1, wherein the etching solution temperature of the second etching process is 30-40 ℃ and the etching time is 50-80 seconds.
5. A method of manufacturing a power device, comprising:
the wafer backside roughening control method according to any one of claims 1 to 4.
6. The power device manufacturing method of claim 5, further comprising:
and depositing metal on the back of the wafer.
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| CN118098933A (en) * | 2024-04-25 | 2024-05-28 | 汉轩微电子制造(江苏)有限公司 | Wafer back surface metallization method and wafer |
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