CN112038382B

CN112038382B - Display panel, preparation method thereof and display device

Info

Publication number: CN112038382B
Application number: CN202010949187.5A
Authority: CN
Inventors: 包征; 辛燕霞
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-09-10
Filing date: 2020-09-10
Publication date: 2022-11-04
Anticipated expiration: 2040-09-10
Also published as: CN112038382A

Abstract

The embodiment of the application provides a display panel, a preparation method of the display panel and a display device. The display panel includes: the display device comprises a substrate, a first metal signal line layer and an interlayer dielectric layer, wherein the periphery area of the substrate comprises the first metal signal line layer and the interlayer dielectric layer which are arranged in a stacked mode; the first cofferdam structure comprises a second metal signal line layer and a supporting layer, wherein the second metal signal line layer and the supporting layer are sequentially stacked on one side, away from the first metal signal line layer, of the interlayer dielectric layer. The embodiment of the application strengthens the stability of the first cofferdam structure and reduces the risk of breakage of the first cofferdam structure, thereby avoiding the defect of the first cofferdam structure, causing bad risks and influencing the quality of the display panel.

Description

Display panel, preparation method thereof and display device

Technical Field

The application relates to the technical field of display panels, in particular to a display panel, a preparation method thereof and a display device.

Background

In a flexible OLED (Organic Light-Emitting Diode) product, a Dam structure Dam is usually disposed at an edge of a Panel of a display Panel, and is generally formed by grooving an edge of a PLN (planarizing Layer) or a PDL (Pixel definition Layer), so that on one hand, an ink overflow of IJP in a Thin-Film Encapsulation (TFE) can be blocked, and on the other hand, the edge grooving process can separate the PLN/PDL in an AA (Active Area, effective display Area) region from the PLN/PDL in a peripheral Area. As the PLN/PDL material belongs to organic matters, the organic matters are easy to absorb water, and the groove digging treatment can block the invasion of external water and oxygen, thereby forming better packaging effect.

At present, many metal signal lines are led out from the Pad side (the side of the driving IC chip) of the bonding area to enter the AA area, and the metal signal lines in the peripheral area cause unevenness on the surface of the substrate.

In the BP front-end process, there are many cleaning (such as spraying, air knife, etc.) processes, and these cleaning processes may cause the missing of the Pad side wall weir structure Dam, thereby causing adverse risks and affecting the quality of the display panel.

Disclosure of Invention

The application provides a display panel, a preparation method thereof and a display device aiming at the defects of the prior art, and aims to solve the technical problem that the quality of the display panel is influenced by the defect of a cofferdam structure Dam of the display panel in the prior art.

In a first aspect, an embodiment of the present application provides a display panel, including:

the display device comprises a substrate, a first metal signal line layer and an interlayer dielectric layer, wherein the periphery area of the substrate comprises the first metal signal line layer and the interlayer dielectric layer which are arranged in a stacked mode;

the first cofferdam structure comprises a second metal signal line layer and a supporting layer, wherein the second metal signal line layer and the supporting layer are sequentially arranged on one side, away from the first metal signal line layer, of the interlayer dielectric layer in a stacking mode.

In one possible implementation, the first cofferdam structure further includes:

and the pixel defining layer is arranged on one side of the interlayer dielectric layer far away from the first metal signal line layer, and at least filled on two sides of the width direction of the second metal signal line layer, wherein the width direction is along the direction from the display area of the substrate to the peripheral area of the substrate.

In one possible implementation manner, the pixel defining layer is provided with a through hole in a corresponding area of the second metal signal line layer, so that one side of the second metal signal line layer, which is far away from the interlayer dielectric layer, is exposed;

and the through hole is filled at one side of the supporting layer close to the second metal signal line layer.

In one possible implementation, the second metal signal line layer includes at least one second metal signal line;

the adjacent second metal signal lines are arranged at intervals;

the pixel definition layer is provided with a through hole in the corresponding area of each second metal signal line.

In one possible implementation, the first cofferdam structure includes at least one of:

the width of the first cofferdam structure is 45-50 um;

the width of the second metal signal line is 3um ~ 5um.

The width of one side of the via hole, which is far away from the second metal signal line, is 3-4 um;

the width of one side of the via hole close to the second metal signal line is not more than the width of one side of the via hole far away from the second metal signal line.

In one possible implementation, the substrate further includes:

the first grid insulation layer is arranged on one side of the first metal signal line layer far away from the interlayer dielectric layer.

In one possible implementation, the substrate further includes:

the third metal signal line layer is arranged on one side, far away from the first metal signal line layer, of the first grid insulation layer;

and the second grid insulation layer is arranged on one side of the third metal signal line layer, which is far away from the first grid insulation layer.

In one possible implementation manner, a second cofferdam structure is arranged on one side of the first cofferdam structure, which is far away from the display area of the display panel;

the second cofferdam structure and the first cofferdam structure are positioned at the same side of the substrate;

the height of the second cofferdam structure in the direction vertical to the base is larger than that of the first cofferdam structure in the direction vertical to the base.

In a second aspect, an embodiment of the present application further provides a display device, including: such as the display panel of the first aspect.

In a third aspect, an embodiment of the present application further provides a method for manufacturing a display panel, including:

sequentially preparing and forming a first metal signal line layer and an interlayer dielectric layer in the peripheral area of the substrate;

preparing and forming a second metal signal line layer in the first cofferdam structure on one side of the interlayer dielectric layer far away from the first metal signal line layer;

and preparing and forming a supporting layer in the first cofferdam structure on one side of the second metal signal line layer far away from the interlayer dielectric layer.

In one possible implementation manner, preparing the second metal signal line layer in the first dam structure on a side of the interlayer dielectric layer away from the first metal signal line layer and preparing the support layer in the first dam structure on a side of the second metal signal line layer away from the interlayer dielectric layer further include:

and preparing and forming a pixel definition layer on one side of the interlayer dielectric layer, which is far away from the first metal signal line layer, so that the pixel definition layer is at least filled on two sides of the second metal signal line layer in the width direction, and the width direction is along the direction from the display area of the substrate to the peripheral area of the substrate.

In one possible implementation, preparing and forming a pixel defining layer on a side of the interlayer dielectric layer away from the first metal signal line layer includes:

forming a via hole in a region of the pixel definition layer corresponding to the second metal signal line layer, so that one side of the second metal signal line layer, which is far away from the interlayer dielectric layer, is exposed;

preparing a support layer in a first cofferdam structure on one side of the second metal signal line layer far away from the interlayer dielectric layer, wherein the support layer comprises:

and preparing and forming a supporting layer on one side of the pixel defining layer and the second metal signal line layer, which is far away from the interlayer dielectric layer, so that the through holes are filled on one side of the supporting layer, which is close to the second metal signal line layer.

In one possible implementation, preparing a second metal signal line layer in a first bank structure on a side of the interlayer dielectric layer away from the first metal signal line layer includes:

forming a second metal layer to be etched on one side of the interlayer dielectric layer, which is far away from the first metal signal line layer; the second metal layer is formed by adopting a sputtering process;

etching the second metal layer to form a second metal signal line layer comprising at least one second metal signal line; and the adjacent second metal signal lines are arranged at intervals, and the second metal signal line layer is formed by adopting dry etching.

The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:

the display panel of the embodiment of the application adds the second metal signal line layer in the first cofferdam structure, the second metal signal line layer is a metal layer, the surface adhesion with the interlayer dielectric layer is stronger, the stability of the first cofferdam structure is enhanced, the fracture risk of the first cofferdam structure is reduced, and therefore the defect of the first cofferdam structure is avoided, the bad risk is caused, and the quality of the display panel is influenced. Simultaneously, the first cofferdam structure of this application embodiment is including range upon range of second metal signal line layer and the supporting layer that sets up, and the adhesion of second metal signal line layer and supporting layer is also stronger, has further strengthened the steadiness of first cofferdam structure, reduces first cofferdam structure fracture risk.

The display panel of the embodiment of the application only needs to modify the Mask of the second metal signal line layer, does not need to add a new process, and is convenient in preparation process and easy to implement.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another display panel provided in the embodiment of the present application;

fig. 3 is a schematic structural diagram of another display panel provided in the embodiment of the present application;

fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another display panel provided in the embodiment of the present application;

fig. 6 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;

fig. 7 to 19 are schematic structural diagrams in sequence in the manufacturing process of the display panel shown in fig. 2.

Reference numerals:

100-substrate, 110-first metal signal line layer, 120-interlayer dielectric layer, 130-first gate insulating layer, 140-third metal signal line layer, 150-second gate insulating layer, 180-packaging layer, 181-first packaging layer, 182-second packaging layer, 190-polyimide layer, 101-first sub-substrate, 102-second sub-substrate;

200-a first cofferdam structure, 210-a second metal signal line layer, 211-a second metal signal line, 220-a supporting layer, 230-a pixel defining layer and 231-a via hole;

300-second cofferdam structure.

Detailed Description

Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is unnecessary for the features of the present application shown, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.

An embodiment of the present application provides a display panel, as shown in fig. 1, 2 and 3, including: a substrate 100 and a first bank structure 200.

The peripheral region of the substrate 100 includes a first metal signal line layer 110 and an interlayer dielectric layer 120, which are stacked. Optionally, other layers may or may not be disposed between the first metal signal line layer 110 and the interlayer dielectric layer 120.

The first bank structure 200 includes a second metal signal line layer 210 and a support layer 220, and the second metal signal line layer 210 and the support layer 220 are sequentially stacked on one side of the interlayer dielectric layer 120 away from the first metal signal line layer 110. Optionally, the second metal signal line layer 210 is adjacent to the interlayer dielectric layer 120, and one side of the second metal signal line layer 210 close to the interlayer dielectric layer 120 is attached to the surface of the interlayer dielectric layer 120, so that the structure of the first dam structure 200 is more stable.

As shown in fig. 4 and fig. 5, the inventors of the present application have found through research that many metal signal lines are led out from the Pad side (the driver IC chip side) of the bonding region into the AA region, and the metal signal lines located in the peripheral region cause unevenness on the substrate surface. Also, the width of the first bank structure 200 is generally narrow, about 50 μm (micrometer). This results in a smaller adhesion ratio of the first bank structure 200 to the surface of the interlayer dielectric layer 120. In the BP front-end process, there are many cleaning (e.g., spraying, air knife, etc.) processes that can cause the absence of the first cofferdam structure 200 at the Pad side of the bonding area.

Based on the above analysis, the display panel according to the embodiment of the present application adds the second metal signal line layer 210 to the first cofferdam structure 200, and the second metal signal line layer 210 is a metal layer, and has stronger surface adhesion with the interlayer dielectric layer 120, so that the stability of the first cofferdam structure 200 is enhanced, and the risk of fracture of the first cofferdam structure 200 is reduced, thereby avoiding the problem that the quality of the display panel is affected due to the bad risk caused by the lack of the first cofferdam structure 200. Meanwhile, the first cofferdam structure 200 of the embodiment of the application includes the second metal signal line layer 210 and the support layer 220 which are stacked, and the adhesion of the second metal signal line layer 210 and the support layer 220 is stronger, so that the stability of the first cofferdam structure 200 is further enhanced, and the risk of breaking the first cofferdam structure 200 is reduced. By applying the display panel of the embodiment of the application, only the Mask of the second metal signal line layer 210 needs to be modified, no new process needs to be added, the preparation process is convenient, and the implementation is easy.

The structure of the display panel according to the embodiment of the present application is described below by taking the schematic structure of the display panel shown in fig. 1 as an example.

Alternatively, as shown in fig. 1, the interlayer dielectric layer 120 and the first metal signal line layer 110 are adjacent without additional film layers therebetween. In practical applications, the interlayer dielectric layer 120 and the first metal signal line layer 110 may be further provided with other layers according to the circumstances.

Optionally, referring to fig. 1, the first cofferdam structure 200 further includes: a pixel definition layer 230.

The pixel definition layer 230 is disposed on a side of the interlayer dielectric layer 120 away from the first metal signal line layer 110, and the pixel definition layer 230 at least fills two sides of the second metal signal line layer 210 in a width direction, the width direction being a direction from the display region of the substrate 100 to the peripheral region of the substrate 100.

Optionally, referring to fig. 1, the pixel definition layer 230 has a via hole 231 in a corresponding area of the second metal signal line layer 210, such that a side of the second metal signal line layer 210 away from the interlayer dielectric layer 120 is exposed. The side of the support layer 220 adjacent to the second metal signal line layer 210 fills the via 231.

The support layer 220 of the embodiment of the application is directly connected with the second metal signal line layer 210 through the via hole 231, so that the contact area of the support layer 220 is increased, and the stability of the first cofferdam structure 200 is further enhanced.

Alternatively, referring to fig. 1 and 13, the second metal signal line layer 210 includes at least one second metal signal line 211. The adjacent second metal signal lines 211 are disposed at intervals. The pixel defining layer 230 has a via hole 231 at a corresponding region of each of the second metal signal lines 211.

Alternatively, 4 second metal signal lines 211 may be provided according to a preset condition. Specifically, according to actual needs, the width of the second metal signal line 211 can be adjusted, so as to adjust the number of the second metal signal lines 211.

Optionally, referring to fig. 1, the first cofferdam structure 200 comprises at least one of:

the width a of the first dam structure 200 is 45um to 50um.

The width b of the second metal signal line 211 is 3um to 5um.

The width c of the via hole 231 away from the second metal signal line 211 is 3um to 4um.

The width of the via hole 231 on the side close to the second metal signal line 211 is not greater than the width of the via hole 231 on the side far from the second metal signal line 211.

Optionally, the width a of the first bank structure 200 may be 45um and 50um, the width b of the second metal signal line 211 may be 3um and 5um, and the width c of the side of the via hole 231 away from the second metal signal line 211 may be 3um and 4um.

Optionally, as an example, the width a of the first bank structure 200 may be 50um, the width b of the second metal signal line 211 may be 5um, and the width c of the side of the via hole 231 far away from the second metal signal line 211 may be 3um.

Alternatively, as shown in fig. 1, the via hole 231 is shaped to have a width gradually increasing in a direction perpendicular to the substrate 100. It will be appreciated by those skilled in the art that the shape of the via 231 may also be gradually smaller or constant in width along a direction perpendicular to the substrate 100, and the shape of the via 231 may be set according to actual conditions.

Alternatively, referring to fig. 1, the first metal signal line layer 110 includes at least one first metal signal line. In the embodiment shown in fig. 1, the first metal signal lines are arranged in the width direction. The first metal signal lines may be disposed in a direction perpendicular to the width direction, that is, in correspondence with the arrangement direction of the second metal signal lines 211.

Optionally, the substrate 100 further comprises: a first gate insulating layer 130. The first gate insulating layer 130 is disposed on a side of the first metal signal line layer 110 away from the interlayer dielectric layer 120.

Optionally, referring to fig. 1, the substrate 100 further comprises: a third metal signal line layer 140 and a second gate insulating layer 150. The third metal signal line layer 140 is disposed on a side of the first gate insulating layer 130 away from the first metal signal line layer 110; the second gate insulating layer 150 is disposed on a side of the third metal signal line layer 140 away from the first gate insulating layer 130.

Alternatively, referring to fig. 1, the structure of the third metal signal line layer 140 is similar to the structure of the first metal signal line layer 110. The third metal signal line layer 140 includes at least one third metal signal line.

Referring to fig. 1, the third metal signal lines are disposed in the width direction. The third metal signal lines may also be disposed in a direction perpendicular to the width direction, i.e., in line with the arrangement direction of the second metal signal lines 211.

In practical applications, if the substrate 100 includes the first metal signal line layer 110 and the third metal signal line layer 140, the first metal signal line of the first metal signal line layer 110 and the third metal signal line of the third metal signal line layer 140 may be disposed perpendicular to each other. The first metal signal line and the third metal signal line may be gate signal lines. Different layers of the first metal signal line and the third metal signal line are overlapped, which is more likely to cause unevenness on the surface of the substrate 100, and the first dam structure 200 according to the embodiment of the present application is more required to be disposed.

Optionally, referring to fig. 1, the substrate 100 further includes a second sub-substrate 102. The second sub-substrate 102 is disposed on a side of the second gate insulating layer 150 away from the third metal signal line layer 140, and the second sub-substrate 102 includes a barrier layer and a buffer layer sequentially stacked.

Optionally, referring to fig. 1, the substrate 100 further includes a polyimide layer 190. The polyimide layer 190 is disposed on a side of the second sub-substrate 102 away from the second gate insulating layer 150.

Optionally, referring to fig. 1, the substrate 100 further includes an encapsulation layer 180, and the encapsulation layer 180 is disposed on a side of the support layer 220 away from the second metal signal line layer 210. Optionally, the encapsulation layer 180 includes a first encapsulation layer 181 and a second encapsulation layer 182, which are sequentially stacked. The encapsulation layer 180 can prevent water and oxygen corrosion on the surface, and does not cause corrosion of the second metal signal line 211 in the reliability verification.

Alternatively, fig. 1 shows a structure of a display panel in which CVD1 and CVD2 correspond to the first and second encapsulation layers 181 and 182, respectively; a PS (Pixel support) corresponding support layer 220; a PDL (Pixel definition Layer) corresponding Pixel definition Layer 230; SD (Signal Data, signal line) corresponds to the second metal Signal line layer 210; an ILD (interlayer dielectric) corresponding to the interlayer dielectric 120; gate (Gate signal line) 1 corresponds to the first metal signal line layer 110; a Gate Insulator (GI) 2 corresponds to the first Gate insulating layer 130; gate2 corresponds to the third metal signal line layer 140; GI1 corresponds to the second gate insulating layer 150; barrier and Buffer correspond to the second sub-substrate 102; PI (Polyimide) corresponds to the Polyimide layer 190.

Referring to fig. 2, another structure of a display panel according to an embodiment of the present application is shown, and the embodiment shown in fig. 2 is different from the embodiment shown in fig. 1 in that: only one first metal signal line layer 110 is disposed in the peripheral region of the substrate 100, and no metal signal line layer may be disposed between the first gate insulating layer 130 and the second gate insulating layer 150. The first gate insulating layer 130 and the second gate insulating layer 150 may also be a gate insulating layer.

Referring to fig. 3, which shows a structure of a display panel according to another embodiment of the present application, only one first metal signal line layer 110 is disposed in a peripheral region of the substrate 100 shown in fig. 3. The embodiment shown in fig. 3 differs from the embodiment shown in fig. 2 in that: the first metal signal line layer 110 is disposed between the first gate insulating layer 130 and the second gate insulating layer 150.

Alternatively, referring to fig. 4, a structure of a display panel according to an embodiment of the present application is shown. The first metal signal line layer 110 is disposed in the substrate 100. The substrate 100 includes a first sub-substrate 101, a first metal signal line layer 110, and a polyimide layer 190.

Optionally, a second cofferdam structure 300 is disposed on a side of the first cofferdam structure 200 away from the display area of the display panel; the second bank structure 300 and the first bank structure 200 are located on the same side of the substrate 100; the height of the second bank structure 300 in the direction perpendicular to the substrate 100 is greater than the height of the first bank structure 200 in the direction perpendicular to the substrate 100.

Alternatively, in the structure of the display panel shown in fig. 4, cathode represents a Cathode layer; a PDL (Pixel definition Layer) corresponding Pixel definition Layer 230; PLN (planarizing layer) denotes a planarizing layer; the first sub-substrate 101 includes a Barrier layer, a Buffer layer, a Gate Insulator (GI), and an interlayer dielectric (ILD) layer stacked; PI (PolyImide) corresponding to the PolyImide layer 190; SD (Singel Line, signal Line) corresponds to the second metal signal Line layer 210; dam1 corresponds to the first cofferdam structure 200; dam2 corresponds to the second cofferdam structure 300; CVD (Chemical Vapor Deposition) corresponding to the encapsulation layer 180; a PS (Pixel support) corresponds to the support layer 220.

Alternatively, the PS layer is prepared using a Half-Tone Half Tone process to form the support layer 220.

Alternatively, referring to fig. 4, the first sub-substrate 101 includes the second sub-substrate 102 of the embodiment shown in fig. 1.

Further research by the inventors of the present application finds that the cleaning (such as spraying, air knife, etc.) process existing in the BP front-end process mainly causes the first cofferdam structure 200 at the Pad side of the bonding area to be missing, and has little influence on the second cofferdam structure 300 at the side of the first cofferdam structure 200 far away from the display area of the display panel. Therefore, in order to facilitate the preparation of the display panel, it is only necessary that the first dam structure 200 includes the second metal signal line layer 210, the requirement of the stability of the structure of the second dam structure 300 is lower than that of the first dam structure 200, and the existing dam structure may be used.

Based on the above analysis, referring to fig. 4, the second bank structure 300 of the embodiment of the present application includes a PS layer, a PDL layer, and a PLN layer, which are sequentially stacked. In practical applications, second cofferdam structure 300 may also be identical to first cofferdam structure 200.

Referring to fig. 5, another structure of a display panel according to an embodiment of the present application is shown. The embodiment shown in fig. 5 differs from the embodiment shown in fig. 3 in that: the support Layer 220 is HPDL (halftone Pixel definition Layer), and a Pixel definition Layer prepared by a halftone hall Tone process is used as the support Layer 220.

Based on the same inventive concept, an embodiment of the present application further provides a display device, including: the display panel of any embodiment of the present application.

Based on the same inventive concept, an embodiment of the present application further provides a method for manufacturing a display panel, as shown in fig. 6, the method for manufacturing a display panel includes the following steps:

s601, sequentially forming a first metal signal line layer 110 and an interlayer dielectric layer 120 in the substrate 100 in the peripheral region of the substrate 100.

S602, forming the second metal signal line layer 210 in the first bank structure 200 on the side of the interlayer dielectric layer 120 away from the first metal signal line layer 110.

S603, preparing and forming the support layer 220 in the first dam structure 200 on the side of the second metal signal line layer 210 away from the interlayer dielectric layer 120.

Alternatively, preparing the second metal signal line layer 210 in the first dam structure 200 on the side of the interlayer dielectric layer 120 away from the first metal signal line layer 110 and preparing the support layer 220 in the first dam structure 200 on the side of the second metal signal line layer 210 away from the interlayer dielectric layer 120, further comprises:

the pixel defining layer 230 is formed on the interlayer dielectric layer 120 away from the first metal signal line layer 110, such that the pixel defining layer 230 at least fills the two sides of the second metal signal line layer 210 in the width direction, which is the direction from the display area of the substrate 100 to the peripheral area of the substrate 100.

Alternatively, the pixel defining layer 230 is formed on the interlayer dielectric layer 120 away from the first metal signal line layer 110, and includes:

forming a via hole 231 in a region of the pixel defining layer 230 corresponding to the second metal signal line layer 210, such that a side of the second metal signal line layer 210 away from the interlayer dielectric layer 120 is exposed;

preparing a support layer 220 for forming the first bank structure 200 on a side of the second metal signal line layer 210 away from the interlayer dielectric layer 120 includes:

the support layer 220 is formed on the side of the pixel defining layer 230 and the second metal signal line layer 210 away from the interlayer dielectric layer 120, such that the side of the support layer 220 close to the second metal signal line layer 210 is filled with the via hole 231.

Alternatively, preparing the second metal signal line layer 210 in the first bank structure 200 on the side of the interlayer dielectric layer 120 away from the first metal signal line layer 110 includes:

forming a second metal layer to be etched on the side of the interlayer dielectric layer 120 far away from the first metal signal line layer 110; the second metal layer is formed by a sputtering process.

Etching the second metal layer to form a second metal signal line layer 210 including at least one second metal signal line 211; the adjacent second metal signal lines 211 are disposed at intervals, and the second metal signal line layer 210 is formed by dry etching.

As an example, in the method for manufacturing a display panel according to the embodiment of the present application, taking the structure of the display panel shown in fig. 2 as an example, the manufacturing process of the display panel shown in fig. 2 is described in detail through the schematic structural diagrams in the method for manufacturing a display panel shown in fig. 7 to 19.

Alternatively, the manufacturing process of the display panel shown in fig. 2 is as follows:

the method comprises the following steps: as shown in fig. 7, a Barrier layer and a Buffer layer are deposited on one side of the PI layer. Specifically, PI (PolyImide) corresponds to the PolyImide layer 190; barrier and Buffer correspond to the second sub-substrate 102.

Step two: referring to fig. 8, a GI1 layer is deposited on the side of the second sub-substrate 102 away from the PI layer. Specifically, a GI (Gate insulator) 1 corresponds to the second Gate insulator 150.

Step three: referring to fig. 9, a GI2 layer is deposited on a side of the GI1 layer away from the second sub-substrate 102. Specifically, GI2 corresponds to the first gate insulating layer 130.

Step four: referring to fig. 10, a metal layer is deposited on the side of the GI2 layer away from the GI1 layer, and the metal layer is etched according to the design, so as to obtain Gate1. Specifically, a Gate (Gate signal line) 1 corresponds to the first metal signal line layer 110.

Step five: referring to fig. 11, an ILD layer is deposited on the Gate1 layer on the side away from the GI2 layer. Specifically, an ILD (interlayer dielectric) corresponds to the interlayer dielectric 120.

Step six: referring to fig. 12, a sputtering Sputter process is used to deposit the SD layer on the side of the ILD layer away from the Gate1 layer. Specifically, SD (signal Line) corresponds to the second metal signal Line layer 210 and is a Ti/Al/Ti metal layer.

Step seven: referring to fig. 13, the Mask of the SD layer is modified, and the SD layer is dry etched to obtain a plurality of second metal signal lines 211 arranged at intervals.

The second metal signal line layer 210 of the embodiment of the application adopts the sputtering Sputter process, the adhesion of the sputtered metal layer and the interlayer dielectric layer 120 of the inorganic layer is stronger, the stability of the first cofferdam structure 200 is enhanced, the fracture risk is reduced, and the Mask of the second metal signal line layer 210 can be modified to realize the process without adding a new process.

Step eight: referring to fig. 14, an Anode layer is deposited on the SD layer on the side away from the ILD layer using a Sputter process. Specifically, the Anode layer is an Anode layer, and includes a first layer of ITO (indium tin oxide), a silver Ag layer, and a second layer of ITO, which are sequentially stacked. The anti layer is filled between the adjacent second metal signal lines 211, and covers a side of the second metal signal lines 211 away from the interlayer dielectric layer 120.

Step nine: referring to fig. 15, the Anode layer is wet etched, and the first ITO and Ag layers of the display region are etched in two steps, and then the first ITO and Ag layers of the SD layer of the peripheral region are removed on the side away from the ILD layer.

Step ten: referring to fig. 16, a second step of etching is performed on the second ITO layer of the Anode layer, and then the second ITO layer on the side of the SD layer away from the ILD layer in the peripheral region is removed.

Two-step etching is adopted after the deposition of the Anode layer, the first ITO layer and the Ag layer are removed in the first step, the second ITO layer is removed in the second step, and dark spots can be effectively avoided.

Step eleven: referring to fig. 17, a PDL layer is formed on the side of the ILD layer away from the Gate1 layer. Specifically, a PDL (Pixel Define Layer) corresponding to the Pixel defining Layer 230 is filled at least at both sides in the width direction of the second metal signal line Layer 210. The PDL layer is formed by a Coating and Curing process.

And etching the PDL layer, and forming a via hole 231 in the region of the PDL layer corresponding to the second metal signal line 211 of the SD layer, so that one side of the second metal signal line 211, which is far away from the ILD layer, is exposed.

Step twelve: referring to fig. 18, the PS layer is prepared on the side of both the PDL layer and the SD layer away from the ILD layer. Specifically, a PS (Pixel support) corresponding support layer 220 is formed using Coating and Curing.

Step thirteen: referring to fig. 18, CVD1 and CVD2 layers are deposited on the PS layer on the side away from the PDL and SD layers. Specifically, CVD1 and CVD2 correspond to the first encapsulation layer 181 and the second encapsulation layer 182, respectively. After covering the PDL layer and the PS layer, CVD2 and CVD1 can block surface water and oxygen corrosion and can not cause the SD layer to be corroded in the reliability verification.

Similarly, the manufacturing process of the display panel shown in fig. 1 and 3 is the same as the principle of the manufacturing process of the display panel shown in fig. 2.

By applying the embodiment of the application, at least the following technical effects can be realized:

(1) The display panel of the embodiment of the application adds the second metal signal line layer 210 in the first cofferdam structure 200, and the second metal signal line layer 210 is a metal layer, and has stronger surface adhesion with the interlayer dielectric layer 120, so that the stability of the first cofferdam structure 200 is enhanced, and the risk of breakage of the first cofferdam structure 200 is reduced, thereby avoiding the problem that the first cofferdam structure 200 is absent, causing bad risk, and affecting the quality of the display panel.

(2) The first cofferdam structure 200 of the embodiment of the application includes the second metal signal line layer 210 and the support layer 220 which are stacked, and the adhesion of the second metal signal line layer 210 and the support layer 220 is stronger, so that the stability of the first cofferdam structure 200 is further enhanced, and the risk of breaking the first cofferdam structure 200 is reduced.

(3) The support layer 220 of the embodiment of the application is directly connected with the second metal signal line layer 210 through the via hole 231, so that the contact area of the support layer 220 is increased, and the stability of the first cofferdam structure 200 is further enhanced.

(4) The requirement for the stability of the structure of the second cofferdam structure 300 of the embodiment of the application is lower than the requirement for the stability of the first cofferdam structure 200, and the second metal signal line layer 210 is not arranged in the second cofferdam structure 300, so that the preparation of the display panel is more convenient and easy to realize.

(5) The encapsulation layer 180 of the embodiment of the application can prevent surface water and oxygen corrosion, and does not cause the second metal signal line 211 to corrode in the reliability verification.

(6) The second metal signal line layer 210 of the embodiment of the application adopts the sputtering Sputter process, the adhesion of the sputtered metal layer and the interlayer dielectric layer 120 of the inorganic layer is stronger, the stability of the first cofferdam structure 200 is enhanced, the fracture risk is reduced, and the Mask of the second metal signal line layer 210 can be modified to realize the process without adding a new process.

Those of skill in the art will understand that various operations, methods, steps in the flow, measures, schemes discussed in this application can be alternated, modified, combined, or deleted. Further, various operations, methods, steps, measures, schemes in the various processes, methods, procedures that have been discussed in this application may be alternated, modified, rearranged, decomposed, combined, or eliminated. Further, the steps, measures, and schemes in the various operations, methods, and flows disclosed in the present application in the prior art can also be alternated, modified, rearranged, decomposed, combined, or deleted.

In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A display panel, comprising:

the device comprises a substrate, a first metal signal line layer and an interlayer dielectric layer, wherein the periphery area of the substrate comprises the first metal signal line layer and the interlayer dielectric layer which are arranged in a stacked mode;

the first cofferdam structure comprises a second metal signal line layer, a supporting layer and a pixel defining layer, wherein the second metal signal line layer and the supporting layer are sequentially stacked on one side of the interlayer dielectric layer, which is far away from the first metal signal line layer;

the pixel definition layer is arranged on one side, far away from the first metal signal line layer, of the interlayer dielectric layer, and at least filled on two sides of the second metal signal line layer in the width direction, wherein the width direction is the direction from the display area of the substrate to the peripheral area of the substrate;

the pixel defining layer is provided with a through hole in a corresponding area of the second metal signal line layer, so that one side of the second metal signal line layer, which is far away from the interlayer dielectric layer, is exposed; and one side of the supporting layer, which is close to the second metal signal line layer, is filled with the through hole.

2. The display panel of claim 1, wherein the second metal signal line layer comprises at least one second metal signal line;

the adjacent second metal signal lines are arranged at intervals;

the pixel definition layer is provided with the through hole in the corresponding area of each second metal signal line.

3. The display panel of claim 2, wherein the first bank structure comprises at least one of:

the width of the first cofferdam structure is 45-50 um;

the width of the second metal signal line is 3 um-5 um;

the width of one side, close to the second metal signal line, of the via hole is not larger than the width of one side, far away from the second metal signal line, of the via hole.

4. The display panel according to claim 1, wherein the substrate further comprises:

and the first grid insulating layer is arranged on one side of the first metal signal line layer far away from the interlayer dielectric layer.

5. The display panel according to claim 4, wherein the substrate further comprises:

and the second grid insulation layer is arranged on one side, far away from the first grid insulation layer, of the third metal signal line layer.

6. The display panel according to claim 1, wherein a side of the first cofferdam structure away from the display area of the display panel is provided with a second cofferdam structure;

the second cofferdam structure and the first cofferdam structure are positioned on the same side of the substrate;

7. A display device, comprising: the display panel of any one of claims 1-6.

8. A method for manufacturing a display panel, comprising:

sequentially preparing and forming a first metal signal line layer and an interlayer dielectric layer in the substrate in the peripheral area of the substrate;

preparing and forming a second metal signal line layer in a first cofferdam structure on one side of the interlayer dielectric layer far away from the first metal signal line layer;

preparing and forming a pixel definition layer on one side of the interlayer dielectric layer, which is far away from the first metal signal line layer, so that the pixel definition layer is at least filled on two sides of the second metal signal line layer in the width direction, a via hole is formed in the area of the pixel definition layer, which corresponds to the second metal signal line layer, and one side of the second metal signal line layer, which is far away from the interlayer dielectric layer, is exposed; the width direction is a direction from the display area of the substrate to the peripheral area of the substrate;

and preparing and forming a supporting layer on one side of the pixel defining layer and one side of the second metal signal line layer, which are far away from the interlayer dielectric layer, so that the through hole is filled on one side of the supporting layer, which is close to the second metal signal line layer.

9. The method according to claim 8, wherein the step of forming a second metal signal line layer in a first bank structure on a side of the interlayer dielectric layer away from the first metal signal line layer comprises:

etching the second metal layer to form a second metal signal line layer comprising at least one second metal signal line; and the second metal signal line layer is formed by adopting dry etching.