CN112035382A - Method and apparatus for low latency access to FTL - Google Patents

Abstract

Methods and apparatus for low latency access to FTLs are provided. A method of accessing an FTL is provided, comprising: sending a preloading request for the FTL table entry of the specified address so as to load the specified FTL table entry into the storage position indicated by the first index of the FTL table entry storage component; and issuing a read request for the FTL entry of the first index to obtain the FTL entry of the first index from the FTL entry storage unit.

Description

Method and apparatus for low latency access to FTL

Technical Field

The invention relates to a storage device controller, in particular to a method and a device for accessing an FTL (flash Translation layer) in the storage device controller.

Background

In the solid-state storage device, mapping information from logical addresses to physical addresses is maintained using FTL (Flash Translation Layer). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented in the prior art using an intermediate address modality. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device. FTL tables of solid state memory devices have large sizes, e.g., several GB levels.

The FTL table includes a plurality of FTL table entries (or table entries). An example of an FTL table structure is provided in chinese patent application No. 201510430174.6. In one example, each FTL table entry records a corresponding relationship between a logical page address and a physical page. In yet another example, each FTL table entry records the corresponding relationship between the logical block address and the physical block address. In still another example, the FTL table records the mapping relationship between logical block addresses and physical block addresses, and/or the mapping relationship between logical page addresses and physical page addresses. The FTL table entry may also record the mapping relationship of the logical address and one or more physical addresses.

In yet another example, FTL tables are stored in a contiguous memory address space, a physical address is recorded in each FTL table entry, and a logical address corresponding to the physical address is represented by the memory address of each FTL table entry itself. The number of FTL table entries corresponds to the size of the solid state storage device logical address space.

The flash controller needs to frequently access the FTL when operating. When reading the flash memory, the FTL is queried by the logical address to obtain the physical address of the flash memory storing data. When writing into the flash memory, a physical address is allocated for the written data, and the correspondence between the written logical address and the physical address is recorded in the FTL. When operations such as GC and erasure equalization occur, the mapping relationship between the logical address and the physical address changes, and the FTL needs to be updated.

There are a number of solutions for accessing the FTL.

FTL features include large number of entries (hundreds of millions of FTL entries are managed in common SSD), small size of each entry (about a few to a few tens of bytes), and strong randomness (access to FTL entries is distributed in whole entry space and lacks locality). And since a large capacity of FLASH is supported, it is often necessary to access a space exceeding 4 GB.

To store GB-level data, DRAM is generally used. The access delay of DRAM cannot match the high-speed processing components such as CPU, and the processing performance of the flash memory controller is seriously affected. Traditionally, Cache is used as an intermediate storage layer to provide high-speed data access capability for the CPU by caching a portion of the data in the DRAM.

However, due to the randomness of FTL table access, even if Cache is used to Cache FTL table, Cache thrashing may be caused by frequent page changing, and FTL access capability may not be significantly improved.

For example, when accessing FTL entry a, first read the address of entry a stored in DRAM, the randomness of FTL entry access, entry a is unlikely to already exist in Cache, so it can be considered that Cache always misses, and entry a needs to be read from external DRAM memory to Cache, and the latency penalty is about above 100 ns.

Due to the storage of the FTL table, the memory size of DRAM in the system often exceeds 4GB, and a conventional 32-bit address access method cannot access an address space exceeding 4GB, thereby requiring the use of TLB. The upper address is obtained by accessing the TLB and the addresses are combined to generate an access to the DRAM. And the TLB access and address combination process further increases access latency.

The FTL can also be accessed using DMA. When accessing the FTL, it needs to configure the high order bits of the address, the low order bits of the address, and then move the FTL to the space that the CPU can directly access (or the low latency can access) by triggering DMA, such as the low 4G DDR or the SRAM of the system. However, the drawbacks of this solution are also evident: the process of configuring DMA takes time and CPU access latency can be significant. And because of the participation of DMA, the problem of memory consistency needs to be considered.

Also, when the size of FTL entries changes, the access latency of the FTL is further increased.

Disclosure of Invention

According to a first aspect of the present invention, there is provided a first apparatus for accessing an FTL according to the first aspect of the present invention, including an FTL entry address storing unit that stores a plurality of FTL entry addresses, an FTL entry data storing unit, a CPU interface, and a main memory interface; the FTL entry data storage component stores a plurality of FTL entry data; accessing the FTL table entry address and the FTL table entry data associated therewith in the FTL table entry address storage component and the FTL table entry data storage component, respectively, by the same index, where the FTL table entry address is a storage address of the FTL table entry data associated therewith in the main memory; responding to a preloading request of a CPU interface for receiving an FTL table entry of a specified address, acquiring the FTL table entry from a main memory through a main memory interface, wherein the preloading request also specifies a first index which indicates the storage position of the FTL table entry of the specified address in an FTL table entry data storage component; and providing the FTL table entry to the CPU through the CPU interface in response to the CPU interface receiving a read request for the FTL table entry of the first index.

According to a first apparatus for accessing an FTL of a first aspect of the present invention, there is provided a second apparatus for accessing an FTL according to the first aspect of the present invention, wherein after receiving a preload request for an FTL entry of a specified address, the apparatus for accessing an FTL processes the load request in an asynchronous manner; and after receiving a read request for the FTL entry of the first index, the apparatus for accessing the FTL processes the read request in a synchronous manner.

The first or second apparatus for accessing an FTL according to the first aspect of the present invention provides a third apparatus for accessing an FTL according to the first aspect of the present invention, wherein after receiving a read request for an FTL entry of a first index, if an FTL entry of a specified address does not exist in the FTL entry data storage unit, it waits for the FTL entry of the specified address to be loaded into the FTL entry data storage unit from a main memory.

According to one of the first to third means for accessing FTL of the first aspect of the present invention, there is provided a fourth means for accessing FTL of the first aspect of the present invention, wherein the obtaining FTL entries from main memory through main memory interface further comprises: and locking FTL table entries of the main memory specified address.

According to a second aspect of the present invention, there is provided a first apparatus for accessing an FTL according to the second aspect of the present invention, including an FTL entry address storing unit that stores a plurality of FTL entry addresses, an FTL entry data storing unit, a CPU interface, and a main memory interface; the FTL entry data storage component stores a plurality of FTL entry data; accessing the FTL table entry address and the FTL table entry data associated therewith in the FTL table entry address storage component and the FTL table entry data storage component, respectively, by the same index, where the FTL table entry address is a storage address of the FTL table entry data associated therewith in the main memory; in response to the CPU interface receiving an update request for the FTL table entry of the first index, updating FTL table entry data indicated by the first index in the FTL table entry data storage component; and in response to the CPU interface receiving a write-over request for the FTL table entry of the first index, writing the FTL table entry data specified by the first index into the main memory through the main memory interface according to the FTL table entry address specified by the first index.

According to a first apparatus for accessing an FTL of a second aspect of the present invention, there is provided a second apparatus for accessing an FTL of the second aspect of the present invention, wherein after receiving an FTL entry update request, the apparatus for accessing an FTL processes the FTL entry update request in a synchronous manner; after receiving the FTL entry refresh request, the apparatus for accessing FTL processes the FTL entry refresh request in an asynchronous manner.

The first or second apparatus for accessing an FTL according to the second aspect of the present invention provides the third apparatus for accessing an FTL according to the second aspect of the present invention, wherein the FTL entry address stored in the FTL entry address storage means is also updated in response to the CPU interface receiving the FTL entry update request.

According to one of the first to third apparatuses for accessing an FTL of the second aspect of the present invention, there is provided the fourth apparatus for accessing an FTL of the second aspect of the present invention, wherein in response to receiving an FTL entry update request, after updating FTL entry data stored in the FTL entry data storage means, it is indicated through the CPU interface that the processing of the FTL entry update request is completed; and writing the updated FTL table entry data into the main memory through the main memory interface.

According to one of the first to fourth apparatuses for accessing an FTL of the second aspect of the present invention, there is provided a fifth apparatus for accessing an FTL according to the second aspect of the present invention, wherein in response to receiving an FTL entry flush request, it is further detected whether a specified FTL entry has been written to a main memory, and after writing the specified FTL entry to the main memory, it is indicated through a CPU interface that processing of the FTL entry flush request is completed.

According to one of the first to fifth apparatuses for accessing an FTL according to the second aspect of the present invention, there is provided a sixth apparatus for accessing an FTL according to the second aspect of the present invention, wherein after receiving an FTL entry flush request, before writing a specified FTL entry into a main memory, the CPU interface indicates that processing of the FTL entry flush request is completed.

According to one of the first to sixth means for accessing FTL of the second aspect of the present invention, there is provided the seventh means for accessing FTL of the second aspect of the present invention, wherein writing the specified FTL entry data to the main memory through the main memory interface at the specified FTL entry address further comprises: and unlocking the FTL table entry of the main memory specified address.

According to one of the first to seventh apparatuses for accessing an FTL of the second aspect of the present invention, there is provided an eighth apparatus for accessing an FTL of the second aspect of the present invention, wherein in response to a CPU interface receiving a preload request for an FTL entry of a specified address, the FTL entry is obtained from a main memory through the main memory interface, the preload request further specifying a first index indicating a storage location of the FTL entry of the specified address in an FTL entry data storage; and providing the FTL table entry to the CPU through the CPU interface in response to the CPU interface receiving a read request for the FTL table entry of the first index.

According to a third aspect of the present invention, there is provided a method for accessing an FTL according to the third aspect of the present invention, comprising: sending a preloading request for the FTL table entry of the specified address so as to load the specified FTL table entry into the storage position indicated by the first index of the FTL table entry storage component; and issuing a read request for the FTL entry of the first index to obtain the FTL entry of the first index from the FTL entry storage unit.

According to the first method for accessing an FTL of the third aspect of the present invention, there is provided a second method for accessing an FTL of the third aspect of the present invention, wherein the operation of issuing a preload request for an FTL entry of a specified address is performed in an asynchronous manner; and the operation of sending out the read request to the FTL table entry of the first index is executed in a synchronous mode.

There is provided a method of accessing an FTL according to the third aspect of the present invention, including: sending an update request to the FTL table entry of the first index to update the FTL table entry indicated by the first index in the FTL table entry storage unit; and issuing a write-through request to the FTL entry of the first index to write the FTL entry indicated by the first index in the FTL entry storage unit into the main memory.

According to one of the methods of the first to third accessing FTLs of the third aspect of the present invention, there is provided a method of the fourth accessing FTL according to the third aspect of the present invention, wherein: the operation of sending out the update request of the FTL table entry of the first index is executed in a synchronous mode; and the operation of sending the flash request to the FTL table entry of the specified address is executed in an asynchronous mode.

According to one of the first to fourth methods of accessing an FTL of the third aspect of the present invention, there is provided a method of accessing an FTL of the fifth aspect of the present invention, wherein: and the operation of sending the flash request to the FTL table entry of the first index is executed in a synchronous mode.

According to one of the first to fifth FTL accessing methods of the third aspect of the present invention, there is provided the sixth FTL accessing method according to the third aspect of the present invention, wherein the preloading request for the FTL entry of the specified address further indicates locking the FTL entry of the specified address.

According to one of the methods of the first to sixth access FTLs of the third aspect of the present invention, there is provided a method of the seventh access FTL according to the third aspect of the present invention, wherein: and the flash request for the FTL table entry of the first index also indicates to unlock the FTL table entry of the FTL table entry address indicated by the first index in the main memory.

According to one of the methods of the first to seventh access to the FTL of the third aspect of the present invention, there is provided a method of the eighth access to the FTL according to the third aspect of the present invention, wherein: after sending out a preloading request for the FTL table entry of the specified address, and before sending out a reading request for the FTL table entry of the first index, the method also executes the operation irrelevant to accessing the FTL table entry of the specified address.

According to one of the methods of the first to eighth accessing FTLs of the third aspect of the present invention, there is provided a method of the ninth accessing FTL according to the third aspect of the present invention, wherein: after sending out an update request to the FTL table item of the first index and before sending out a write-over request to the FTL table item of the first index, the method also executes operation irrelevant to accessing the FTL table item of the first index.

According to one of the methods of accessing to the FTL of the third aspect of the present invention, there is provided the method of accessing to the tenth FTL according to the third aspect of the present invention, wherein the operation unrelated to accessing to the FTL entry of the first index comprises an operation accessing to the second FTL entry.

According to one of the methods of the first to tenth accessing FTLs of the third aspect of the present invention, there is provided a method of the eleventh accessing FTL according to the third aspect of the present invention, further comprising: entries of the FTL entry storage unit having the first index are allocated.

According to one of the methods of the first to eleventh accessing to the FTL of the third aspect of the present invention, there is provided a method of the twelfth accessing to the FTL according to the third aspect of the present invention, further comprising: and issuing a write-over request to the FTL table entry storage unit so as to write all updated FTL table entries in the FTL table entry storage unit into the main memory.

According to one of the first to twelfth methods of accessing an FTL of the third aspect of the present invention, there is provided the thirteenth method of accessing an FTL of the third aspect of the present invention, further comprising writing the updated FTL entry in the FTL storage component into the main memory after issuing the update request for the FTL entry of the first index.

According to a fourth aspect of the present invention there is provided a computer program comprising computer program code which, when loaded into a computer system and executed thereon, causes the computer system to perform the FTL access method provided in accordance with the third aspect of the present invention.

According to a fifth aspect of the present invention, there is provided a program comprising program code which, when loaded into and executed on a storage device, causes the storage device to perform the FTL access method provided in accordance with the third aspect of the present invention.

Drawings

The invention, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of circuitry according to an embodiment of the invention;

FIG. 2 is a block diagram of FTL acceleration circuitry according to an embodiment of the present invention;

FIG. 3 is a flowchart of an FTL entry reading process according to an embodiment of the present invention;

FIG. 4A is a flow diagram of an FTL entry update process according to one embodiment of the present invention; and

fig. 4B is a flowchart of an FTL entry updating process according to another embodiment of the present invention.

Detailed Description

Circuit system

FIG. 1 is a block diagram of circuitry according to an embodiment of the invention. The CPU is coupled with a main memory such as a DRAM, constituting a circuit system. An FTL acceleration circuit is provided between the CPU and the main memory. The FTL acceleration circuit is coupled to the CPU. The CPU accesses the FTL acceleration circuit through a high-speed local interface. For example, the CPU accesses the FTL acceleration circuit in a register access manner. When the CPU accesses the FTL acceleration circuit, the FTL acceleration circuit provides the result to the CPU within one instruction execution cycle.

The FTL acceleration circuit is coupled to a main memory (e.g., DRAM) through a bus. The main memory stores FTL tables. The storage space of the main memory can be several GB, and the storage space occupied by the FTL table can be several GB. The FTL acceleration circuit can access the FTL tables stored in main memory using prior art means.

The CPU accesses the FTL table stored in the main memory through the FTL accelerating circuit. Alternatively, the CPU may also have direct access to main memory without utilizing FTL acceleration circuitry. Alternatively, the CPU accesses the FTL table stored in the main memory through the FTL acceleration circuit, and the CPU directly accesses the main memory to obtain contents other than the FTL table stored in the main memory.

Fig. 2 is a block diagram of FTL acceleration circuit according to an embodiment of the present invention. The FTL acceleration circuit includes an FTL entry storage unit. The FTL entry storage unit includes an FTL entry address storage unit and an FTL entry data storage unit, which are respectively used for storing an address of the FTL entry (e.g., a storage address of the FTL entry in the main memory) and data of the FTL entry corresponding to the address.

In the FTL acceleration circuit, a plurality of pairs of FTL entries may be stored. The FTL entry may be, for example, { FTL entry address, FTL entry data }. And, by the index, the CPU can explicitly access the FTL entry address storing means and/or the FTL entry data storing means of the FTL acceleration circuit.

In another example, the length of the FTL entry is also stored in association with the FTL entry in the FTL acceleration circuit. Therefore, the address of the FTL table entry indicates the initial address of the FTL table entry in the main memory, and the length of the FTL table entry indicates the size of the memory space occupied by the FTL table entry.

The FTL acceleration circuit further comprises a CPU interface and a main memory interface. The CPU accesses the FTL acceleration circuit through the CPU interface. The CPU interface is a low latency access interface that supports synchronous/asynchronous modes of operation. In the synchronous operation mode, the CPU sends an access request to the FTL accelerator circuit through the CPU interface of the FTL accelerator circuit, the FTL accelerator circuit indicates to the CPU that the processing of the access request is completed after obtaining the access result, and provides the access result to the CPU, and the CPU continues to execute subsequent operations (e.g., execute the next instruction) after obtaining the access result provided by the FTL accelerator circuit. In the asynchronous operation mode, the CPU sends an access request to the FTL accelerating circuit through the CPU interface, and the FTL accelerating circuit indicates the completion of the processing of the access request to the CPU without waiting for a return result.

The FTL acceleration circuit accesses a main memory (e.g., DDR memory) through a main memory interface. The main memory interface is used to access main memory and may be any known or yet to be developed memory access interface.

The CPU interface of the FTL acceleration circuit provides multiple access modes.

(1) FTL entry preloading (FTL _ Prefetch (index, addr))

The CPU sends an FTL table entry preloading request (FTL _ Prefetch) to the FTL acceleration circuit through the CPU interface to request the FTL acceleration circuit to load an FTL table entry A of a specified main memory address (e.g., an address indicated by addr) from the main memory, store the FTL table entry address of the FTL table entry A in an address storage unit of the FTL acceleration circuit, store FTL table entry data of the table entry A in an FTL table entry data storage unit of the FTL acceleration circuit, and store the address of the table entry A in the FTL table entry address storage unit. An Index (Index) is also included in the preload request sent by the CPU to the FTL acceleration circuit, and indicates where the FTL entry is loaded to the FTL entry storage unit. Through the Index (Index), the CPU may also obtain the entry address and/or entry data of entry a from the FTL acceleration circuit. Since the time to access main memory is much longer than the CPU instruction execution time, to avoid the CPU waiting for a long time for the execution result of the FTL acceleration circuit, it is preferable to process the access request using the asynchronous operation mode.

Optionally, a plurality of addresses are included in the request sent by the CPU to the FTL acceleration circuit. The FTL acceleration circuit splices multiple addresses into an address for the main memory. For example, the plurality of addresses are respectively a high-order address and a low-order address, and the plurality of addresses may also be respectively a page address and an offset address within a page.

After receiving the preload request, the FTL acceleration circuit reads the data with the specified length from the main memory by using the main memory address to obtain the FTL entry a, and stores the entry data of the entry a in the entry data storage component indexed by the Index of the FTL acceleration circuit. The FTL acceleration circuit also stores the main memory address of table entry a in an entry address storage unit of the FTL acceleration circuit indexed by Index.

Optionally, when the FTL acceleration circuit reads FTL entry data from the main memory, it also locks the FTL entry data in the main memory. And in the FTL table entry preloading request sent by the CPU, whether to lock FTL table entry data in the main memory is also indicated.

Optionally, the logic address of the FTL entry a to be loaded is indicated in the FTL entry preloading request. The FTL acceleration circuit determines a main memory address for storing the FTL table entry A in the main memory according to the logical address. For example, the main memory address storing FTL table entry a is determined by FTL table base address and logical address as offset value. Or, using the logical address as an index to search the main memory address storing the FTL entry a.

Alternatively, if the index is indicated in the FTL entry preloading request, and the storage unit indicated by the index in the FTL entry storage unit of the FTL acceleration circuit has been allocated (the FTL entry is already stored or the FTL entry to be stored in the storage unit indicated by the index is already loaded to the main memory), the content of the storage unit indicated by the index is also cleared or marked invalid, and the FTL entry is retrieved from the main memory.

(2) FTL entry Read (FTL _ Read _ item (index))

And the CPU sends an FTL table entry reading request to the FTL accelerating circuit through the CPU interface. In the FTL entry read request, an index (index) of the FTL entry to be read in the FTL entry storage unit is specified. The CPU requests the FTL acceleration circuit to provide the corresponding FTL entry a by indexing Index. The FTL acceleration circuit obtains the table entry data from the FTL table entry data storage unit according to the Index, and provides the table entry data to the CPU. The time required for the FTL acceleration circuit to provide the table entry data to the CPU is close to the CPU instruction execution time, and thus the access request is preferably processed using the synchronous operation mode. If the CPU requests the FTL acceleration circuit to provide the corresponding entry data of the FTL entry a through the Index, the FTL entry storage component of the FTL acceleration circuit does not have the requested entry data, and the FTL acceleration circuit checks whether a request for obtaining the FTL entry a of the specified main memory address has been issued to the main memory. If the request is sent, the main memory is waited to return the FTL table entry A, the FTL table entry A is stored in the FTL table entry storage unit, and the table entry A is provided for the CPU. If the request has not been issued, the CPU is informed that the requested FTL entry A does not exist in the FTL acceleration unit.

(3) FTL entry address Read (FTL _ Read _ addr (index))

And the CPU sends an FTL table entry address reading request to the FTL accelerating circuit through the CPU interface. The CPU requests the FTL acceleration circuit to provide the entry address of the corresponding FTL entry a through an Index (Index). The FTL acceleration circuit obtains the table entry data from the internal FTL table entry address storage unit according to the Index, and provides the table entry data to the CPU. The time required for the FTL acceleration circuit to provide the entry address to the CPU is close to the CPU instruction execution time, and thus the access request is preferably processed using the synchronous mode of operation. And if the CPU requests the FTL accelerating circuit to provide the corresponding table entry address of the FTL table entry A through the Index, and the FTL table entry address storage unit of the FTL accelerating circuit does not have the requested table entry address, informing the CPU that the requested FTL table entry A does not exist in the FTL accelerating unit.

A read operation of the FTL entry address stored in the FTL acceleration circuit is not necessary. In general, when the CPU updates the FTL entry, only the entry data is updated without updating the FTL entry address, so that the CPU does not need to update the FTL entry address stored in the FTL acceleration circuit.

(4) FTL entry update (FTL _ Write _ item (index, item))

And the CPU sends an FTL table item updating request to the FTL accelerating circuit through the CPU interface. The CPU requests the FTL acceleration circuit to update the FTL entry data indexed as Index to new entry data (item) specified by the CPU. The FTL acceleration circuit performs an update of the entry data in the FTL entry data storage unit. The time required for the FTL acceleration circuit to update the table entry data is close to the CPU instruction execution time, and thus the access request is preferably processed using the synchronous operation mode. Optionally, if the CPU requests the FTL acceleration circuit to update the corresponding FTL entry data through the Index, and there is no entry data with the Index in the FTL entry data storage unit of the FTL acceleration circuit, the new entry data is stored in the FTL entry data storage unit. And optionally, informing the CPU that there is no entry data with Index in the FTL entry data storage means of the FTL acceleration circuit.

Optionally, in the FTL entry update request sent by the CPU, it is further indicated whether to unlock the FTL entry data in the main memory. And when the FTL accelerating circuit updates the FTL table entry data to the main memory, unlocking the FTL table entry data in the main memory according to the indication. Therefore, when the CPU needs to continuously update the FTL table entry data, the CPU can unlock the FTL table entry data in the main memory only when the FTL table entry data is updated for the last time.

(5) FTL entry address update (FTL _ Write _ addr (index, addr))

And the CPU sends an FTL table entry address updating request to the FTL accelerating circuit through the CPU interface. The CPU requests the FTL acceleration circuit to update the FTL entry address indexed as Index in the FTL entry address storage unit to the new entry address (addr) specified by the CPU. The FTL acceleration circuit performs an update of the entry address in the FTL entry address storage unit. The time required for the FTL acceleration circuit to update the entry address is close to the CPU instruction execution time, and thus the access request is preferably processed using the synchronous operation mode. Optionally, if the CPU requests the FTL acceleration circuit to update the corresponding FTL entry address through the Index, and there is no entry address with the Index in the FTL entry address storage unit of the FTL acceleration circuit, the new entry address is stored in the FTL entry address storage unit. And optionally, the FTL acceleration circuit informs the CPU that there is no entry address indexed as Index in the FTL entry address storage unit of the FTL acceleration circuit.

An update operation to the FTL entry address stored in the FTL acceleration circuit is not necessary.

(6) FTL table entry flash (FTL _ Flush _ entry (index))

And the CPU sends an FTL table entry flashing request to the FTL accelerating circuit through the CPU interface. The CPU requests the FTL acceleration circuit to write FTL entry a indexed by Index into the main memory. The FTL acceleration circuit obtains the main memory address of FTL table entry a from the FTL table entry address storage unit according to the Index, obtains FTL table entry data (table entry a) from the FTL table entry data storage unit, and writes the table entry a into the main memory according to the main memory address. Since the time to access main memory is much longer than the CPU instruction execution time, to avoid the CPU waiting for a long time for the execution result of the FTL acceleration circuit, it is preferable to process the access request using the asynchronous operation mode.

Optionally, no parameter is provided in the FTL entry flush request, and the FTL acceleration circuit writes all FTL entries in the FTL entry storage unit to the main memory in response to the FTL entry flush request without parameter. And writing the FTL table entry data stored in the FTL table entry data storage unit into the main memory according to the corresponding FTL table entry address stored in the FTL table entry address storage unit.

Optionally, in the FTL entry flashing request sent by the CPU, it is further indicated whether to unlock the FTL entry data in the main memory.

(7) FTL entry write-through (FTL _ WriteThrough _ item (index, item))

And the CPU sends an FTL table entry write-through request to the FTL accelerating circuit through the CPU interface. And the CPU requests the FTL accelerating circuit to update the FTL table entry data with the Index of the FTL table entry data storage unit as Index into new table entry data specified by the CPU, and writes the new table entry data into the main memory. The FTL acceleration circuit performs an update of the entry data in the FTL entry data storage unit. The FTL acceleration circuit also actively initiates a main memory update request, obtains a main memory address from the FTL entry address storage unit according to the index (index), and writes FTL entry data indicated by the index (index) to the main memory according to the main memory address without CPU intervention.

Since the operation of writing data into the main memory takes a lot of time, preferably, the access request is processed in an asynchronous operation mode, and the FTL acceleration circuit writes FTL table entry data into the FTL table entry data storage unit and then indicates to the CPU that the FTL table entry write-through request processing is completed.

Operation process

(1) Reading FTL table entries

Fig. 3 is a flowchart of an FTL entry reading process according to an embodiment of the present invention. When a CPU wishes to use FTL table entries, the FTL table entries (such as table entry A) are obtained from a main memory according to the embodiment of the invention.

For example, the CPU receives a request to read the storage device and needs to query the FTL to obtain the physical address to be accessed by the read request. By reading the logical address of the request, the CPU determines that FTL entry A at main memory address Addr is to be loaded. The CPU requests the FTL acceleration circuit to preload the FTL entry a through the FTL acceleration circuit local interface (e.g., FTL _ Prefetch (index, addr)) (310). In order to request the FTL acceleration circuit to preload the FTL entry a, the CPU further informs the FTL acceleration circuit of an index (index) for indexing the FTL entry a, so that after the FTL acceleration circuit loads the FTL entry a, the CPU can quickly obtain the FTL entry a from the FTL acceleration circuit through the index. The FTL acceleration circuit stores the acquired FTL entry a in the FTL entry data storage unit and the FTL entry address storage unit addressed by the index (index).

The CPU requests the FTL acceleration circuit to preload the operation of FTL table entry A, and the operation is executed in an asynchronous mode. After the CPU issues the request, it continues to perform other processing without waiting for the FTL acceleration circuit to return the execution result (320). Thus, the processing capability of the CPU can be effectively utilized during the FTL acceleration circuit reading FTL table entry A from the main memory (e.g., DRAM).

The FTL acceleration circuit reads data from the main memory as FTL table entry a using address addr in response to a request to preload FTL table entry a issued by the CPU (315). The FTL accelerating circuit responds to a request for preloading FTL table entries A sent by the CPU in an asynchronous mode, and indicates the completion of the processing of the preloading request to the CPU before obtaining the FTL table entries A from the main memory after receiving the FTL table entry A preloading request.

In one example, the CPU also informs the FTL acceleration circuitry of the length of FTL table entry A requested, so that the FTL acceleration circuitry reads the specified length of data from main memory. Optionally, the CPU further instructs the FTL acceleration circuit to lock the requested FTL entry a, and when the FTL acceleration circuit obtains the FTL entry a from the main memory, it first requests to lock the FTL entry a, and after the FTL entry a is successfully locked, it reads the FTL entry a from the main memory.

After a period of time, the CPU estimates that the FTL acceleration circuitry has retrieved FTL entry A from main memory. The CPU reads (e.g. FTL _ Read _ item) FTL table entry A indexed as index from FTL acceleration circuit through FTL acceleration circuit CPU interface (330). In another example, the FTL acceleration circuit sends a message or interrupt to the CPU to indicate that the CPU has retrieved FTL entries from main memory.

In the example of the following figure, when the CPU reads the FTL entry a indexed by index from the FTL acceleration circuit, the FTL acceleration circuit has obtained the FTL entry a from the main memory and stored in the FTL entry data storage section of the FTL acceleration circuit, the FTL acceleration circuit also stores the main memory address addr of the entry a in the FTL entry address storage section, and the FTL entry a stored in the FTL acceleration circuit and the address of the entry a can be accessed by the index.

In response to the CPU reading the FTL entry a indexed by index from the FTL acceleration circuit, the FTL acceleration circuit acquires the entry a from the FTL entry data storage unit and provides it to the CPU (335). The operation of reading the FTL entry a with index from the FTL acceleration circuit by the CPU is performed in a synchronous manner. After the CPU receives the entry a provided by the FTL acceleration circuit, it continues to perform other operations (e.g., an operation using the FTL entry a).

In another example, when the CPU reads FTL entry a with index from the FTL acceleration circuit, the FTL acceleration circuit receives a request to preload FTL entry a from the main memory, but has not obtained FTL entry a from the main memory. Since the operation of reading the FTL entry a indexed by index from the FTL acceleration circuit is performed in a synchronous manner, the FTL acceleration circuit waits for obtaining the FTL entry a from the main memory, stores the entry a in the FTL entry data storage section of the FTL acceleration circuit, and provides the FTL entry a to the CPU.

In yet another example, when the CPU reads FTL entry a with index from the FTL acceleration circuit, the FTL acceleration circuit has not received a request to preload FTL entry a from main memory. The FTL accelerating circuit checks whether a request for preloading an FTL table entry A of a specified main memory address is sent to a main memory; if the request has not been issued, the CPU is informed that the requested FTL entry A does not exist in the FTL acceleration unit. Optionally, the FTL acceleration circuit checks whether a request to preload FTL table entry a of the specified main memory address has been issued to the main memory; if the request is not sent, the FTL accelerating circuit sends a request for preloading the FTL table entry A of the specified main memory address to the main memory, and stores the table entry A in an FTL table entry data storage component of the FTL accelerating circuit after waiting for obtaining the FTL table entry A from the main memory, and provides the FTL table entry A for the CPU.

In another embodiment, to take full advantage of the pre-load capability of the FTL acceleration circuit, the CPU issues a plurality of pre-load requests to the FTL acceleration circuit to request the FTL acceleration circuit to pre-load a plurality (e.g., m being a positive integer) of FTL entries. After issuing m preload requests, FTL entry a initially requesting preload has been retrieved from main memory by the FTL acceleration circuit so that immediately after the CPU issues an FTL entry read request, the FTL acceleration circuit can immediately provide the read FTL entry a to the CPU.

(2) Updating FTL table item (FIG. 4A)

When some IO requests (e.g., write requests) are processed, a new corresponding physical address needs to be allocated for the logical address, and the FTL entry (e.g., entry a) needs to be updated. Fig. 4A shows a process of updating FTL entry according to the embodiment of the present invention.

To update the FTL entry a, the CPU obtains the FTL entry a from the main memory by the embodiment according to the present invention, and stores it in the FTL entry data storage component of the FTL acceleration circuit.

Next, the CPU allocates a new physical address to FTL entry a. To write the FTL entry a with the updated physical address into the main memory, the CPU writes the FTL entry a (containing the newly allocated physical address) with index into the FTL acceleration circuit through the FTL acceleration circuit CPU interface (410). In response to the CPU writing (FTL _ Write _ item (index, item)) the FTL entry a indexed by index to the FTL acceleration circuit, the FTL acceleration circuit updates the entry data indexed by index in the FTL entry data storage unit (415). The operation of writing the FTL entry a with index to the FTL acceleration circuit by the CPU is executed in a synchronous manner.

The CPU may then perform other processing (420).

In one example, the CPU also requests, through the FTL acceleration circuit CPU interface, the FTL acceleration circuit to Flush the FTL entry (index) indexed as index to the main memory (FTL _ Flush _ entry). In response to a request of the CPU for the FTL acceleration circuit to flush the FTL entry indexed by the index to the main memory, the FTL acceleration circuit acquires the main memory address of the entry a from the FTL entry address storage unit, acquires the content of the entry a from the FTL entry data storage unit, and issues a write request to the main memory through the main memory interface, based on the index of the entry a. The operation that the CPU requests the FTL accelerating circuit to flash the FTL table entry with the index to the main memory can be executed in an asynchronous mode, so that the CPU can execute other processing in the process that the FTL accelerating circuit flushes the FTL table entry to the main memory. The CPU requests the FTL accelerating circuit to flush the FTL table entry with the index to the main memory, or can execute the operation in a synchronous mode, and the FTL accelerating circuit indicates the completion of the FTL table entry flushing request to the CPU after flushing the FTL table entry to the main memory. Optionally, the FTL acceleration circuit combines multiple FTL entries and writes multiple FTL entries to the main memory in one main memory update request.

In another example, the CPU also requests the FTL acceleration circuit to Flush all "dirty" FTL entries to main memory (FTL _ Flush _ entry) through the FTL acceleration circuit CPU interface. An FTL entry that is "dirty" refers to an FTL entry that has been loaded into the FTL entry storage unit, has been updated, but has not been flushed to main memory.

Optionally, the FTL acceleration circuitry also maintains status for each entry of the FTL entry storage means, including an empty status indicating that the FTL entry is not loaded, a "preload" status that the FTL entry loading request has been received but the FTL entry has not been received, a valid status that the FTL entry has been loaded and the FTL entry has not been updated, a "dirty" status that the FTL entry has been updated, etc.

Optionally, the CPU further instructs the FTL acceleration circuit to unlock the updated FTL entry a. And when the FTL accelerating circuit updates the FTL table entry A to the main memory, the FTL table entry A in the main memory is unlocked.

In another embodiment, the CPU generates a new FTL entry instead of fetching the FTL entry from main memory. The CPU issues an FTL entry update (FTL _ Write _ entry (index, item)) request to the FTL acceleration circuit through a CPU interface of the FTL acceleration circuit to Write the generated FTL entry into the FTL entry storage unit indicated by the FTL acceleration circuit routing index.

Fig. 4B shows a process for updating FTL entry according to another embodiment of the present invention.

To update the FTL entry a, the CPU obtains the FTL entry a from the main memory according to the embodiment of the present invention, and allocates a new physical address to the FTL entry a. In order to write the FTL entry a with the updated physical address into the main memory, the CPU issues an FTL entry a (including the newly allocated physical address) write-through request (FTL _ WriteThrough _ item) with index to the FTL acceleration circuit through the FTL acceleration circuit CPU interface. In response to the CPU issuing an FTL entry a write-through request to the FTL acceleration circuit, the FTL acceleration circuit updates entry data indexed to index in the FTL entry data storage unit. The FTL acceleration circuit also obtains the main memory address from the FTL entry address storage unit according to the index, and writes the new entry data into the main memory through the main memory interface according to the main memory address without intervention of the CPU. And the CPU writes the FTL table entry A with index to the FTL accelerating circuit in an asynchronous mode. Enabling the CPU to perform other processing (420) during the FTL acceleration device updating the FTL entry storage means and writing the new entry data to the main memory.

Optionally, the FTL acceleration circuit combines multiple FTL entries and writes multiple FTL entries to the main memory in one main memory update request.

Optionally, after issuing the FTL entry write-through request, the CPU further requests, through the FTL acceleration circuit CPU interface, the FTL acceleration circuit to write the FTL entry indexed by index to the main memory (FTL _ Flush _ entry (index)). After receiving the FTL entry refresh request, the FTL acceleration circuit checks the FTL entry with index in the FTL entry storage unit, and if the FTL entry has been written into the main memory, directly indicates to the CPU that the FTL entry refresh request is completed; and if the FTL table entry is not written into the main memory, indicating the completion of the FTL table entry flashing request to the CPU after waiting for writing the FTL table entry into the main memory.

It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions may be loaded onto a general purpose computer, special purpose computer, or other programmable data control apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data control apparatus create means for implementing the functions specified in the flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data control apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the function specified in the flowchart block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data control apparatus to cause a series of operational operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart block or blocks.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of operations for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Although the present invention has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the invention, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the invention.

Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims (10)

1. A method of accessing an FTL, comprising:

sending a preloading request for the FTL table entry of the specified address so as to load the specified FTL table entry into the storage position indicated by the first index of the FTL table entry storage component;

and sending a read request to the FTL table entry of the first index so as to acquire the FTL table entry of the first index from the FTL table entry storage unit.

2. The method of claim 1, wherein the operation of issuing a preload request for FTL entry of specified address is performed in an asynchronous manner; and the operation of sending out the read request to the FTL table entry of the first index is executed in a synchronous mode.

3. The method of claim 1 or 2, wherein the method further comprises:

sending an update request to the FTL table entry of the first index to update the FTL table entry indicated by the first index in the FTL table entry storage unit;

and issuing a write-over request to the FTL table entry of the first index so as to write the FTL table entry indicated by the first index in the FTL table entry storage unit into the main memory.

4. The method of claim 3, wherein the operation of issuing a flush request to the FTL entry for the first index is performed in a synchronous manner.

5. The method of any one of claims 1-4, further comprising:

after sending an update request to an FTL table item of a first index and before sending a write-over request to the FTL table item of the first index, executing operation irrelevant to accessing the FTL table item of the first index; and/or the presence of a gas in the gas,

after a preloading request for an FTL table item of a specified address is sent out, and before a reading request for the FTL table item of a first index is sent out, operation irrelevant to accessing the FTL table item of the specified address is executed.

6. The method of claim 5, wherein the operation unrelated to accessing the FTL entry of the first index comprises an operation accessing a second FTL entry.

7. The method of claim 5, wherein the preload request for the FTL entry of specified address further indicates locking the FTL entry of specified address.

8. The method of claim 5 or 7, wherein the flush request to the FTL entry of the first index further indicates unlocking the FTL entry of the FTL entry address indicated by the first index in main memory.

9. An apparatus for accessing an FTL, which is applied to perform the method according to any one of claims 1 to 8, and which comprises an FTL entry address storage unit, an FTL entry data storage unit, a CPU interface, and a main memory interface, wherein the FTL entry address storage unit stores a plurality of FTL entry addresses;

the FTL entry data storage component stores a plurality of FTL entry data;

accessing the FTL table entry address and the FTL table entry data associated therewith in the FTL table entry address storage component and the FTL table entry data storage component, respectively, by the same index, where the FTL table entry address is a storage address of the FTL table entry data associated therewith in the main memory;

in response to the CPU interface receiving an update request for the FTL table entry of the first index, updating FTL table entry data indicated by the first index in the FTL table entry data storage component; and in response to the CPU interface receiving a write-over request for the FTL table entry of the first index, writing the FTL table entry data specified by the first index into the main memory through the main memory interface according to the FTL table entry address specified by the first index.

10. A program comprising program code which, when loaded into a computer system and executed thereon, causes the computer system to perform the FTL access method of any of claims 1-8.

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