CN112018134A

CN112018134A - Image sensor and forming method thereof

Info

Publication number: CN112018134A
Application number: CN201911271896.6A
Authority: CN
Inventors: 林政贤; 蔡纾婷; 许慈轩
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-05-29
Filing date: 2019-12-12
Publication date: 2020-12-01

Abstract

Various embodiments of the present disclosure relate to an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric structure is disposed on the first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate between the photodetector and the storage node, wherein the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate opposite the first side, and wherein the first isolation structure is spaced apart from the first side by a second distance that is less than the first distance.

Description

Image sensor and forming method thereof

Technical Field

The disclosure relates to an image sensor and a forming method thereof.

Background

Many modern electronic devices, such as smartphones, digital cameras, biomedical imaging devices, automated imaging devices, and the like, include image sensors. The image sensor includes one or more photodetectors (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident radiation and output electrical signals corresponding to the incident radiation. Some types of image sensors include charge-coupled devices (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared to CCD image sensors, CMOS image sensors are favored because of their advantages such as low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and backside illuminated (BSI) image sensors.

Disclosure of Invention

In some embodiments, the present disclosure provides an image sensor. The image sensor includes: a photodetector disposed in the semiconductor substrate; an interlayer dielectric (ILD) structure disposed on a first side of a semiconductor substrate; a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance; a first isolation structure is disposed in the semiconductor substrate between the photodetector and the storage node, wherein the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate opposite the first side, and wherein the first isolation structure is spaced apart from the first side by a second distance that is less than the first distance.

In some embodiments, the present disclosure provides an image sensor. The image sensor includes: a photodetector disposed in the semiconductor substrate, wherein the photodetector is spaced apart from the first side of the semiconductor substrate by a first distance; an interlayer dielectric (ILD) structure disposed on a first side of a semiconductor substrate; a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a second distance greater than the first distance; and a first vertical transfer gate disposed on the first side and configured to selectively form a first conductive channel between the photodetector and the storage node, wherein a first portion of the first vertical transfer gate extends from the first side into the semiconductor substrate by a third distance, and wherein the third distance is greater than the first distance and less than the second distance.

In some embodiments, the present disclosure provides a method for forming an image sensor, comprising: forming a photodetector in a semiconductor substrate; forming a storage node in the semiconductor substrate and spaced apart from the photodetector; forming a first vertical transfer gate and a second vertical transfer gate on a first side of a semiconductor substrate, wherein a portion of the first vertical transfer gate and a portion of the second vertical transfer gate extend into the semiconductor substrate from the first side; forming an interlayer dielectric (ILD) structure on the first side and over the first and second vertical transfer gates; forming an isolation structure in the semiconductor substrate, wherein the isolation structure extends into the first semiconductor substrate from a second side of the semiconductor substrate opposite the first side; a reflective structure is formed on the second side of the semiconductor substrate, wherein at least a portion of the reflective structure is disposed between opposite sides of the storage node.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of some embodiments of a backside illuminated global shutter (BSIGS) image sensor.

Fig. 2 illustrates a cross-sectional view of some other embodiments of the BSIGS image sensor of fig. 1.

Fig. 3 illustrates a cross-sectional view of some other embodiments of the BSIGS image sensor of fig. 1.

Fig. 4 illustrates a cross-sectional view of some other embodiments of the BSIGS image sensor of fig. 1.

Fig. 5-20 illustrate a series of cross-sectional views for forming some embodiments of the BSIGS image sensor of fig. 4.

Fig. 21 illustrates a flow diagram of some embodiments of a method for forming a BSIGS image sensor.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below … (beneath)", "below … (below)", "lower (lower)", "above … (above)", "upper (upper)" and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Some cmos image sensors have an array of pixel sensors. Pixel sensors record incident radiation using a photodetector, and digitally readout of the record is facilitated by a plurality of pixel devices, such as transfer gates, reset transistors, source follower transistors, and/or row-select transistors. Some CIS are Global Shutter (GS) CIS. The GSCIS is configured to start and stop exposure in each pixel sensor at the same time. For example, the GSCIS may start exposing the optical image to each pixel sensor at the same first time, and then the GSCIS may stop exposing the optical image to each pixel at the same second time. Some GSCIS are front-side illuminated (FSI) GSCIS. The FSIGSCIS is configured to record incident radiation that passes through the front side of the semiconductor substrate. For example, an interlayer dielectric (ILD) structure may be disposed on the front side of the semiconductor substrate, and the FSIGSCIS is configured to record incident radiation through the ILD structure and the front side of the semiconductor substrate.

One challenge of the FSIGSCIS described above is to improve the Quantum Efficiency (QE) and/or Angular Response (AR) of the FSIGSCIS while maintaining high Shutter Efficiency (SE). Because the FSIGSCIS is configured to record incident radiation through the front side of the semiconductor substrate, the FSIGSCIS has a relatively long optical path, adversely affecting the QE and/or AR of the FSIGSCIS. Furthermore, because the FSIGSCIS is configured to record incident radiation through the front side of the semiconductor substrate, interconnect structures disposed in the ILD structure may reflect some of the incident radiation, thereby adversely affecting the QE and/or AR of the FSIGSCIS. While the interconnect structure may adversely affect the QE and/or AR of the FSIGSCIS, the interconnect structure may protect the storage nodes of the FSIGSCIS from most incident radiation, thereby beneficially affecting the SE.

Various embodiments of the present disclosure relate to a backside illuminated global shutter (BSIGS) image sensor. The BSIGS image sensor is configured to record incident radiation that passes through the back side of the semiconductor substrate. The BSIGS image sensor includes a photodetector disposed in a semiconductor substrate. The storage node is disposed in the semiconductor substrate and spaced apart from the photodetector. The interconnect structure is disposed on the front side of the semiconductor substrate. The reflective structure is disposed on a backside of the semiconductor substrate opposite the front side. The reflective structure is disposed such that the reflective structure at least partially protects the storage node from incident radiation passing through the backside of the semiconductor substrate.

Because the BSIGS image sensor is configured to record incident radiation through the backside of the semiconductor substrate, the BSIGS image sensor may have a better QE and/or AR when compared to the FSIGSCIS because the BSIGS image sensor has a shorter optical path than the FSIGSCIS. Furthermore, because the BSIGS image sensor is configured to record incident radiation through the backside of the semiconductor substrate, the BSIGS image sensor may have a better QE and/or AR due to a reduction (or elimination) of incident radiation reflected by the interconnect structure when compared to FSIGSCIS. Furthermore, the BSIGS image sensor may have a high SE because the reflective structure at least partially protects the storage node from incident radiation that passes through the backside of the semiconductor substrate. Accordingly, the BSIGS image sensor may have improved QE and/or AR over FSIGSCIS while maintaining a high SE.

Fig. 1 illustrates a cross-sectional view of some embodiments of a backside illuminated global shutter (BSIGS) image sensor 100.

As shown in fig. 1, the BSIGS image sensor 100 includes a first semiconductor substrate 102. The first semiconductor substrate 102 has a front side 102f and a back side 102b opposite the front side 102 f. The first semiconductor substrate 102 may comprise any type of semiconductor body (e.g., a single crystal silicon/CMOS block, silicon germanium (SiGe), Silicon On Insulator (SOI), etc.). The BSIGS image sensor 100 is configured to record incident radiation (e.g., photons) that pass through the backside 102b of the first semiconductor substrate 102.

A photodetector 104, such as a photodiode, is disposed in the first semiconductor substrate 102. The photodetector 104 comprises a portion of a first semiconductor substrate 102 having a first doping type (e.g., n-type/p-type). In some embodiments, the portion of the first semiconductor substrate 102 adjacent to the photodetector 104 may have a second doping type opposite the first doping type (e.g., p-type/n-type), or may be intrinsic. The photodetector 104 is configured to absorb incident radiation (e.g., light) and generate an electrical signal corresponding to the incident radiation.

The storage node 106 is disposed in the first semiconductor substrate 102 and spaced apart from the photodetector 104. The storage node 106 is a region of the first semiconductor substrate 102 having a first doping type. Storage node 106 is configured to store charge transferred from photodetector 104 to storage node 106.

A floating diffusion node 108 is disposed in the first semiconductor substrate 102 and is laterally spaced apart from the photodetector 104 and the storage node 106. The floating diffusion node 108 is a region of the first semiconductor substrate 102 having a first doping type. A first doped region 110 is disposed in the first semiconductor substrate 102 and spaced apart from the floating diffusion node 108. The first doped region 110 is a region of the first semiconductor substrate having a first doping type. In some embodiments, the first doped region 110 is a source/drain region for an anti-blooming (AB) gate. The second doped region 112 is disposed in the first semiconductor substrate 102 and is spaced apart from the first doped region 110 and the floating diffusion node 108. The second doped region 112 is a region of the first semiconductor substrate having the first doping type. In some embodiments, the second doped region 112 is a source/drain region of a reset transistor. In still other embodiments, a first isolation structure 114, such as a Shallow Trench Isolation (STI) structure, is disposed in the first semiconductor substrate 102.

A plurality of gates 116 are disposed on the front side 102f of the first semiconductor substrate 102. For example, the first gate 116a, the second gate 116b, the first vertical transfer gate 116c, and the second vertical transfer gate 116d may be disposed on the front side 102f of the first semiconductor substrate 102. The first vertical transfer gate 116c is configured to selectively form a first conductive channel between the photodetector 104 and the storage node 106 such that charge accumulated in the photodetector 104 (e.g., via absorption of incident radiation) can be transferred to the storage node 106. The second vertical transfer gate 116d is configured to selectively form a second conductive channel between the storage node 106 and the floating diffusion node 108 such that charge stored in the storage node 106 can be transferred to the floating diffusion node 108. In some embodiments, the first gate 116a may be an AB gate and the second gate 116b may be a reset gate.

First and second

vertical transfer gates

116c and 116d extend from the front side 102f into the first semiconductor substrate 102. For example, a first portion of the first vertical transfer gate 116c is disposed over the front side 102f and a second portion of the first vertical transfer gate 116c extends from the front side 102f into the first semiconductor substrate 102. The plurality of gates 116 each include a gate dielectric layer 118 and include a gate electrode 120 disposed on the gate dielectric layer 118, respectively. For example, the first gate 116a includes a first gate dielectric layer 118a and a first gate electrode 120a disposed on the first gate dielectric layer 118a, the second gate 116b includes a second gate dielectric layer 118b and a second gate electrode 120b disposed on the second gate dielectric layer 118b, the first vertical transfer gate 116c includes a third gate dielectric layer 118c and a third gate electrode 120c disposed on the third gate dielectric layer 118c, and the second vertical transfer gate 116d includes a fourth gate dielectric layer 118d and a fourth gate electrode 120d disposed on the fourth gate dielectric layer 118 d.

A first interlayer dielectric (ILD) structure 122 is disposed over the front side 102f of the first semiconductor substrate 102. A first interconnect structure 124, such as a copper interconnect, is disposed in the first ILD structure 122. The first interconnect structure 124 includes a plurality of conductive contact structures 124a (e.g., metal contacts), a plurality of vias 124b (e.g., metal vias), and a plurality of conductive lines 124c (e.g., metal lines). In some embodiments, the first ILD structure 122 comprises one or more stacked ILD layers that may comprise a low-k dielectric (e.g., a dielectric material having a dielectric constant of less than about 3.9), an oxide (e.g., silicon dioxide (SiO), respectively₂) ) or the like. In other embodiments, the first interconnect structure 124 may comprise, for example, copper (Cu), aluminum (Al), tungsten (W), gold (Au), some other conductive material, or a combination thereof. In still other embodiments, the conductive contact structure 124a may comprise a first conductive material (e.g., W), and the via 124b and the conductive line 124c may comprise a second conductive material (e.g., copper) different from the first conductive material.

A second isolation structure 126, such as a back-side deep trench isolation (BDTI) structure, is disposed in the first semiconductor substrate 102. The second isolation structure 126 is more opaque than the first semiconductor substrate 102. The second isolation structure 126 extends from the backside 102b of the first semiconductor substrate 102 and along the storage node 106 into the first semiconductor substrate 102. The second isolation structure 126a as a first portion extends into the first semiconductor substrate 102 between the storage node 106 and the photodetector 104. The second isolation structure 126b as the second portion extends into the first semiconductor substrate 102 on generally opposite sides of the storage node 106 as the second isolation structure 126a as the first portion. The second isolation structure 126a as the first portion may be referred to as a third isolation structure, and the second isolation structure 126b as the second portion may be referred to as a fourth isolation structure. Because the second isolation structure 126 extends into the first semiconductor substrate 102 and along the storage node 106, the second isolation structure 126 may at least partially protect the storage node 106 from incident radiation.

In some embodiments, the first and second

vertical transfer gates

116c and 116d are disposed at least partially between the second isolation structure 126a (a first portion of the second isolation structure 126) and the second isolation structure 126b (a second portion of the second isolation structure 126). Because the first vertical transfer gate 116c extends into the first semiconductor substrate 102, and because the first vertical transfer gate 116c is disposed at least partially between the second isolation structure 126a (the first portion of the second isolation structure 126) and the second isolation structure 126b (the second portion of the second isolation structure 126), the first vertical transfer gate 116c may improve charge transfer between the photodetector 104 and the storage node 106. Because the second vertical transfer gate 116d extends into the first semiconductor substrate 102, and because the second vertical transfer gate 116d is at least partially disposed between the second isolation structure 126a (the first portion of the second isolation structure 126) and the second isolation structure 126b (the second portion of the second isolation structure 126), the second vertical transfer gate 116d may improve charge transfer between the storage node 106 and the floating diffusion node 108. In addition, because the first and second

vertical transfer gates

116c and 116d are at least partially disposed between the second isolation structure 126a (the first portion of the second isolation structure 126) and the second isolation structure 126b (the second portion of the second isolation structure 126), the first and/or second

vertical transfer gates

116c and 116d may at least partially protect the storage node 106 from incident radiation.

In some embodiments, the second isolation structure 126 is a continuous structure. In other embodiments, the second isolation structure 126 may include discrete portions (discrete ports). For example, the second isolation structure 126a (a first portion of the second isolation structure 126) may be discrete from the second isolation structure 126b (a second portion of the second isolation structure 126). In further embodiments, the first and second

vertical transfer gates

116c and 116d are disposed at least partially within an inner perimeter (inner perimeter) of the second isolation structure 126. In still other embodiments, the floating diffusion nodes 108 are both disposed outside of the inner perimeter of the second isolation structure 126. In further embodiments, the second isolation structure 126 may comprise an oxide (e.g., SiO)₂) Nitride (e.g., silicon nitride (SiN)), oxynitride (e.g., silicon oxynitride (SiO)), nitride oxide (e.g., silicon oxynitride (SiO)), and/or nitride oxide (e.g., silicon nitride oxide (SiN)), and/or nitride oxide (e.g., silicon nitride oxide (SiO)) and_XN_Y) Silicon carbide (SiC)), carbides (such as silicon carbide (SiC)), or the like.

The reflective structure 128 is disposed on the back side 102b of the first semiconductor substrate 102. The reflective structure 128 is more opaque than the first semiconductor substrate 102. In some embodiments, the reflective structure 128 may comprise, for example, W, Al, Cu, some other metal, or a combination of the foregoing. In further embodiments, the reflective structure 128 may be embedded in the dielectric structure 130. In still other embodiments, the reflective structure 128 is referred to as a metal structure.

At least a portion of the reflective structure 128 is offset from the photodetector 104 in a lateral direction. In other words, at least a portion of the photodetector 104 is disposed outside of the outer perimeter (outer perimeter) of the reflective structure 128. At least a portion of the reflective structure 128 is disposed between opposite sides of the storage node 106. In some embodiments, opposite sides of the storage node 106 are disposed between opposite sidewalls of the reflective structure 128. In further embodiments, the outer perimeter of the storage node 106 is disposed within the outer perimeter of the reflective structure 128. Because at least a portion of the reflective structure 128 is disposed between opposite sides of the storage node 106, the reflective structure 128 may at least partially protect the storage node 106 from incident radiation.

Because the BSIGS image sensor 100 is configured to record incident radiation through the backside 102b of the first semiconductor substrate 102, the BSIGS image sensor 100 may have better Quantum Efficiency (QE) and/or Angular Response (AR) when compared to a front-side illuminated global shutter (FSIGS) image sensor. Furthermore, because the reflective structure 128 at least partially protects the storage node 106 from incident radiation, the BSIGS image sensor 100 may have a high Shutter Efficiency (SE). Furthermore, the second isolation structure 126 may help to provide the BSIGS image sensor 100 with a high SE by at least partially protecting the storage node 106 from incident radiation. Furthermore, the first vertical transfer gate 116c and/or the second vertical transfer gate 116d may help to make the BSIGS image sensor 100 have a high SE by at least partially protecting the storage node 106 from incident radiation. Accordingly, the BSIGS image sensor 100 may have a better QE and/or AR than the FSIGS image sensor while also having a high SE.

Fig. 2 illustrates a cross-sectional view of some other embodiments of the BSIGS image sensor 100 of fig. 1.

As shown in fig. 2, a filter 202 (e.g., an infrared filter, a red filter, a blue filter, a green filter, etc.) is disposed on the dielectric structure 130. The filter 202 is configured to transmit incident radiation of a particular wavelength (or range of wavelengths). It should be appreciated that in some embodiments, the filter 202 is one of a plurality of filters disposed in a filter array. In such embodiments, the plurality of filters may be configured to transmit a particular wavelength (or range of particular wavelengths), respectively. For example, a first filter (e.g., a red filter) may transmit light having wavelengths within a first range, while a second filter (e.g., a blue filter) may transmit light having wavelengths within a second range different from the first range.

In some embodiments, the dielectric structure 130 and the reflective structure 128 are both disposed between the optical filter 202 and the first semiconductor substrate 102. In other embodiments, the optical filter 202 may be disposed between the first semiconductor substrate 102 and the dielectric structure 130 and the reflective structure 128. Dielectric structure 130 can comprise, for example, an oxide (e.g., SiO)₂) Nitride (e.g., SiN), oxynitride (e.g., SiO)_XN_Y) High-k dielectric materials (e.g., hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Or some other dielectric material having a dielectric constant greater than about 3.9), some other dielectric material, or a combination of the foregoing. In another embodiment, the dielectric structure 130 may include a first layer and a second layer. The first layer is stacked on the second layer. The first layer comprises an oxide and the second layer comprises a high-k dielectric material, or may be interchanged with one another.

In some embodiments, the dielectric structure 130 may be a BSI antireflective structure configured to reduce the amount of reflection of incident radiation by the first semiconductor substrate 102. In other embodiments, the dielectric structure 130 may be different from the BSI anti-reflective structure. In such embodiments, the BSI antireflective structure may be disposed between the dielectric structure 130 and the first semiconductor substrate 102, or the dielectric structure 130 may be disposed between the antireflective structure and the first semiconductor substrate 102.

For FSIGS image sensors having an FSI anti-reflective structure, the FSI anti-reflective structure is disposed on the front side of the semiconductor substrate. However, this configuration (orientation) limits the ability to optimize FSI anti-reflection structures to improve QE and/or AR. However, because the BSIGS image sensor 100 is configured to record incident radiation that passes through the backside 102b of the first semiconductor substrate 102, BSI anti-reflective structures are disposed on the backside 102b of the first semiconductor substrate 102. Because the BSI anti-reflective structure is disposed on the backside 102b of the first semiconductor substrate 102, the capabilities of the BSI anti-reflective structure may be better optimized when compared to the FSIGS image sensor, and the bsig image sensor 100 may have better QE and/or AR.

In some embodiments, the microlenses 204 are disposed on the back side 102b of the first semiconductor substrate 102. In further embodiments, the microlenses 204 are disposed on the filters 202. The microlens 204 is configured to focus incident radiation onto the photodetector 104. It should be appreciated that in some embodiments, the microlens 204 is one of a plurality of microlenses configured to focus incident radiation onto a plurality of photodetectors, respectively.

In some embodiments, the reflective structure 128 includes a reflective structure 128a as a first portion, a reflective structure 128b as a second portion, and a reflective structure 128c as a third portion. In further embodiments, the reflective structure 128b as the second portion and the reflective structure 128c as the third portion are both coupled to the reflective structure 128a as the first portion, such that the reflective structure 128 is a continuous structure. In some embodiments, the reflective structure 128a as the first portion may have a circular sidewall.

The reflective structure 128b as the second portion and the reflective structure 128c as the third portion extend from the backside 102b into the first semiconductor substrate 102. The reflective structure 128b as the second portion may be disposed in the second isolation structure 126a (the first portion of the second isolation structure 126). The reflective structure 128c as the third portion may be disposed in the second isolation structure 126b (the second portion of the second isolation structure 126). In some embodiments, the reflective structure 128 is more opaque than the second isolation structure 126. Because the reflective structure 128b (the second portion of the reflective structure 128) and the reflective structure 128c (the third portion of the reflective structure 128) extend into the first semiconductor substrate 102 and along the storage node 106, and because the reflective structure 128 is more opaque than the second isolation structure 126, the reflective structure 128 can further protect the storage node 106 from incident radiation. Accordingly, the reflective structure 128 may further increase the SE of the BSIGS image sensor 100.

In some embodiments, the reflective structure 128b (the second portion of the reflective structure 128) and/or the reflective structure 128c (the third portion of the reflective structure) is at least partially disposed in the dielectric structure 130. In further embodiments, the reflective structure 128b (the second portion of the reflective structure 128) and the reflective structure 128c (the third portion of the reflective structure 128) can both be disposed between opposing sidewalls of the reflective structure 128a (the first portion of the reflective structure 128). The reflective structure 128b (the second portion of the reflective structure 128) and the reflective structure 128c (the third portion of the reflective structure 128) may have sloped sidewalls. In still other embodiments, the second isolation structure 126a (the first portion of the second isolation structure 126) and the second isolation structure 126b (the second portion of the second isolation structure 126) may have sloped sidewalls.

A plurality of sidewall spacers 206 are respectively along the plurality of gates116 are disposed on the sidewalls. For ease of illustration, only one of the sidewall spacers 206 is labeled. In some embodiments, each of the sidewall spacers 206 is disposed along a sidewall of a corresponding one of the gate dielectric layers 118 and a corresponding one of the gate electrodes 120. For example, one of the sidewall spacers 206 is disposed on the front side 102f of the first semiconductor substrate 102 and along sidewalls of the third gate dielectric layer 118c and sidewalls of the third gate electrode 120 c. In some embodiments, the sidewall spacers 206 may comprise, for example, a nitride (e.g., SiN), an oxynitride (e.g., SiO), or the like_XN_Y) Or the like. In further embodiments, the gate dielectric layer 118 may comprise, for example, an oxide (e.g., SiO)₂) High-k dielectric materials (e.g., HfO)₂、ZrO₂Or some other dielectric material having a dielectric constant greater than about 3.9) or the like. In still other embodiments, gate electrode 120 may comprise, for example, polysilicon (e.g., doped/undoped polysilicon), a metal (e.g., W, Al, titanium (Ti), molybdenum (Mo), or the like.

The first ILD structure 122 may include a second ILD structure 208 and a third ILD structure 210. The second ILD structure 208 is disposed over the front side 102f of the first semiconductor substrate 102 and over the plurality of gates 116. The conductive contact structure 124a is disposed in the second ILD structure 208. In some embodiments, the second ILD structure 208 comprises one or more ILD layers that may comprise low-k dielectrics (e.g., dielectric materials having a dielectric constant of less than about 3.9), oxides (e.g., SiO) respectively₂) Or the like.

A third ILD structure 210 is disposed over the second ILD structure 208 and the conductive contact structure 124 a. The via 124b and the conductive line 124c are disposed in the third ILD structure 210. In some embodiments, the third ILD structure 210 comprises one or more ILD layers that may comprise a low-k dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., SiO), respectively₂) Or the like.

In some embodiments, the second semiconductor substrate 212 is disposed over the first ILD structure 122, the first interconnect structure 124, and the front side 102f of the first semiconductor substrate 102. The second semiconductor substrate 212 may comprise any type of semiconductor body (e.g., single crystal silicon/CMOS bulk, SiGe, SOI, etc.). In further embodiments, the second semiconductor substrate 212 is bonded to the first ILD structure 122 via a bonding structure 214. In other embodiments, the second semiconductor substrate 212 is bonded directly to the first ILD structure 122. It is to be appreciated that, in some embodiments, a plurality of conductive features (e.g., bond pads, metal vias, metal lines, through substrate vias, etc.) may be disposed in the bonding structure 214 and/or the second semiconductor substrate 212, thereby providing electrical connections between the first interconnect structure 124 and one or more input/output (I/O) structures (e.g., contact pads, solder bumps, etc.). In still other embodiments, the second semiconductor substrate 212 may be referred to as a carrier substrate.

Also shown in fig. 2, the photodetector 104 is spaced apart from the front side 102f of the first semiconductor substrate 102 by a first distance. The storage node 106 is spaced apart from the front side 102f of the first semiconductor substrate 102 by a second distance that is greater than the first distance. The second isolation structure 126 is spaced apart from the front side 102f of the first semiconductor substrate 102 by a third distance. In some embodiments, the third distance is greater than the first distance and less than the second distance. In other embodiments, the third distance may be less than or equal to the first distance, or greater than or equal to the second distance. In further embodiments, the reflective structure 128b (the second portion of the reflective structure 128) and/or the reflective structure 128c (the third portion of the reflective structure 128) is spaced apart from the front side 102f of the first semiconductor substrate 102 by a fourth distance greater than the third distance. In still other embodiments, the fourth distance may be greater than or equal to the second distance. In other embodiments, the fourth distance may be greater than the first distance and less than the second distance. In still other embodiments, the fourth distance may be less than or equal to the first distance.

The bottommost surface of the first vertical transfer gate 116c and/or the bottommost surface of the second vertical transfer gate 116d is spaced apart from the front side 102f of the first semiconductor substrate 102 by a fifth distance. In some embodiments, the fifth distance is less than the second distance. The fifth distance may be greater than the third distance and less than the fourth distance. In some embodiments, the fifth distance is less than or equal to the third distance. In other embodiments, the fifth distance is greater than or equal to the third distance.

Also shown in fig. 2, the first vertical transfer gate 116c extends into the first semiconductor substrate 102 to a first depth. The first depth is the distance between the front side 102f of the first semiconductor substrate 102 and the bottom most surface of the third gate dielectric layer 118 c. In some embodiments, the first depth is between about 0.5 micrometers (μm) and about 2 micrometers.

The portion of the first vertical transfer gate 116c disposed in the first semiconductor substrate 102 has a first width. The first width is a width of the third gate dielectric layer 118c disposed between outer sidewalls of the first semiconductor substrate 102 that are opposite to each other. In some embodiments, the first width is a maximum width of the third gate dielectric layer 118c disposed between outer sidewalls of the first semiconductor substrate 102 that are opposite to each other. In further embodiments, the first width is between about 0.1 microns and about 0.4 microns.

The second vertical transfer gate 116d extends into the first semiconductor substrate 102 to a second depth. The second depth is the distance between the front side 102f of the first semiconductor substrate 102 and the bottom-most surface of the fourth gate dielectric layer 118 d. In some embodiments, the first depth is between about 0.5 microns and about 2 microns. In further embodiments, the second depth is substantially the same as the first depth. In other embodiments, the second depth is different from the first depth.

The portion of the second vertical transfer gate 116d disposed in the first semiconductor substrate 102 has a second width. The second width is a width of the fourth gate dielectric layer 118d disposed between outer sidewalls opposite to each other in the first semiconductor substrate 102. In some embodiments, the second width is a maximum width of the fourth gate dielectric layer 118d disposed between outer sidewalls of the first semiconductor substrate 102 that are opposite to each other. In further embodiments, the second width is between about 0.1 microns and about 0.4 microns. In yet other embodiments, the second width is substantially the same as the first width. In other embodiments, the second width is different from the first width.

Fig. 3 illustrates a cross-sectional view of some other embodiments of the BSIGS image sensor 100 of fig. 1.

As shown in FIG. 3, in some embodiments, the second gate 116b is disposed directly above the storage node 106. The second gate 116b may be disposed between the first vertical transfer gate 116c and the second vertical transfer gate 116 d. In further embodiments, the floating diffusion node 108 and/or the second doped region 112 may be disposed directly above the storage node 106. The floating diffusion node 108 and/or the second doped region 112 may be disposed between the first vertical transfer gate 116c and the second vertical transfer gate 116 d.

A doped well 302 is disposed in the first semiconductor substrate 102. The doped well 302 is a region of the first semiconductor substrate having a second doping type. In some embodiments, the doped well 302 doped with a dopant of the second doping type (e.g., a p-type dopant) has a higher doping concentration than adjacent regions of the first semiconductor substrate 102. In further embodiments, the second doped region 112 and/or the floating diffusion node 108 are disposed between opposite sides of the doped well 302.

In some embodiments, the doped well 302 is disposed directly between the second gate 116b and the storage node 106, directly between the second doped region 112 and the storage node 106, and directly between the floating diffusion node 108 and the storage node 106. In some embodiments, the doped well 302 may extend under at least a portion of the first isolation structure 114. In further embodiments, the doped well 302 may be disposed directly between a portion of the first vertical transfer gate 116c and the storage node 106 and/or between a portion of the second vertical transfer gate 116d and the storage node 106. In other embodiments, the doped well 302 may be spaced a lateral distance from the first vertical transfer gate 116c and/or the second vertical transfer gate 116 d. In yet other embodiments, the doped well 302 may be spaced apart from the storage node 106.

A doped isolation region (doped isolation region)303 is disposed in the first semiconductor substrate 102. The doped isolation region 303 is a region of the first semiconductor substrate having the second doping type. In some embodiments, the doped isolation region 303 is spaced apart from the storage node 106, the floating diffusion node 108, and the second doped region 112. The doped isolation region 303 may be spaced apart from the first isolation structure 114. The doped isolation region 303 may be disposed directly between the second gate 116b and the storage node 106, directly between the second doped region 112 and the storage node 106, and/or directly between the floating diffusion node 108 and the storage node 106.

In some embodiments, the doped isolation region 303 may extend under at least a portion of the first isolation structure 114. In further embodiments, the doped isolation region 303 may be disposed directly between a portion of the first vertical transfer gate 116c and the storage node 106 and/or between a portion of the second vertical transfer gate 116d and the storage node 106. In other embodiments, the doped isolation region 303 may be spaced apart from the first vertical transfer gate 116c and/or the second vertical transfer gate 116d by a lateral distance.

In some embodiments, the doped isolation region 303 formed with the second doping type dopant has a higher doping concentration than the doped well 302. The doped isolation region 303 formed with the second dopant type dopant may have a thickness of between about 5 x 10¹⁵cm^-3And about 5X 10¹⁸cm^-3With the doping concentration in between. Since the doped well 302 formed with the second dopant type dopant has a thickness of between about 5 x 10¹⁵cm^-3And about 5X 10¹⁸cm^-3In between, the doped isolation region 303 may improve QE, AR, and/or SE of the BSIGS image sensor 100 by improving electrical isolation (e.g., via p-n junction isolation) between the storage node 106 and the floating diffusion node 108 and/or between the second doped region 112.

Also shown in fig. 3, an Integrated Chip (IC) 304 is disposed over the first semiconductor substrate 102, the first ILD structure 122, and the first interconnect structure 124. The IC 304 includes a third semiconductor substrate 306. The third semiconductor substrate 306 may comprise any type of semiconductor body (e.g., single crystal silicon/CMOS bulk, SiGe, SOI, etc.). A plurality of semiconductor devices 308 a-308 b (e.g., p-channel MOSFETs, n-channel MOSFETs, etc.) are disposed on the third semiconductor substrate 306. In some embodiments, semiconductor devices 308 a-308 b are image processing devices configured to process signals output by storage node 106.

A fourth ILD structure 310 is disposed between the third semiconductor substrate 306 and the first ILD structure 122. In some embodiments, the fourth ILD structure 310 comprises one or more stacked ILD layers that may comprise, respectively, a low-k dielectric material (e.g., a dielectric material having a dielectric constant of less than about 3.9), an oxide (e.g., silicon dioxide (SiO)₂) ) or the like. A second interconnect structure 312 (e.g., a copper interconnect) is disposed in the fourth ILD structure 310. The second interconnect structure 312 includes a plurality of conductive features (e.g., metal lines, metal vias, metal contacts, bond pads, etc.). In further embodiments, the plurality of conductive features may include, for example, Cu, Al, W, Au, some other conductive material, or a combination of the foregoing. It is understood that in some embodiments, one or more conductive features (e.g., through substrate vias) may be disposed in the third semiconductor substrate 306, providing electrical connections between the second interconnect structure 312 and the one or more I/O structures.

The fourth ILD structure 310 is bonded to the third ILD structure 210. The first interconnect structure 124 may include a plurality of first conductive bonding pads 124 d. The second interconnect structure 312 may include a plurality of second conductive bonding pads 312 a. In some embodiments, the first conductive bonding pads 124d are respectively bonded to the second conductive bonding pads 312 a. In further embodiments, the first conductive bond pads 124d are respectively electrically coupled to the second conductive bond pads 312a, providing electrical connections between features (e.g., AB gates, vertical transfer gates, reset gates, source follower gates, source/drain regions, floating diffusion nodes, etc.) disposed on the first semiconductor substrate to a plurality of semiconductor devices 308 a-308 b disposed on the third semiconductor substrate 306.

Fig. 4 illustrates a cross-sectional view of some other embodiments of the BSIGS image sensor 100 of fig. 1.

As shown in fig. 4, a third doped region 402 is disposed in the first semiconductor substrate 102. The third doped region is a region of the first semiconductor substrate 102 having the second doping type. The third doped region 402 is disposed between the photodetector 104 and the front side 102f of the first semiconductor substrate 102.

A plurality of fourth doped regions 404 is disposed in the first semiconductor substrate 102. For ease of illustration, only one of the fourth doped regions 404 is labeled. The fourth doped region 404 is a region of the first semiconductor substrate 102 having the second doping type. The fourth doped region 404 may extend from the front side 102f of the first semiconductor substrate 102 into the first semiconductor substrate 102. A first one of the fourth doped regions 404 may extend into the first semiconductor substrate 102 between the photodetector 104 and the storage node 106. A second one of the fourth doped regions 404 may extend into the first semiconductor substrate 102 on an opposite side of the photodetector 104 as the first one of the fourth doped regions 404. A third one of the fourth doped regions 404 may extend into the first semiconductor substrate 102 on an opposite side of the storage node 106 as the first one of the fourth doped regions 404. In some embodiments, a third one of the fourth doped regions 404 is disposed directly below a portion of the first isolation structure 114. In further embodiments, the first doped region 110 may be disposed in a second one of the fourth doped regions 404.

In some embodiments, the bottom side of the fourth doped region 404 is disposed between the backside 102b of the first semiconductor substrate 102 and both the storage node 106 and the photodetector 104. In further embodiments, the fourth doped region 404 is spaced apart from the backside 102b of the first semiconductor substrate 102. The fourth doped region 404 may have different widths. For example, a first one of the fourth doped regions 404 may have a third width, and a second one (and/or a third one) of the fourth doped regions 404 may have a fourth width different from the third width. In still other embodiments, the second isolation structure 126 is at least partially disposed in the fourth doped region 404.

The doped isolation region 303 may be disposed between the reflective structure 128b (the second portion of the reflective structure 128) and the reflective structure 128c (the third portion of the reflective structure 128). In some embodiments, the bottom side of the doped isolation region 303 may be disposed between the front side 102f of the first semiconductor substrate 102 and the uppermost surface of the reflective structure 128b (the second portion of the reflective structure 128) and/or between the front side 102f and the uppermost surface of the reflective structure 128c (the third portion of the reflective structure 128). In other embodiments, the uppermost surface of the reflective structure 128b (the second portion of the reflective structure 128) and/or the uppermost surface of the reflective structure 128c (the third portion of the reflective structure 128) is disposed between the upper side of the doped isolation region 303 and the bottom side of the doped isolation region 303. In still other embodiments, an uppermost surface of the reflective structure 128b (the second portion of the reflective structure 128) and/or an uppermost surface of the reflective structure 128c (the third portion of the reflective structure 128) is disposed between the front side 102f of the first semiconductor substrate 102 and the upper side of the doped isolation region 303. In further embodiments, a portion of the first vertical transfer gate 116c is disposed between the second isolation structure 126a (the first portion of the second isolation structure 126) and the doped isolation region 303. In further embodiments, a portion of the second vertical transfer gate 116d is disposed between the second isolation structure 126b (the second portion of the second isolation structure 126) and the doped isolation region 303.

In some embodiments, the dielectric structure 130 may include a first dielectric layer 130a and a second dielectric layer 130 b. The first dielectric layer 130a is disposed between the second dielectric layer 130b and the first semiconductor substrate 102. The first dielectric layer 130a may have a substantially planar bottom surface. The reflective structure 128a (a first portion of the reflective structure 128) may be embedded in the first dielectric layer 130 a. In further embodiments, the reflective structure 128a (the first portion of the reflective structure 128) has a substantially flat bottom surface that is coplanar with the bottom surface of the first dielectric layer 130 a. In still other embodiments, the first dielectric layer 130a may comprise, for example, an oxide (e.g., SiO)₂) Nitride (e.g., SiN), oxynitride (e.g., SiO)_XN_Y) High-k dielectric materials (e.g., HfO)₂、ZrO₂Or some other dielectric material having a dielectric constant greater than about 3.9), some other dielectric material, or a combination of the foregoing.

The second dielectric layer 130b separates the reflective structure 128a (the first portion of the reflective structure 128) from the filter 202. The second dielectric layer 130b may have a substantially flat bottom surface. In some embodiments, the second dielectric layer 130b can include, for example, an oxide (e.g., SiO)₂) Nitride (e.g., SiN), oxynitride (e.g., SiO)_XN_Y) High-k dielectric materials (e.g., HfO)₂、ZrO₂Or some other dielectric material having a dielectric constant greater than about 3.9), some other dielectric material, or a combination of the foregoing. In further embodiments, the second dielectric layer 130b may contact a bottom surface of the first dielectric layer 130a and a bottom surface of the reflective structure 128a (the first portion of the reflective structure 128). In still other embodiments, the first dielectric layer 130a and the second dielectric layer 130b may comprise the same dielectric material. In other embodiments, the first dielectric layer 130a and the second dielectric layer 130b may comprise different dielectric materials.

Fig. 5-20 illustrate a series of cross-sectional views for forming some embodiments of the BSIGS image sensor 100 of fig. 4.

As shown in fig. 5, a first isolation structure 114 is formed in the first semiconductor substrate 102. In some embodiments, the first isolation structure 114 may be formed by: the first semiconductor substrate 102 is selectively etched to form trenches on the first semiconductor substrate 102, and the trenches are subsequently filled with a dielectric material. In further embodiments, the first semiconductor substrate 102 is selectively etched by: a mask layer (e.g., a positive/negative photoresist) (not shown) is formed on the front side 102f of the first semiconductor substrate 102, and the first semiconductor substrate 102 is subsequently exposed to an etchant (e.g., a wet/dry etchant) to remove unmasked portions of the first semiconductor substrate 102. Subsequently, in some embodiments, the mask layer is stripped. In still other embodiments, the dielectric material may comprise an oxide (e.g., SiO)₂) Nitride (e.g., SiN), oxynitride (e.g., SiO)_XN_Y) Carbide (e.g., SiC), or the like. It is understood that in some embodiments, the first semiconductor substrate 102 may be doped (e.g., via ion implantation) with the second doping type (e.g., p-type/n-type) prior to forming the first isolation structure 114.

As shown in fig. 6, a photodetector 104 is formed in the first semiconductor substrate 102. The photodetector 104 includes a region of the first semiconductor substrate 102 having a first doping type (e.g., n-type/p-type) opposite a second doping type. In some embodiments, the photodetector 104 may be formed by a first implantation process (e.g., via ion implantation) that utilizes a first mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 to selectively implant first doping-type dopants (e.g., n-type dopants) into the first semiconductor substrate 102. Subsequently, in some embodiments, the first mask layer is stripped.

Also shown in fig. 6, a storage node 106 is formed in the first semiconductor substrate 102. The storage node 106 is a region of the first semiconductor substrate 102 having a first doping type. In some embodiments, the storage node 106 is deeper in the first semiconductor substrate 102 (e.g., spaced further from the front side 102 f) than in the photodetector 104. In some embodiments, the storage node 106 may be formed by a second implantation process that utilizes a second mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 to selectively implant the first dopant-type dopant into the first semiconductor substrate 102. Subsequently, in some embodiments, the second mask layer is stripped. In further embodiments, the storage node 106 and the photodetector 104 may be formed by the same selective implantation process (e.g., using the same mask layer and/or the same ion implantation process).

As shown in fig. 7, a doped well 302 is formed in the first semiconductor substrate 102. The doped well 302 is a region of the first semiconductor substrate 102 having a second doping type. In some embodiments, the doped well 302 is formed directly over the storage node 106. In further embodiments, the doped wells 302 may be formed by a first implantation process that utilizes a first mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 to selectively implant second dopant-type dopants (e.g., p-type dopants) into the first semiconductor substrate 102. Subsequently, in some embodiments, the first mask layer is stripped.

Also shown in fig. 7, a doped isolation region 303 is formed in the first semiconductor substrate 102. The doped isolation region 303 is a region of the first semiconductor having the second doping type. In some embodiments, the doped isolation region 303 formed with the second dopant has a higher doping concentration than the doped well 302 also formed with the second dopant. In further embodiments, the doped isolation region 303 may be formed in the doped well 302. It is to be appreciated that the doped isolation region 303 can be formed before or after the doped well 302 is formed.

In some embodiments, the process for forming the doped isolation region 303 includes forming a second mask layer on the front side 102f of the first semiconductor substrate 102. Thereafter, a second implantation process is performed with the second mask layer in place to implant second dopant-doped type dopants into the unmasked portions of the first semiconductor substrate 102, thereby forming doped isolation regions 303. Subsequently, in some embodiments, the second mask layer is stripped.

In some embodiments, the second implantation process implants dopants of the second doping type into the first semiconductor substrate 102 such that the doped isolation region 303 has a thickness of between about 5 x 10¹⁵cm^-3And about 5X 10¹⁸cm^-3Doping concentration of the second doping-type dopant in between. It should be appreciated that in some embodiments, the second mask layer is not formed, but rather the first semiconductor substrate 102 may be masked with the first mask layer during the second implantation process. In other embodiments, a second mask layer may be formed on the first mask layer and the first semiconductor substrate 102, and both the first mask layer and the second mask layer may be stripped after the second implantation process.

Also shown in fig. 7, a plurality of fourth doped regions 404 are formed in the first semiconductor substrate 102. The fourth doped region 404 is a region of the first semiconductor substrate 102 having the second doping type. In some embodiments, the fourth doping region 404 may be formed by a third implantation process that utilizes a third mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 to selectively implant the second doping type dopant into the first semiconductor substrate 102. Subsequently, in some embodiments, the third mask layer is stripped. It is to be appreciated that the fourth doped region 404 may be formed before or after forming the doped well 302, or may be formed before or after forming the doped isolation region 303.

As shown in fig. 8, a plurality of openings 802a to 802b are formed in the first semiconductor substrate 102. For example, a first opening 802a and a second opening 802b are formed in the first semiconductor substrate 102 and are spaced apart from each other. A first opening 802a and a second opening 802b may be formed on opposite sides of the doped isolation region 303. The openings 802a to 802b are formed to extend from the front side 102f of the first semiconductor substrate 102 into the first semiconductor substrate 102. In some embodiments, openings 802 a-802 b are formed with sloped sidewalls. The openings 802 a-802 b may be formed with a bottom surface disposed between the storage node 106 and the bottom surface of the first isolation structure 114. In further embodiments, the process for forming the openings 802 a-802 b includes forming a mask layer (not shown) on the front side 102f of the first semiconductor substrate 102. Thereafter, the first semiconductor substrate 102 is exposed to an etchant to remove unmasked portions of the first semiconductor substrate 102, thereby forming openings 802a through 802 b. Subsequently, in some embodiments, the mask layer is stripped.

As shown in fig. 9, a gate dielectric layer 902 is formed on the front side 102f of the first semiconductor substrate 102 and lines the openings 802a through 802 b. In some embodiments, the process for forming the gate dielectric layer 902 includes depositing or growing the gate dielectric layer 902 on the first semiconductor substrate 102. The gate dielectric layer 902 may be deposited or grown by, for example, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, sputtering, some other deposition or growth process, or a combination of the foregoing. In further embodiments, the gate dielectric layer 902 may comprise, for example, an oxide (e.g., SiO)₂) High-k dielectric materials (e.g., HfO)₂、ZrO₂Or some other dielectric material having a dielectric constant greater than about 3.9) or the like.

Also shown in fig. 9, a gate electrode layer 904 is formed over the gate dielectric layer 902. In some embodiments, the process for forming the gate electrode layer 904 includes depositing the gate electrode layer 904 over the gate dielectric layer 902. The gate electrode layer 904 can be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In further embodiments, the gate electrode layer 904 may comprise, for example, polysilicon (e.g., doped/undoped polysilicon), a metal (e.g., W, Al, Ti, Mo, or the like), or the like.

As shown in fig. 10, a plurality of gates 116 are formed on the front side 102f of the first semiconductor substrate 102. For example, a first gate 116a, a second gate 116b, a first vertical transfer gate 116c, and a second vertical transfer gate 116d are formed on/in the first semiconductor substrate 102 and spaced apart from each other. In some embodiments, the process for forming the plurality of gates 116 includes forming a mask layer (not shown) over the gate electrode layer 904 (see, e.g., fig. 9). Thereafter, the gate electrode layer 904 and the gate dielectric layer 902 are exposed to an etchant. The etchant removes unmasked portions of the gate electrode layer 904 to form a plurality of gate electrodes 120 on the gate dielectric layer 902, and removes unmasked portions of the gate dielectric layer 902 to form a plurality of gate dielectric layers 118. Subsequently, the mask layer may be stripped. It is understood that one or more etchant and/or mask layers may be used to form the plurality of gates 116.

As shown in fig. 11, a plurality of sidewall spacers 206 are formed over the first semiconductor substrate 102 and along sidewalls of the plurality of gates 116. In some embodiments, the sidewall spacers 206 may be formed by depositing a spacer layer (not shown) over the first semiconductor substrate 102 and over the plurality of gates 116. In further embodiments, the spacer layer may be deposited by PVD, CVD, ALD, sputtering or the like. The spacer layer is then etched to remove the spacer layer from the horizontal surfaces, leaving the spacer layer extending along opposite sides of the plurality of gates 116 as sidewall spacers 206. In some embodiments, the spacer layer may comprise, for example, a nitride (e.g., SiN), an oxynitride (e.g., SiO), or the like_XN_Y) Or the like. It is understood that in some embodiments, the lightly doped source/drain regions may be formed in the first semiconductor substrate 102 prior to forming the sidewall spacers 206.

Also shown in fig. 11, a third doped region 402 is formed in the first semiconductor substrate 102. In some embodiments, the third doped region 402 has the second doping type. In further embodiments, the third doped region 402 may be formed at least partially in the photodetector 104. In yet other embodiments, the process for forming the third doped region 402 includes forming a mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 and over the plurality of gates 116. Thereafter, after the mask layer is in place, an implantation process is performed to selectively implant second dopant-doping type dopants into the first semiconductor substrate 102. Subsequently, in some embodiments, the mask layer is stripped.

As shown in fig. 12, a floating diffusion node 108, a first doped region 110, and a second doped region 112 are formed in a first semiconductor substrate 102. The floating diffusion node 108 is a region of the first semiconductor substrate 102 having a first doping type. In some embodiments, the first doped region 110 has a first doping type. In further embodiments, the second doped region 112 has a first doping type. The floating diffusion node 108 and the second doped region 112 may be formed in the doped well 302. In further embodiments, the floating diffusion node 108 and the second doped region 112 are formed between the first vertical transfer gate 116c and the second vertical transfer gate 116 d. In still other embodiments, the first doped region 110 may be formed in one of the fourth doped regions 404.

In some embodiments, the process for forming the floating diffusion node 108, the first doped region 110, and the second doped region 112 includes forming a mask layer (not shown) covering the plurality of gates 116 on the front side 102f of the first semiconductor substrate 102. Thereafter, after the mask layer is in place, an implantation process is performed to selectively implant first dopant-doped species into the first semiconductor substrate 102. It should be appreciated that in some embodiments, multiple implantation processes are performed to form the floating diffusion node 108, the first doped region 110, and the second doped region 112.

As shown in fig. 13, a second ILD structure 208 is formed over the front side 102f of the first semiconductor substrate 102 and over the plurality of gates 116. In some embodiments, the second ILD structure 208 may be formed with a substantially planar upper surface. In further embodiments, the process for forming the second ILD structure 208 includes depositing an ILD layer on the first semiconductor substrate 102 such that the ILD layer covers the plurality of gates 116. The ILD layer may be deposited by CVD, PVD, sputtering, or some other deposition process. Thereafter, a planarization process (e.g., chemical-mechanical polishing (CMP)) may be performed on the ILD layer.

Also shown in fig. 13, a plurality of conductive contact structures 124a are formed extending through the second ILD structure 208. The conductive contact structure 124a may be formed to extend to the plurality of gate electrodes 120 and/or the first semiconductor substrate 102 (e.g., the floating diffusion node 108, the first doped region 110, the second doped region 112, etc.). In some embodiments, the process for forming the conductive contact structure 124a includes forming a plurality of conductive contact structure openings in the second ILD structure 208 that extend to the plurality of gates 116 and/or the first semiconductor substrate 102. The conductive contact structure openings may be formed by a selective etch process that selectively exposes the second ILD structure 208 to an etchant using a masking layer (not shown) on the second ILD structure 208 to remove unmasked portions of the second ILD structure 208. Subsequently, in some embodiments, the mask layer is stripped.

Subsequently, a conductive material (e.g., W) is deposited on the second ILD structure 208 such that the conductive material fills the conductive contact structure openings. Subsequently, a planarization process (e.g., CMP) is performed on the conductive material, thereby forming the conductive contact structure 124 a. In some embodiments, the conductive material may be deposited by CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing.

As shown in fig. 14, a third ILD structure 210, a plurality of vias 124b, a plurality of conductive lines 124c, and a plurality of first conductive bonding pads 124d are formed over the second ILD structure 208 and the conductive contact structure 124 a. The third ILD structure 210 may be formed with a substantially planar upper surface. In some embodiments, the process for forming the third ILD structure 210 includes depositing a plurality of ILD layers stacked on top of each other over the second ILD structure 208 and the conductive contact structure 124 a. The ILD layer may be deposited by CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. In further embodiments, a planarization process (e.g., CMP) may be performed on one or more of the plurality of ILD layers.

In some embodiments, the process for forming the conductive line 124c, the via 124b, and the first conductive bond pad 124d includes forming a first ILD layer over the second ILD structure 208 and the conductive contact structure 124 a. The first ILD layer is selectively etched to form a first set of conductive line openings (not shown) corresponding to the first set of conductive lines 124 c. A conductive material (e.g., Cu) is deposited on the first ILD layer and in the first set of conductive line openings. A planarization process (e.g., CMP) is performed on the conductive material, forming a first set of conductive lines 124 c.

Thereafter, a second ILD layer is formed over the first set of conductive lines and the first ILD layer. The second ILD layer is selectively etched to form a first set of via openings (not shown) corresponding to the first set of vias 124 b. A conductive material (e.g., Cu) is deposited over the second ILD layer and in the first set of via openings. A planarization process (e.g., CMP) is performed on the conductive material to form the first set of via holes 124 b. This process is repeated (e.g., alternately forming conductive lines and vias) until conductive lines 124c and vias 124b are formed. It is understood that in some embodiments, conductive line 124c and via 124b may be formed by one or more dual damascene processes.

Thereafter, a third ILD layer is formed over the conductive line 124c, the first ILD layer, the via 124b, and the second ILD layer. The third ILD layer is selectively etched to form a plurality of bond pad openings (not shown) on the third ILD layer. A conductive material (e.g., Cu, Au, etc.) is deposited on the third ILD layer and in the bond pad openings. A planarization process (e.g., CMP) is performed on the conductive material, thereby forming a first conductive bonding pad 124 d. In yet other embodiments, the formation of the first ILD structure 122 is completed after the formation of the first conductive bonding pad 124 d.

As shown in fig. 15, an Integrated Chip (IC) 304 is bonded to the first semiconductor substrate 102. In some embodiments, IC 304 includes: a third semiconductor substrate 306; a plurality of semiconductor devices 308a to 308 b; a fourth ILD structure 310; and a second interconnect structure 312 including a plurality of second conductive bonding pads 312 a. In further embodiments, the process for bonding the IC 304 to the first semiconductor substrate 102 includes placing the IC 304 such that the second conductive bond pads 312a are substantially aligned with and face the first conductive bond pads 124d, respectively. Thereafter, the second conductive bonding pads 312a are bonded to the first conductive bonding pads 124d, respectively (e.g., via a hybrid bonding process, a direct bonding process, etc.). It is understood that in some embodiments, the fourth ILD structure 310 is bonded to the third ILD structure 210.

As shown in fig. 16, a second isolation structure 126 is formed in the first semiconductor substrate 102. The second isolation structure 126 is formed to extend from the back side 102b of the first semiconductor substrate 102 into the first semiconductor substrate 102. A second isolation structure 126a, which is a first portion of the second isolation structure 126, may be formed to extend into the first semiconductor substrate 102 and between the storage node 106 and the photodetector 104. The second isolation structure 126b, which is a second portion of the second isolation structure 126, may be formed to extend into the first semiconductor substrate 102 and may be formed on an opposite side of the storage node 106 as the second isolation structure 126a (a first portion of the second isolation structure 126). In some embodiments, the second isolation structure 126a (a first portion of the second isolation structure 126) may be formed in one of the fourth doped regions 404, and the second isolation structure 126b (a second portion of the second isolation structure 126) may be formed in another one of the fourth doped regions 404.

In some embodiments, the process for forming the second isolation structure 126 includes selectively etching the first semiconductor substrate 102 to form an isolation structure opening on the first semiconductor substrate 102 that extends from the back side 102b of the first semiconductor substrate 102 into the first semiconductor substrate 102. Thereafter, the isolation structure openings are filled with a dielectric material (e.g., via CVD, PVD, ALD, thermal oxidation, sputtering, etc.). In further embodiments, the first semiconductor substrate 102 is selectively etched by: a mask layer (not shown) is formed on the backside 102b of the first semiconductor substrate 102, and the first semiconductor substrate 102 is subsequently exposed to an etchant configured to remove unmasked portions of the first semiconductor substrate 102. In further embodiments, the dielectric material may include an oxide (e.g., SiO)₂) Nitride (e.g., SiN), oxynitride (e.g., SiO)_XN_Y) Carbide (e.g., SiC), or the like. In yet other embodiments, a planarization process (e.g., CMP) may be performed on the dielectric material and the first semiconductor substrate 102 to form a substantially planar surface. It is understood that in some embodiments, the first semiconductor substrate 102 may be thinned (e.g., via grinding, CMP, or the like) before (or after) forming the second isolation structures 126.

As shown in fig. 17, a first dielectric layer 130a is formed on the backside 102b of the first semiconductor substrate 102 and the second isolation structure 126. In some embodiments, the first dielectric layer 130a may be formed by CVD, PVD, ALD, sputtering, or the like. Subsequently, in some embodiments, a planarization process (e.g., CMP) may be performed on the first dielectric layer 130a to planarize an upper surface of the first dielectric layer 130 a.

As shown in fig. 18, a reflective structure 128 is formed on the back side 102b of the first semiconductor substrate 102. In some embodiments, the reflective structure 128 is formed to extend from the backside 102b into the first semiconductor substrate 102. For example, the reflective structure 128a as a first portion of the reflective structure 128 may be formed in the first dielectric layer 130a, the reflective structure 128b as a second portion of the reflective structure 128 may be formed in the second isolation structure 126a (a first portion of the second isolation structure 126), and the reflective structure 128c as a third portion of the reflective structure 128 may be formed in the second isolation structure 126b (a second portion of the second isolation structure 126).

In some embodiments, the process for forming the reflective structure 128 includes forming a first opening (not shown) in the first dielectric layer 130a corresponding to the reflective structure 128a (the first portion of the reflective structure 128). The first opening may be formed by a first selective etching process that selectively exposes the first dielectric layer 130a to a first etchant that removes unmasked portions of the first dielectric layer 130a using a first mask layer (not shown) on the first dielectric layer 130 a. Subsequently, in some embodiments, the first mask layer is stripped.

Thereafter, a plurality of second openings extending into the second isolation structures are formed. The second openings correspond to the reflective structure 128b (the second portion of the reflective structure 128) and the reflective structure 128c (the third portion of the reflective structure 128), respectively. The second opening may be formed by a second selective etch process that selectively exposes the first dielectric layer 130a and the second isolation structure 126 to a second etchant that removes unmasked portions of the first dielectric layer 130a and unmasked portions of the second isolation structure 126 using a second mask layer (not shown) on the first dielectric layer 130 a. Next, a conductive material (e.g., W, Al, Cu, etc.) is deposited on the first dielectric layer 130a, in the first opening, and in the second opening. A planarization process (e.g., CMP) is performed on the conductive material to form the reflective structure 128. Subsequently, in some embodiments, the second mask layer is stripped. It is understood that in some embodiments, a second mask layer may be formed on the first mask layer and the first dielectric layer 130a, and the first mask layer and the second mask layer may be stripped after depositing the conductive material.

As shown in fig. 19, a second dielectric layer 130b is formed on the first dielectric layer 130a and the reflective structure 128. Which in some embodiments may be formed by CVD, PVD, ALD, sputtering, or the like, the second dielectric layer 130 b. Subsequently, in some embodiments, a planarization process (e.g., CMP) may be performed on the second dielectric layer 130b to planarize an upper surface of the second dielectric layer 130 b. In some embodiments, after forming the second dielectric layer 130b, the formation of the dielectric structure 130 is completed. In further embodiments, the dielectric structure 130 may be a BSI antireflective structure configured to reduce the amount of reflection of incident radiation by the first semiconductor substrate 102. In other embodiments, the dielectric structure 130 may be different from the BSI anti-reflective structure. In such embodiments, it is understood that the BSI antireflective layer may be formed (e.g., via CVD, PVD, ALD, sputtering, etc.) prior to (or after) forming the dielectric structure 130.

As shown in fig. 20, an optical filter 202 is formed on the dielectric structure 130. In some embodiments, the filter 202 is formed on the second dielectric layer 130 b. In some embodiments, the process for forming the optical filter 202 includes depositing (e.g., via CVD, PVD, ALD, sputtering, spin-coating, etc.) a light filtering material onto the dielectric structure 130. A light filtering material is a material that allows radiation (e.g., light) having a particular range of wavelengths to be transmitted while blocking light of wavelengths outside the specified range. Subsequently, in some embodiments, a planarization process (e.g., CMP) may be performed on the filter 202 to planarize an upper surface of the filter 202.

Also shown in fig. 20, microlenses 204 are formed on the filter 202. In some embodiments, the microlenses 204 may be formed by depositing a microlens material (e.g., via CVD, PVD, ALD, sputtering, spin-coating, etc.) on the filter 202. A microlens template (not shown) having an arcuate upper surface is patterned on the microlens material. In some embodiments, the microlens template can comprise a photoresist material that is exposed, developed, and baked to form a circular shape using a dispensed exposure dose (e.g., for a negative photoresist, more light is exposed at the bottom of the bends and less light is exposed at the top of the bends). Next, microlenses 204 are formed by selectively etching the microlens material according to the microlens template. In further embodiments, after forming the microlenses 204, the formation of the BSIGS image sensor 100 is completed.

Fig. 21 illustrates a flow diagram 2100 of some embodiments of a method for forming a backside illuminated global shutter (BSIGS) image sensor 100. While the flowchart 2100 of fig. 21 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated order of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more of the acts depicted herein may be performed in one or more separate acts and/or phases.

At act 2102, a photodetector and a storage node are formed in a first semiconductor substrate, wherein the first semiconductor substrate includes a front side and a back side opposite the front side. Fig. 5-6 illustrate a series of cross-sectional views of some embodiments corresponding to act 2102.

At act 2104, a plurality of gates are formed on a front side of a semiconductor substrate, where the plurality of gates includes a first vertical transfer gate and a second vertical transfer gate extending into the semiconductor substrate from the front side. Fig. 7-11 illustrate a series of cross-sectional views corresponding to some embodiments of act 2104. In some embodiments, a doped isolation region may be formed in the first semiconductor substrate prior to forming the plurality of gates. Figure 7 illustrates a cross-sectional view of some embodiments for forming doped isolation regions.

At act 2106, a floating diffusion node, a first doped region, and a second doped region are formed in a first semiconductor substrate. Figure 12 illustrates a cross-sectional view of some embodiments corresponding to act 2106.

At act 2108, an inter-layer dielectric (ILD) structure is formed on the front side of the first semiconductor substrate and over the plurality of gates. Figures 13-14 illustrate a series of cross-sectional views of some embodiments corresponding to act 2108.

At act 2110, a second semiconductor substrate is bonded to the first semiconductor substrate, wherein the first semiconductor substrate is separated from the second semiconductor substrate by the ILD structure. Figure 15 illustrates a cross-sectional view of some embodiments corresponding to act 2110.

At act 2112, an isolation structure is formed in the first semiconductor substrate that extends into the first semiconductor substrate from the backside of the first semiconductor substrate. Figure 16 illustrates a cross-sectional view of some embodiments that corresponds to act 2112.

At act 2114, a reflective structure is formed on the backside of the first semiconductor substrate, wherein at least a portion of the reflective structure is disposed between opposite sides of the storage node. Fig. 17-19 illustrate a series of cross-sectional views of some embodiments corresponding to act 2114. In some embodiments, filters and/or microlenses are formed on the backside of the first semiconductor substrate. FIG. 20 illustrates a cross-sectional view of some embodiments for forming filters and/or microlenses.

In some embodiments, the image sensor further comprises: a metal structure disposed on the second side, wherein a first portion of the metal structure is disposed between opposing sides of the storage node.

In some embodiments, at least a portion of the metal structure is offset from the photodetector in a lateral direction.

In some embodiments, the opposite sides of the storage node are disposed between mutually opposite sidewalls of the metal structure.

In some embodiments, a second portion of the metal structure is disposed in the first isolation structure and extends from the second side into the semiconductor substrate.

In some embodiments, the second portion of the metal structure is spaced apart from the first side by a third distance that is greater than the first distance.

In some embodiments, the image sensor further comprises: a microlens disposed on the second side, wherein the metal structure is disposed between the microlens and the semiconductor substrate.

In some embodiments, the image sensor further comprises: a dielectric structure disposed between the microlens and the semiconductor substrate, wherein the metal structure is disposed in the dielectric structure.

In some embodiments, the image sensor further comprises: a first vertical transfer gate configured to selectively form a first conductive channel between the photodetector and the storage node, wherein the first vertical transfer gate extends into the semiconductor substrate from the first side, and wherein a bottom-most surface of the first vertical transfer gate is spaced apart from the first side by a fourth distance that is greater than the second distance.

In some embodiments, the image sensor further comprises: a second vertical transfer gate spaced apart from the first vertical transfer gate and configured to selectively form a second conductive channel between the storage node and a floating diffusion node, wherein the second vertical transfer gate extends into the semiconductor substrate from the first side, and wherein a bottom-most surface of the second vertical transfer gate is spaced apart from the first side by a fifth distance that is greater than the second distance.

In some embodiments, the image sensor further comprises: a second isolation structure disposed in the semiconductor substrate and separated from the first isolation structure by the storage node, wherein the second isolation structure extends into the semiconductor substrate from the second side, and wherein the first vertical transfer gate and the second vertical transfer gate are both disposed at least partially between the first isolation structure and the second isolation structure.

In some embodiments, the second isolation structure is spaced apart from the first side by a sixth distance that is less than the first distance and the fourth distance.

In some embodiments, the image sensor further comprises: a doped isolation region disposed in the semiconductor substrate between the first vertical transfer gate and the second vertical transfer gate, wherein the doped isolation region is disposed between the storage node and the floating diffusion node, and wherein the doped isolation region and the floating diffusion node have opposite doping types.

In some embodiments, the image sensor further comprises: a doped isolation region disposed in the semiconductor substrate, wherein the doped isolation region is disposed between the storage node and at least a second portion of the first vertical transfer gate, and wherein the doped isolation region and the storage node have opposite doping types.

In some embodiments, the image sensor further comprises: a reflective structure disposed on a second side of the semiconductor substrate opposite the first side, wherein opposite sides of the storage node are disposed between sidewalls of the reflective structure that are opposite each other.

In some embodiments, the image sensor further comprises: a first isolation structure extending into the semiconductor substrate from a second side of the semiconductor substrate opposite the first side, wherein the first isolation structure extends into the semiconductor substrate and is located between the storage node and the photodetector, and wherein the first portion of the first vertical transfer gate and the photodetector are disposed on opposite sides of the first isolation structure.

In some embodiments, the image sensor further comprises: a second vertical transfer gate spaced apart from the first vertical transfer gate and configured to selectively form a second conductive channel between the storage node and a floating diffusion node, wherein a portion of the second vertical transfer gate extends into the semiconductor substrate from the first side by a fourth distance, and wherein the fourth distance is greater than the first distance and less than the second distance.

In some embodiments, the first isolation structure laterally surrounds the storage node; the first portion of the first vertical transfer gate and the portion of the second vertical transfer gate are both disposed within an inner perimeter of the first isolation structure; and the floating diffusion node and the photodetector are both disposed outside of the inner perimeter of the first isolation structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising:

a photodetector disposed in the semiconductor substrate;

an interlayer dielectric structure disposed on a first side of the semiconductor substrate;

a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance; and

a first isolation structure disposed in the semiconductor substrate and between the photodetector and the storage node, wherein the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate opposite the first side, and wherein the first isolation structure is spaced apart from the first side by a second distance that is less than the first distance.

2. The image sensor of claim 1, further comprising:

a metal structure disposed on the second side, wherein a first portion of the metal structure is disposed between opposing sides of the storage node.

3. The image sensor of claim 2, wherein at least a portion of the metal structure is offset from the photodetector in a lateral direction.

4. The image sensor of claim 2, wherein the opposite sides of the storage nodes are disposed between mutually opposite sidewalls of the metal structures.

5. The image sensor of claim 2, wherein a second portion of the metal structure is disposed in the first isolation structure and extends from the second side into the semiconductor substrate.

6. The image sensor of claim 2, further comprising:

a microlens disposed on the second side, wherein the metal structure is disposed between the microlens and the semiconductor substrate.

7. The image sensor of claim 6, further comprising:

a dielectric structure disposed between the microlens and the semiconductor substrate, wherein the metal structure is disposed in the dielectric structure.

8. The image sensor of claim 1, further comprising:

a first vertical transfer gate configured to selectively form a first conductive channel between the photodetector and the storage node, wherein the first vertical transfer gate extends into the semiconductor substrate from the first side, and wherein a bottom-most surface of the first vertical transfer gate is spaced apart from the first side by a fourth distance that is greater than the second distance.

9. The image sensor of claim 8, further comprising:

a second vertical transfer gate spaced apart from the first vertical transfer gate and configured to selectively form a second conductive channel between the storage node and a floating diffusion node, wherein the second vertical transfer gate extends into the semiconductor substrate from the first side, and wherein a bottom-most surface of the second vertical transfer gate is spaced apart from the first side by a fifth distance that is greater than the second distance.

10. The image sensor of claim 9, further comprising:

a second isolation structure disposed in the semiconductor substrate and separated from the first isolation structure by the storage node, wherein the second isolation structure extends into the semiconductor substrate from the second side, and wherein the first vertical transfer gate and the second vertical transfer gate are both disposed at least partially between the first isolation structure and the second isolation structure.

11. The image sensor of claim 10, further comprising:

a doped isolation region disposed in the semiconductor substrate between the first vertical transfer gate and the second vertical transfer gate, wherein the doped isolation region is disposed between the storage node and the floating diffusion node, and wherein the doped isolation region and the floating diffusion node have opposite doping types.

12. An image sensor, comprising:

a photodetector disposed in a semiconductor substrate, wherein the photodetector is spaced apart from a first side of the semiconductor substrate by a first distance;

an interlayer dielectric structure disposed on the first side of the semiconductor substrate;

a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a second distance that is greater than the first distance; and

a first vertical transfer gate disposed on the first side and configured to selectively form a first conductive channel between the photodetector and the storage node, wherein a first portion of the first vertical transfer gate extends into the semiconductor substrate from the first side by a third distance, and wherein the third distance is greater than the first distance and less than the second distance.

13. A method for forming an image sensor, comprising:

forming a photodetector in a semiconductor substrate;

forming a storage node in the semiconductor substrate and spaced apart from the photodetector;

forming a first vertical transfer gate and a second vertical transfer gate on a first side of the semiconductor substrate, wherein a portion of the first vertical transfer gate and a portion of the second vertical transfer gate extend into the semiconductor substrate from the first side;

forming an interlayer dielectric structure on the first side and over the first and second vertical transfer gates;

forming an isolation structure in the semiconductor substrate, wherein the isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate opposite the first side; and

a reflective structure is formed on the second side of the semiconductor substrate, wherein at least a portion of the reflective structure is disposed between opposing sides of the storage node.