CN112015490A - Method, apparatus and medium for programmable device implementing and testing reduced instruction set - Google Patents
Method, apparatus and medium for programmable device implementing and testing reduced instruction set Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The invention discloses a method, a device and a medium for realizing and testing a simplified instruction set by adopting a programmable device, wherein the method comprises the following steps: configuring a base instruction set in the reduced instruction set to the static portion; saving alternative instruction sets in the reduced instruction set except for a basic instruction set in a storage unit connected with the programmable device; according to the processor function to be realized by the programmable device, in the operation process: calling the basic instruction set; and configuring the replaceable instruction set required to be used in the dynamic configurable part in time to call the currently required replaceable instruction set. Under the condition that the area of the programmable device is not enough to load all instruction sets, the technical effect of completing the test of the whole instruction set without interrupting the software debugging process is achieved.
Description
Technical Field
The invention relates to the field of FPGA (field programmable gate array) testing, in particular to a method for realizing a simplified instruction set by adopting a programmable device and a method for testing the simplified instruction set by adopting the programmable device.
Background
Testing as many instruction set combinations as possible by using an FPGA (Field Programmable Gate Array) requires instantiating modules included in all instruction sets, which consumes a large amount of hardware resources and greatly increases the cost. And the test of the different instruction sets by blocks and parts cannot adopt a set of software test codes (different instruction sets are combined and compiled to have different results, if no multiplication exists, a multiplication instruction cannot be compiled and can be replaced by a plurality of addition and shift instructions). And different instruction set permutation and combination needs to be tried for many times, so that the test is sufficient, and the workload is greatly increased. Thus, in some cases, it is necessary to test the completed instruction set using a set of software.
Disclosure of Invention
In view of this, a method for implementing and testing a reduced instruction set using a programmable device is provided, which achieves the technical effect of completing the test of the entire instruction set without interrupting the software debugging process under the condition that the area of the programmable device is not enough to install all instruction sets.
The embodiment of the application provides a method for realizing a reduced instruction set by adopting a programmable device, wherein the programmable device is divided into a static part and a dynamically configurable part, and the method is characterized by comprising the following steps:
configuring a base instruction set in the reduced instruction set to the static portion;
saving alternative instruction sets in the reduced instruction set except for a basic instruction set in a storage unit connected with the programmable device;
according to the processor function to be realized by the programmable device, in the operation process:
calling the basic instruction set; and
and configuring the replaceable instruction set required to be used in the dynamic configurable part in a time-sharing manner to call the currently required replaceable instruction set.
In one embodiment, the base instruction set includes a subset of basic integer instructions; the alternative instruction set includes at least one of: a multiply instruction set, a memory atomic instruction set, a single precision floating point instruction set, a double precision floating point instruction set, a compress instruction set, and a vector instruction set.
In one embodiment, the saving the alternative instruction set other than the base instruction set in the reduced instruction set in a storage unit connected to the programmable device includes:
presetting addresses of the replaceable instruction sets in the storage unit;
configuring an access interface for accessing the address of each replaceable instruction set;
a bitstream file of the alternative instruction set is generated and saved in a corresponding address.
In one embodiment, said configuring, in a time-division manner during execution, the dynamically configurable portion with the alternative instruction sets to be used according to the processor functions to be implemented by the programmable device includes:
when the dynamically configurable portion is not configured with an instruction set, configuring the alternative instruction set directly to the dynamically configurable portion;
when the dynamically configurable portion has configured an instruction set, the configured instruction set is replaced with an alternative instruction set that is currently needed for execution.
In an embodiment, when the dynamically configurable part is configured with an instruction set, replacing the configured instruction set with an alternative instruction set required for current operation includes:
decoupling the configured instruction set;
calling a corresponding access interface to read a bit stream file required by current operation according to a replaceable instruction set required by the current operation;
and configuring the bit stream file required by the current operation to the decoupled dynamically configurable part.
In one embodiment, said configuring said alternative instruction set directly to said dynamically configurable portion when said dynamically configurable portion is not configured with an instruction set comprises:
calling a corresponding access interface to read a bit stream file required by current operation according to a replaceable instruction set required by the current operation;
and directly configuring the bit stream file required by the current operation to the dynamically configurable part.
In one embodiment, the method comprises:
generating a test code according to the function of a processor to be realized by the programmable device, wherein in the test process:
calling the basic instruction set; and
directly configuring an alternative instruction set required for current operation to the dynamically configurable portion; wherein the dynamically configurable portion of the programmable device is currently not configured with an instruction set;
when the replacement instruction set is needed, the configured instruction set is replaced by using the replacement instruction set needed by the current operation.
In one embodiment, the method further comprises:
during the replacement of the replaceable instruction set, the test is suspended;
when the replacement of the replaceable instruction set is completed, the test continues to run.
To achieve the above object, there is also provided a computer-readable storage medium, on which a program for implementing a reduced instruction set using a programmable device and a method for testing a reduced instruction set using a programmable device is stored, wherein the program for implementing the reduced instruction set using the programmable device and the method for testing the reduced instruction set using the programmable device performs any of the steps of the method described above when the program is executed by a processor.
In order to achieve the above object, an apparatus for implementing a programmable device and testing a reduced instruction set is further provided, which includes a memory, a processor, and a program stored in the memory and executable on the processor, where the program implements a method for implementing a reduced instruction set using a programmable device and a method for testing a reduced instruction set using a programmable device, and the processor implements any of the steps of the method when executing the program implementing a reduced instruction set using a programmable device and the method for testing a reduced instruction set using a programmable device.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: configuring a base instruction set in the reduced instruction set to the static portion; the frequency of use of the base instruction set is higher than the frequency of use of the alternative instruction set, and the arrangement of the base instruction set in the static portion can avoid unnecessary replacement of the instruction set. Saving alternative instruction sets in the reduced instruction set except for a basic instruction set in a storage unit connected with the programmable device; and the replaceable instruction set is stored in a storage unit connected with the programmable device, so that convenience is provided for subsequent replacement. According to the processor function to be realized by the programmable device, in the operation process: calling the basic instruction set; and configuring the replaceable instruction set required to be used in the dynamic configurable part in a time-sharing manner to call the currently required replaceable instruction set. According to the functions of the processor to be realized by the programmable device, the basic instruction set and the replaceable instruction set are called to realize the functions of the processor, and the replaceable instruction set can be replaced in the realization process. Under the condition that the area of the programmable device is not enough to load all instruction sets, the technical effect of completing the test of the whole instruction set without interrupting the software debugging process is achieved.
Drawings
FIG. 1 is a hardware architecture diagram illustrating a method for implementing a reduced instruction set using a programmable device and a method for testing a reduced instruction set using a programmable device according to an embodiment of the present disclosure;
FIG. 2 is a schematic flow chart diagram illustrating a first embodiment of a method for implementing a reduced instruction set using a programmable device according to the present application;
fig. 3 is a schematic flowchart illustrating a specific flow of step S120 in the first embodiment of the method for implementing a reduced instruction set by using a programmable device according to the present application;
fig. 4 is a schematic flowchart illustrating a specific flow of step S140 in the first embodiment of the method for implementing a reduced instruction set by using a programmable device according to the present application;
fig. 5 is a schematic flowchart illustrating a specific flow of step S142 in the first embodiment of the method for implementing a reduced instruction set by using a programmable device according to the present application;
fig. 6 is a schematic flowchart illustrating a specific flow of step S141 in the first embodiment of the method for implementing a reduced instruction set by using a programmable device according to the present application;
FIG. 7 is a flowchart illustrating a first embodiment of a method for testing a reduced instruction set using a programmable device according to the present application;
FIG. 8 is a schematic diagram illustrating an alternative instruction set replacement in the method for testing a reduced instruction set using a programmable device according to the present application;
FIG. 9 is a flowchart illustrating a second embodiment of a method for testing a reduced instruction set using a programmable device according to the present application.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The main solution of the embodiment of the invention is as follows: configuring a base instruction set in the reduced instruction set to the static portion; saving alternative instruction sets in the reduced instruction set except for a basic instruction set in a storage unit connected with the programmable device; according to the processor function to be realized by the programmable device, in the operation process: calling the basic instruction set; and configuring the replaceable instruction set required to be used in the dynamic configurable part in time to call the currently required replaceable instruction set. Under the condition that the area of the programmable device is not enough to load all instruction sets, the technical effect of completing the test of the whole instruction set without interrupting the software debugging process is achieved.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
The present application relates to a programmable device implementing and testing apparatus 010 of reduced instruction set, comprising as shown in fig. 1: at least one processor 012, memory 011.
The processor 012 may be an integrated circuit chip having signal processing capability. In implementation, the steps of the method may be performed by hardware integrated logic circuits or instructions in the form of software in the processor 012. The processor 012 may be a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 011, and the processor 012 reads the information in the memory 011 and completes the steps of the method in combination with the hardware.
It is to be understood that the memory 011 in embodiments of the present invention can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, or a flash memory. Volatile memory may be random access memory, which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory, dynamic random access memory, synchronous dynamic random access memory, double data rate synchronous dynamic random access memory, enhanced synchronous dynamic random access memory, synchronous link dynamic random access memory, and direct memory bus random access memory. The memory 011 of the systems and methods described in connection with the embodiments of the invention is intended to comprise, without being limited to, these and any other suitable types of memory.
Referring to fig. 2, fig. 2 is a first embodiment of a method for implementing a reduced instruction set using a programmable device partitioned into a static portion and a dynamically configurable portion, the method comprising:
the Programmable Device may be a Programmable Logic Device (PLD). Programmable logic devices are produced as a general purpose integrated circuit whose logic functions are determined by the programming of the device by a user. The integration level of a typical programmable logic device is high enough to meet the requirements of designing a typical digital system. Programmable logic devices are standard off-the-shelf components that can provide a wide variety of logic capabilities, characteristics, speed, and voltage characteristics to customers, and such devices can be changed at any time to perform a wide variety of different functions.
The instruction set of the static partial configuration in the programmable device is the most basic instruction set and is not replaceable. The instruction set configured by the dynamically configurable part in the programmable device is a replaceable instruction set, and the replaceable instruction set configured by the dynamically configurable part in the programmable device and the replaceable instruction set in the storage unit connected with the programmable device can be dynamically adjusted and replaced.
Step S110: configuring a base instruction set in the reduced instruction set to the static portion.
The computer instructions are instructions and commands for commanding the machine to work, the program is a series of instructions arranged in a certain sequence, and the process of executing the program is the working process of the computer. The instruction set is a set of instructions used by the CPU to calculate and control the computer system, and each new CPU is designed to define a series of instruction systems that cooperate with other hardware circuits.
Reduced Instruction Set (RISC), which has a relatively simple Instruction system, requires hardware to execute only a limited and most frequently used portion of instructions, and most complex operations are synthesized from simple instructions using sophisticated compilation techniques. RISC-V is an open Instruction Set Architecture (ISA) based on Reduced Instruction Set (RISC) principles. The reduced instruction set in the present invention is RISC-V, and may be other instruction sets that can be modularized, and is not limited herein.
The base instruction set may be the instruction set required for the basic functions of the processor to be implemented by the programmable device. In the present invention, the base instruction set may be the only mandatory implementation of the instruction set portion, the basic integer instruction subset denoted by the I-letter, i.e., RV-I.
Step S120: and saving the replaceable instruction set except the basic instruction set in the simplified instruction set in a storage unit connected with the programmable device.
The alternative instruction set is an instruction set except the basic instruction set, and may be multiple, and the positions are not in sequence.
The memory cell has a large number of memory cells in the memory, which are divided into groups by the same bit, and all the memory cells in a group are read or written simultaneously, and such a group of memory cells is called a memory cell. A memory location can typically hold one byte; the memory unit is a basic unit of the CPU accessing the memory.
Step S130: according to the processor function to be realized by the programmable device, in the operation process: the base instruction set is invoked.
The processor functions include the following four:
1. and (3) sequence control: this refers to the execution order of the instructions in the control program. The instructions in the program are in strict sequence, and the instructions must be executed in the sequence specified by the program to ensure the working correctness of the computer.
2. And (3) operation control: the function of an instruction is often performed by a component in a computer performing a series of operations. The CPU generates corresponding operation control signals according to the functions of the instructions and sends the operation control signals to corresponding parts, so that the parts are controlled to act according to the requirements of the instructions.
3. Time control: time control is the timing of various operations. During the execution of an instruction, at what time and what operation should be done is strictly controlled. Only then can the computer automatically operate in a systematic manner.
4. Data processing: i.e., arithmetic and logical operations on data, or other information processing.
Step S140: and configuring the replaceable instruction set required to be used in the dynamic configurable part in a time-sharing manner to call the currently required replaceable instruction set.
Calling a basic instruction set and a replaceable instruction set in real time according to the functional requirements of the processor, and directly calling when the required replaceable instruction set is configured on the dynamically configurable part; and when the required replaceable instruction set is not configured in the dynamically configurable part, executing the replacement operation and calling.
The beneficial effects present in the above embodiments: configuring a base instruction set in the reduced instruction set to the static portion; the frequency of use of the base instruction set is higher than the frequency of use of the alternative instruction set, and the arrangement of the base instruction set in the static portion can avoid unnecessary replacement of the instruction set. Saving alternative instruction sets in the reduced instruction set except for a basic instruction set in a storage unit connected with the programmable device; and the replaceable instruction set is stored in a storage unit connected with the programmable device, so that convenience is provided for subsequent replacement. According to the processor function to be realized by the programmable device, in the operation process: calling the basic instruction set; and configuring the replaceable instruction set required to be used in the dynamic configurable part in a time-sharing manner to call the currently required replaceable instruction set. According to the functions of the processor to be realized by the programmable device, the basic instruction set and the replaceable instruction set are called to realize the functions of the processor, and the replaceable instruction set can be replaced in the realization process. Under the condition that the area of the programmable device is not enough to load all instruction sets, the technical effect of completing the test of the whole instruction set without interrupting the software debugging process is achieved.
In one embodiment, the base instruction set includes a subset of basic integer instructions; the alternative instruction set includes at least one of: a multiply instruction set, a memory atomic instruction set, a single precision floating point instruction set, a double precision floating point instruction set, a compress instruction set, and a vector instruction set.
The replaceable instruction is stripped from the system, and the stripped part mainly comprises an instruction decoding table, an arithmetic execution unit and the like.
In the embodiment, the instruction set of RISC-V is organized in a modular manner, and each module is represented by an english alphabet. RV-M is a multiplication instruction set, an RV-A memory atom instruction set, an RV-F single-precision floating point instruction set, an RV-D double-precision floating point instruction set, an RV-C compression instruction set and an RV-V vector instruction set.
The modular way of the replaceable instruction enables the reduced instruction set to be matched with the dynamically reconfigurable function of the programmable device, and data support is provided for realizing the method in the invention.
Referring to fig. 3, fig. 3 is a specific flowchart of step S120 in a first embodiment of a method for implementing a reduced instruction set by using a programmable device, where saving an alternative instruction set in the reduced instruction set, except for a basic instruction set, in a storage unit connected to the programmable device includes:
step S121: the addresses of the respective alternative instruction sets in the memory location are preset.
The addresses of the respective replaceable instruction sets in the memory locations of all the replaceable instruction sets are set in advance. Wherein the memory unit may be FLASH based.
Memory addresses are typically represented as hexadecimal numbers, with each memory address holding a set of binary (or hexadecimal) numbers, commonly referred to as the contents of the address. It is noted that the address of the memory cell and the content in the address are both different. The former is the number of the memory cell, indicating a location in the memory, and the latter indicates the data stored in this location. Just as one is the room number and one is the person who lives in the room.
Step S122: an access interface is configured to access the address of each alternative instruction set.
The corresponding access interface is configured such that during the replacement process the address at which the replaceable instruction set is located is accessed.
Step S123: a bitstream file of the alternative instruction set is generated and saved in a corresponding address.
A bit is a bit in a binary digit, and a unit of measurement of the amount of information is the minimum unit of the amount of information. The bitstream file may be an underlying file that converts the alternative instruction set to contain only bits.
The beneficial effects present in the above embodiments: the bit stream file generated by the replaceable instruction set is stored in the preset address of the storage unit, so that the speed of replacing the replaceable instruction set is improved.
Referring to fig. 4, fig. 4 is a specific flowchart of step S140 in a first embodiment of a method for implementing a reduced instruction set by using a programmable device, where the configuring, in a time-sharing manner during an operation process, an alternative instruction set to be used in the dynamically configurable portion according to a processor function to be implemented by the programmable device includes:
step S141: when the dynamically configurable portion is not configured with an instruction set, the alternative instruction set is configured directly to the dynamically configurable portion.
According to the processor function to be realized by the programmable device, when one or more of the alternative instruction sets are needed to be used, whether the dynamically configurable part in the programmable device is configured with the alternative instruction set or not is monitored in real time, and if the instruction set is not configured, the needed alternative instruction set can be directly configured on the dynamically configurable part.
Step S142: when the dynamically configurable portion has configured an instruction set, the configured instruction set is replaced with an alternative instruction set that is currently needed for execution.
According to the processor function to be realized by the programmable device, when one or more of the replaceable instruction sets are needed to be used, whether the replaceable instruction set is configured in the dynamically configurable part of the programmable device is monitored in real time, and if the instruction set is configured, the configured instruction set can be replaced by the needed instruction set.
The beneficial effects present in the above embodiments: the operation steps corresponding to the two conditions that the instruction set is not configured by the dynamically configurable part and the instruction set is configured by the dynamically configurable part are supplemented, and the smooth operation of the functions of the processor is ensured.
Referring to fig. 5, fig. 5 is a specific flowchart of step S142 in the first embodiment of the method for implementing a reduced instruction set by using a programmable device, where when the dynamically configurable partial configured instruction set is used, replacing the configured instruction set with an alternative instruction set required for current operation includes:
step S1421: and performing decoupling processing on the configured instruction set.
Coupling refers to the phenomenon whereby two or more systems or two forms of motion interact with each other through interactions to join them together. The coupling between the modules of the software can be realized, and the coupling between the software and the hardware can also be realized. Coupling is a measure of the interrelationship between the various modules in a program structure. It depends on the complexity of the interface between the various modules, the way the modules are called, and which information passes through the interface. In the present invention, the coupling between hardware and software.
The decoupling is to reduce the degree of association between software and hardware, and in the invention, the configured replaceable instruction is separated from the dynamically configurable part, and a blank position is reserved for the replaceable instruction set required by the current operation.
Step S1422: and calling the corresponding access interface to read the bit stream file required by the current operation according to the replaceable instruction set required by the current operation.
And calling a corresponding access interface (which can be selected to be accessed through a bus designated address) according to the alternative instruction set required by the current operation, and reading the bit stream file required by the current operation.
Step S1423: and configuring the bit stream file required by the current operation to the decoupled dynamically configurable part.
And configuring the currently required bit stream file to the blank position of the decoupled dynamically configurable part.
The beneficial effects present in the above embodiments: when the dynamically configurable part of the instruction sets are configured, the configured instruction sets are replaced by the replaceable instruction sets required by current operation, so that the technical effect of completing the test of the whole instruction set without interrupting the software debugging process is achieved under the condition that the area of the programmable device is not enough to load all the instruction sets.
Referring to fig. 6, fig. 6 is a specific flowchart of step S141 in the first embodiment of the method for implementing a reduced instruction set by using a programmable device, where when the dynamically configurable portion is not configured with an instruction set, directly configuring the replaceable instruction set in the dynamically configurable portion includes:
step S1411: and calling the corresponding access interface to read the bit stream file required by the current operation according to the replaceable instruction set required by the current operation.
And calling a corresponding access interface (which can be selected to be accessed through a bus designated address) according to the alternative instruction set required by the current operation, and reading the bit stream file required by the current operation.
Step S1412: and directly configuring the bit stream file required by the current operation to the dynamically configurable part.
And directly configuring the bit stream file required by the current operation to the blank position of the dynamic configurable part.
The beneficial effects present in the above embodiments: the method and the device have the advantages that when the instruction set is not configured in the dynamic configuration part, the replaceable instruction set is directly configured in the specific execution step of the dynamic configuration part, and smooth operation of the functions of the processor is guaranteed.
Referring to FIG. 7, FIG. 7 is a first embodiment of a method for testing a reduced instruction set using a programmable device, the method comprising:
step S110': generating a test code according to the function of a processor to be realized by the programmable device, wherein in the test process: the base instruction set is invoked.
Test description is a process used to facilitate the verification of the correctness, integrity, security, and quality of software. Testing is a process of auditing or comparing between actual and expected outputs. The classical definition of a test is: the process of operating a program under specified conditions to discover program errors, to measure software quality, and to evaluate whether it meets design requirements.
The test code may be code generated by the programmable device to test the functionality of the processor. In the testing process, each testing point is functionally tested, and a basic instruction set is required to be called.
Step S120': directly configuring an alternative instruction set required for current operation to the dynamically configurable portion; wherein the dynamically configurable portion of the programmable device is not currently configured with an instruction set.
When the dynamically configurable part of the programmable device is not configured with the instruction set currently, the dynamically configurable part is directly configured with the blank position of the dynamically configurable part according to the replaceable instruction set required by the current operation.
Step S130': when the replacement instruction set is needed, the configured instruction set is replaced by using the replacement instruction set needed by the current operation.
When the dynamically configurable portion of the programmable device currently has configured an instruction set, the configured instruction set is replaced with an alternate instruction set that is currently needed for execution.
In the above embodiment, as shown in fig. 8, a schematic diagram of replacing the replaceable instruction set in the method for testing the simplified instruction set using the programmable device is shown, and the replacement step of the replaceable instruction set in the specific implementation steps of the method for testing the simplified instruction set using the programmable device ensures that the technical effect of completing the test of the entire instruction set without interrupting the software debugging process is achieved under the condition that the area of the programmable device is not enough to load all instruction sets.
Referring to fig. 9, fig. 9 is a second embodiment of a method for testing a reduced instruction set using a programmable device, further including:
step S210': generating a test code according to the function of a processor to be realized by the programmable device, wherein in the test process: the base instruction set is invoked.
Step S220': directly configuring an alternative instruction set required for current operation to the dynamically configurable portion; wherein the dynamically configurable portion of the programmable device is not currently configured with an instruction set.
Step S230': when the replacement instruction set is needed, the configured instruction set is replaced by using the replacement instruction set needed by the current operation.
Step S240': during the replacement of the alternative instruction set, the test will be suspended.
In the process of replacing the replaceable instruction set, the testing process is suspended or suspended, so that the testing process is more accurate, and each testing point in the testing process can be ensured to be tested smoothly. The test is suspended without affecting the replacement process of the replaceable instruction set.
Step S250': when the replacement of the replaceable instruction set is completed, the test continues to run.
When the replacement of the replaceable instruction set is complete, the test will continue.
Compared with the first embodiment, the second embodiment includes step S240 'and step S250', and other steps are not described again.
The beneficial effects present in the above embodiments: and the method for testing the simplified instruction set by adopting the programmable device suspends the test in the replacement process of the replaceable instruction set, and the test continues to run after the replacement process of the replaceable instruction set is completed. The replacement process of the replaceable instruction set is guaranteed not to be affected mutually, and therefore smooth testing is guaranteed.
The invention also provides a computer readable storage medium, wherein the computer readable storage medium stores a program of a method for realizing the reduced instruction set by using a programmable device and a method for testing the reduced instruction set by using the programmable device, and the method for realizing the reduced instruction set by using the programmable device and the method for testing the reduced instruction set by using the programmable device realize the steps of any one of the methods when the program is executed by a processor.
The invention also provides equipment for realizing the programmable device and testing the reduced instruction set, which comprises a memory, a processor, a method for realizing the reduced instruction set by adopting the programmable device and a program for testing the reduced instruction set by adopting the programmable device, wherein the method is stored in the memory and can be operated on the processor, and the steps of any one of the methods are realized when the processor executes the method for realizing the reduced instruction set by adopting the programmable device and the program for testing the reduced instruction set by adopting the programmable device.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method for implementing a reduced instruction set using a programmable device partitioned into a static portion and a dynamically configurable portion, the method comprising:
configuring a base instruction set in the reduced instruction set to the static portion;
saving alternative instruction sets in the reduced instruction set except for a basic instruction set in a storage unit connected with the programmable device;
according to the processor function to be realized by the programmable device, in the operation process:
calling the basic instruction set; and
and configuring the replaceable instruction set required to be used in the dynamic configurable part in a time-sharing manner to call the currently required replaceable instruction set.
2. The method of implementing a reduced instruction set using a programmable device of claim 1, wherein the base instruction set includes a subset of basic integer instructions; the alternative instruction set includes at least one of: a multiply instruction set, a memory atomic instruction set, a single precision floating point instruction set, a double precision floating point instruction set, a compress instruction set, and a vector instruction set.
3. The method of claim 1, wherein said storing an alternate instruction set in the reduced instruction set, other than a base instruction set, in a memory unit coupled to the programmable device comprises:
presetting addresses of the replaceable instruction sets in the storage unit;
configuring an access interface for accessing the address of each replaceable instruction set;
a bitstream file of the alternative instruction set is generated and saved in a corresponding address.
4. A method for implementing a reduced instruction set using a programmable device as defined in claim 3, wherein configuring the dynamically configurable portion with the alternative instruction sets to be used in a time-division manner during execution based on the processor functions to be implemented by the programmable device comprises:
when the dynamically configurable portion is not configured with an instruction set, configuring the alternative instruction set directly to the dynamically configurable portion;
when the dynamically configurable portion has configured an instruction set, the configured instruction set is replaced with an alternative instruction set that is currently needed for execution.
5. The method of claim 4 for implementing a reduced instruction set using a programmable device, wherein said replacing a configured instruction set with an alternate instruction set currently needed for execution when said dynamically configurable partially configured instruction set is present, comprises:
decoupling the configured instruction set;
calling a corresponding access interface to read a bit stream file required by current operation according to a replaceable instruction set required by the current operation;
and configuring the bit stream file required by the current operation to the decoupled dynamically configurable part.
6. The method of claim 4 for implementing a reduced instruction set using a programmable device, wherein said directly configuring the alternative instruction set to the dynamically configurable portion when the dynamically configurable portion is not configured with an instruction set comprises:
calling a corresponding access interface to read a bit stream file required by current operation according to a replaceable instruction set required by the current operation;
and directly configuring the bit stream file required by the current operation to the dynamically configurable part.
7. A method for testing a reduced instruction set using a programmable device, the method comprising:
generating a test code according to the function of a processor to be realized by the programmable device, wherein in the test process:
calling a basic instruction set; and
directly configuring an alternative instruction set required by current operation to the dynamically configurable part; wherein the dynamically configurable portion of the programmable device is not currently configured with an instruction set;
when a replacement instruction set is needed, the configured instruction set is replaced with the replacement instruction set needed for current operation.
8. The method for testing a reduced instruction set using a programmable device of claim 7, further comprising:
during the replacement of the replaceable instruction set, the test is suspended;
when the replacement of the replaceable instruction set is completed, the test continues to run.
9. A computer-readable storage medium, having stored thereon a program for implementing a method for compacted instruction set using a programmable device and a method for testing a compacted instruction set using a programmable device, wherein the program for implementing a method for compacted instruction set using a programmable device and a method for testing a compacted instruction set using a programmable device implements the steps of the method of any of claims 1 to 8 when executed by a processor.
10. A programmable device implementing and testing reduced instruction set apparatus, comprising a memory, a processor, and a program stored on the memory and executable on the processor for implementing and testing reduced instruction set using a programmable device, wherein the processor implements the steps of the method of any one of claims 1 to 8 when executing the program for implementing and testing reduced instruction set using a programmable device.
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