CN111987062A - Semiconductor packaging structure and preparation method thereof - Google Patents
Semiconductor packaging structure and preparation method thereof Download PDFInfo
- Publication number
- CN111987062A CN111987062A CN201910426712.2A CN201910426712A CN111987062A CN 111987062 A CN111987062 A CN 111987062A CN 201910426712 A CN201910426712 A CN 201910426712A CN 111987062 A CN111987062 A CN 111987062A
- Authority
- CN
- China
- Prior art keywords
- layer
- glass substrate
- antenna
- metal
- metal connecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000011521 glass Substances 0.000 claims abstract description 144
- 239000000758 substrate Substances 0.000 claims abstract description 137
- 229910052751 metal Inorganic materials 0.000 claims abstract description 136
- 239000002184 metal Substances 0.000 claims abstract description 136
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 321
- 238000000034 method Methods 0.000 claims description 44
- 239000011241 protective layer Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 12
- 238000000465 moulding Methods 0.000 claims description 2
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 12
- 230000009286 beneficial effect Effects 0.000 abstract description 10
- 239000000463 material Substances 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000012858 packaging process Methods 0.000 description 6
- 238000010329 laser etching Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229920001296 polysiloxane Polymers 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 238000000748 compression moulding Methods 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000010295 mobile communication Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005108 dry cleaning Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor packaging structure and a preparation method thereof. The structure comprises a rewiring layer, wherein the rewiring layer comprises a dielectric layer and a metal connecting layer; a first glass substrate on a second surface of the rewiring layer; the metal connecting column penetrates through the first glass substrate and is electrically connected with the metal connecting layer; the first antenna layer is electrically connected with the metal connecting column; a second glass substrate covering the first antenna layer; the second antenna layer is positioned on the surface of the second glass substrate; the metal bump is electrically connected with the metal connecting layer; and the chip is electrically connected with the metal connecting layer. The semiconductor packaging structure of the invention adopts the rewiring layer and the multilayer glass substrate to realize the integration of two or more antenna metal layers, which is beneficial to reducing the volume of the packaging structure, improving the integration level of devices, simultaneously reducing the cost and improving the performance of the packaging structure. The preparation method of the invention is beneficial to simplifying the preparation process and reducing the production cost.
Description
Technical Field
The invention belongs to the field of semiconductor packaging, and particularly relates to a semiconductor packaging structure and a preparation method thereof.
Background
With the development of economy and the advancement of science and technology, various high-tech electronic products have been developed, which are very convenient and enrich people's lives, and among them, the development of various portable mobile communication terminals represented by mobile phones and tablet computers (PAD) is particularly remarkable.
An antenna structure is generally built in an existing portable mobile communication terminal for communication functions, such as voice and video connection, surfing the internet, and the like. At present, the antenna is directly manufactured on the surface of a circuit board in a common method for embedding the antenna, but the method has poor device integration because the antenna needs to occupy extra circuit board area, and further miniaturization of the mobile communication terminal is restricted. Meanwhile, as the number of electronic circuits on the circuit board is large, electromagnetic interference exists between the antenna and other circuits, and even the risk of short circuit between the antenna and other metal circuits exists.
Although the technology of packaging the antenna and the chip together has appeared in the field of packaging, the packaging process needs to be carried out by means of a carrier, and the process is complex and the cost is high. In addition, most of the existing antenna packages are single-layer structures, and the antenna efficiency is low, so that the requirement for increasing the performance of the antenna is not met enough.
In view of the above problems, it is desirable to provide a semiconductor package structure with high integration and high efficiency and a method for fabricating the same.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same, which are used to solve the problems of low integration, high package cost, low antenna efficiency, and the like of the antenna package structure in the prior art.
To achieve the above and other related objects, the present invention provides a semiconductor package structure, comprising: the rewiring layer is provided with a first surface and a second surface opposite to the first surface and comprises a dielectric layer and a metal connecting layer positioned in the dielectric layer; a first glass substrate on a second surface of the rewiring layer; the metal connecting column penetrates through the first glass substrate and is electrically connected with the metal connecting layer; the first antenna layer is positioned on the surface, away from the rewiring layer, of the first glass substrate, and the first antenna layer is electrically connected with the metal connecting column; a second glass substrate covering the first antenna layer; the second antenna layer is positioned on the surface, away from the first antenna layer, of the second glass substrate; the metal bump is positioned on the first surface of the rewiring layer and is electrically connected with the metal connecting layer; and the chip is positioned on the first surface of the rewiring layer and is electrically connected with the metal connecting layer.
Optionally, the first antenna layer includes a plurality of spaced apart antennas, and the semiconductor package structure further includes a protective layer located between the antennas.
Optionally, the second antenna layer includes a plurality of antennas distributed at intervals, the number of antennas included in the first antenna layer is the same as that of antennas included in the second antenna layer, and the antennas of the first antenna layer and the antennas of the second antenna layer are arranged in a one-to-one correspondence manner.
Optionally, the semiconductor package structure further includes an underfill layer filled between the chip and the redistribution layer.
Optionally, the first antenna layer further has an alignment mark thereon, and the first antenna layer and the second antenna layer are aligned by the alignment mark.
The invention also provides a preparation method of the semiconductor packaging structure, which comprises the following steps:
1) providing a first glass substrate, wherein the first glass substrate is provided with a first surface and a second surface opposite to the first surface, and a rewiring layer is formed on the first surface of the first glass substrate and comprises a dielectric layer and a metal connecting layer positioned in the dielectric layer;
2) forming a metal connecting column, wherein the metal connecting column penetrates through the first glass substrate and is exposed on the second surface of the first glass substrate, and the metal connecting column is electrically connected with the metal connecting layer;
3) Forming a first antenna layer on the second surface of the first glass substrate, wherein the first antenna layer is electrically connected with the metal connecting column;
4) providing a second glass substrate, wherein the second glass substrate is provided with a first surface and a second surface opposite to the first surface, and a second antenna layer is formed on the first surface of the second glass substrate;
5) attaching the first glass substrate with the first antenna layer and the second glass substrate with the second antenna layer to obtain an attachment sheet, wherein the surface of the first antenna layer and the second surface of the second glass substrate are attachment surfaces;
6) bonding the surface, away from the first glass substrate, of the rewiring layer of the attaching sheet with a chip, wherein the chip is electrically connected with the metal connecting layer;
7) and forming a metal bump on the surface of the rewiring layer, which is far away from the first glass substrate, wherein the metal bump is electrically connected with the metal connecting layer.
Optionally, the preparation method further comprises a step of curing and molding the first glass substrate and the second glass substrate by using an ultraviolet curing or thermosetting process after the first glass substrate and the second glass substrate are attached.
Optionally, the preparation method further includes a step of forming an underfill layer filled between the chip and the rewiring layer after bonding the chip and the rewiring layer.
Optionally, the step of forming the first antenna layer on the second surface of the first glass substrate includes:
forming a first antenna metal layer on the second surface of the first glass substrate;
etching the first antenna metal layer to separate the first antenna metal layer into a plurality of antennas distributed at intervals;
and forming a protective layer in the gap between the antennas.
Optionally, the manufacturing method further includes a step of forming an alignment mark on the first antenna layer, and the alignment is achieved through the alignment mark in the process of attaching the first glass substrate to the second glass substrate.
As described above, the semiconductor package structure of the present invention adopts the redistribution layer and the multilayer glass substrate to realize the integration of two or more antenna metal layers, which is beneficial to reducing the volume of the package structure, improving the integration level of devices, simultaneously reducing the cost, and improving the performance of the package structure. By adopting the preparation method, a carrier is not required to be used for transferring in the packaging process, the alignment in the packaging process is simpler, the preparation process is facilitated to be simplified, and the production cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor package structure according to a first embodiment of the invention.
Fig. 2 to 4 are schematic top views illustrating a first antenna layer in a semiconductor package structure according to a first embodiment of the invention.
Fig. 5 is a schematic structural diagram of a semiconductor package structure according to a second embodiment of the invention.
Fig. 6 to 8 are schematic top view diagrams illustrating a first antenna layer in a semiconductor package structure according to a second embodiment of the invention.
Fig. 9 is a flowchart illustrating a method for fabricating a semiconductor package structure according to a third embodiment of the invention.
Fig. 10 to 12 are schematic structural views showing steps of the manufacturing method according to fig. 9.
Description of the element reference numerals
11 rewiring layer
111 dielectric layer
112 metal connection layer
12 first glass substrate
13 metal connecting column
14 first antenna layer
141 antenna
15 second glass substrate
16 second antenna layer
17 metal bump
18 chip
19 protective layer
20 underfill layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 12. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, the present invention provides a semiconductor package structure, which includes: the rewiring layer 11 is provided with a first surface and a second surface opposite to the first surface, and the rewiring layer 11 comprises a dielectric layer 111 and a metal connecting layer 112 positioned in the dielectric layer 111; a first glass substrate 12 on a second surface of the rewiring layer 11; a metal connection post 13 penetrating through the first glass substrate 12 and electrically connected to the metal connection layer 112; a first antenna layer 14 located on the surface of the first glass substrate 12 away from the redistribution layer 11, wherein the first antenna layer 14 is electrically connected to the metal connection stud 13; a second glass substrate 15 covering the first antenna layer 14; a second antenna layer 16 located on the surface of the second glass substrate 15 away from the first antenna layer 14; a metal bump 17 located on the first surface of the redistribution layer 11 and electrically connected to the metal connection layer 112; and a chip 18 located on the first surface of the redistribution layer 11 and electrically connected to the metal connection layer 112. The semiconductor packaging structure of the invention adopts the rewiring layer 11 and the multilayer glass substrate to realize the integration of two or more antenna metal layers, which is beneficial to reducing the volume of the packaging structure, improving the integration level of devices, simultaneously being beneficial to reducing the cost and being beneficial to improving the performance of the packaging structure.
The rewiring layer 11 includes a dielectric layer 111 and a single-layer metal connection layer 112 located in the dielectric layer 111, and the metal connection layer 112 is located in the dielectric layer 111 to prevent the metal connection layer 112 from being oxidized and polluted to cause resistance increase of the metal connection layer to cause performance reduction of a device or even complete failure of the device. The metal connection layer 112 may be partially exposed from the surface of the dielectric layer 111 to facilitate electrical connection with other structures. By way of example, the material of the dielectric layer 111 includes, but is not limited to, one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the method for forming the dielectric layer 111 includes, but is not limited to, a chemical vapor deposition method or a physical vapor deposition method; the method for forming the metal connection layer 112 includes, but is not limited to, a physical vapor deposition method or an electroplating method, such as forming a pattern corresponding to the metal connection layer 112 in the dielectric layer 111 by a photolithography etching method, filling metal by the aforementioned method to form the metal connection layer 112, and then forming a dielectric material covering the metal connection layer 112; the material of the metal connection layer 112 includes, but is not limited to, one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. In other examples, the number of layers of the dielectric layer 111 and the metal connection layer 112 may be 3 or more, but it is necessary to ensure electrical connection between the multiple metal connection layers 112.
The first glass substrate 12 and the second glass substrate 15 may be made of inorganic glass such as silicate, or organic glass, and it is important that the glass is transparent or light-permeable. The thickness of the first glass substrate 12 may be the same as or different from the thickness of the second glass substrate 15. In this embodiment, as an example, the thickness of the first glass substrate 12 is greater than that of the second glass substrate 15, and the thickness of the first glass substrate 12 is set to be relatively thick, which helps to avoid electromagnetic interference of other metal wire layers including the metal connection layer 112 on the first antenna layer 14, and helps to avoid short circuit.
By way of example, the material of the metal connection stud 13 includes, but is not limited to, one or more of gold, silver, aluminum, and copper, and a bonding pad (not labeled) formed by metal such as nickel and having a larger cross section than the metal connection stud 13 may be formed at the connection position of the metal connection stud 13 and the metal connection layer 112 to ensure sufficient electrical connection between the metal connection stud 13 and the metal connection layer 112.
The material of the first antenna layer 14 includes, but is not limited to, one or more of copper, aluminum, and silver, for example, the first antenna layer 14 may be a composite metal layer with a copper metal layer plated with a silver layer to improve the performance of the first antenna layer 14.
As shown in fig. 2, in an example, the first antenna layer 14 includes a plurality of spaced apart antennas 141, and the semiconductor package structure further includes a protective layer 19 located between the antennas 141, where the protective layer 19 includes, but is not limited to, one or more of polyimide, silicone, and epoxy. The plurality of antennas 141 may be uniformly spaced or non-uniformly spaced; the structures of the antennas 141 may be completely the same or different from each other, and in this embodiment, it is preferable that the structures and the sizes of the antennas 141 are completely the same and are arranged at uniform intervals, so that the transmission frequencies and the intensities of the antennas 141 are the same, which is beneficial to improving the overall performance of the semiconductor package structure.
As shown in fig. 3, in another example, the antenna 141 of the first antenna layer 14 has a spiral shape, which is beneficial to enhance the radiation coupling of the first antenna layer 14 and improve the performance of the semiconductor package device.
As shown in fig. 4, in another example, the first antenna layer 14 may include one or more circular antennas 141, which is advantageous for increasing the radiation direction of the first antenna layer 14 and improving the performance of the semiconductor package device.
Of course, the specific structure of the first antenna layer 14 may have other options according to different needs, and is not limited in this embodiment. In the present embodiment, the first antenna layer 14 is formed on the surface of the first glass substrate 12, in order to prevent the first antenna layer 14 from being contaminated or oxidized by the external environment, a gap between the periphery of the first antenna layer 14 and the antenna 141 is usually protected by the protective layer 19, the first antenna layer 14 and the protective layer 19 are illustrated in fig. 2 to 4, and the first antenna layer 14 is grounded through a grounding wire (not shown).
As an example, the second antenna layer 16 includes a plurality of antennas 141 distributed at intervals, the number of the antennas 141 included in the first antenna layer 14 and the second antenna layer 16 is the same, and the antennas 141 of the first antenna layer 14 and the antennas 141 of the second antenna layer 16 are arranged in a one-to-one correspondence manner, that is, the antennas 141 of the second antenna layer 16 and the antennas 141 of the first antenna layer 14 are identical in structure, size and arrangement direction, and this arrangement of the structure helps to enhance the antenna field strength, improve the antenna gain, and improve the performance of the semiconductor package structure. Of course, in other examples, the structures, sizes and arrangement directions of the second antenna layer 16 and the first antenna layer 14 may not be completely the same or different according to different needs, for example, the arrangement directions of the antennas 141 of the first antenna layer 14 and the antennas 141 of the second antenna layer 16 may form an included angle of 45 °, and the present embodiment is not limited thereto. The second antenna layer 16 can be electrically connected to the first antenna layer 14, or can be electrically connected to other structures by disposing metal leads (not shown) on the surface thereof, so that there is no need to provide etching vias and filling metal to form conductive metal pillars, which helps to simplify the manufacturing process. Of course, the structure of the antenna 141 may be three or more layers in addition to a two-layer structure, the uppermost antenna layer is preferably provided with a metal lead on its surface for electrical leading, and the lower antenna layer is preferably electrically connected to the lower structure in turn by forming a structure similar to the metal connecting column 13, and each antenna layer is usually grounded through a grounding structure (not shown). The arrangement of the antenna layers helps to reduce the size of the packaging structure, improve the integration level of the device, simultaneously help to reduce the cost and is beneficial to improving the performance of the device.
As an example, the semiconductor package structure further includes an underfill layer 20 filled between the chip 18 and the redistribution layer 11, and the underfill layer 20 may improve the bonding strength between the chip 18 and the redistribution layer 11 and protect the redistribution layer 11. The material of the underfill layer 20 includes, but is not limited to, one or more of polyimide, silicone, and epoxy, and the method for forming the underfill layer 20 includes, but is not limited to, one or more of inkjet, dispensing, compression molding, transfer molding, liquid encapsulation, vacuum lamination, and spin coating.
By way of example, the metal bump 17 includes but is not limited to one or more of a tin solder bump, a silver solder bump and a gold-tin alloy solder bump, and a bonding pad (not labeled) made of nickel material, for example, may be disposed at the junction of the metal bump 17 and the metal connection layer 112 to ensure sufficient electrical connection between the metal bump 17 and the metal connection layer 112. The lower surfaces of the metal bumps 17 preferably protrude outward compared to the lower surface of the chip 18 to protect the chip 18 (as shown in fig. 1, the lower surfaces of the two are not at the same level).
As an example, an alignment mark (not shown) is further formed on the first antenna layer 14, and the first antenna layer 14 and the second antenna layer 16 are aligned by the alignment mark. The alignment mark can be one or more of a circle, a triangle, a cross, a Chinese character 'mi' or any other structure, and the number of the alignment mark can be one or more. The alignment mark is preferably located at the edge of the first antenna layer 14, and the material of the alignment mark is preferably the same as that of the antenna 141 of the first antenna layer 14, that is, the alignment mark is made of a metal material, and the alignment mark is preferably formed together with the antenna 141, which helps to simplify the manufacturing process. Since the first glass substrate 12 and the second glass substrate 15 are both made of transparent materials, alignment can be achieved by means of the alignment marks in the packaging process, and production cost is reduced.
Example two
As shown in fig. 5, the present embodiment provides a semiconductor package structure with another structure, and the semiconductor package structure of the present embodiment is different from the semiconductor package structure of the first embodiment in that: in the first embodiment, the first antenna layer 14 is formed on the upper portion of the first glass substrate 12, the upper surfaces of the two are not on the same horizontal plane, and the gap existing between the antennas 141 of the first antenna layer 14 is filled with the protective layer 19 to protect the first antenna layer 14; in this embodiment, since the grooves (not shown) are formed in the first glass substrate 12 and the first antenna layer 14 is formed in the grooves, the first glass substrate 12 between the grooves in this embodiment can well protect the first antenna layer 14 without making the protective layer 19, and thus, when viewed from the top view of the first antenna layer 14 illustrated in fig. 6 to 7, the first antenna layer 14 is exposed from the surface of the first glass substrate 12, that is, the first antenna layer 14 is embedded in the first glass substrate 12. In one example, the trenches have different depths, that is, the bottom surfaces of the trenches are uneven, for example, the bottoms of the trenches gradually deepen from the sidewalls of the bottoms of the trenches to the centers of the trenches to form corrugations, which facilitates the close contact between the first antenna layer 14 and the first glass substrate, facilitates the close contact between the first antenna layer 14 and the first glass substrate 12 and the stress release of the first antenna layer 14, and facilitates the performance improvement of the semiconductor package device. In other examples, the second antenna layer 16 may also adopt such an embedded structure. This design facilitates simplification of the structure and reduction of packaging cost. In addition, the upper surface of the first antenna layer 14 is preferably not higher than the upper surface of the first glass substrate 12, for example, the upper surfaces of the two may be flush with each other or the upper surface of the first antenna layer 14 is lower than the upper surface of the first glass substrate 12 (i.e., the maximum thickness of the first antenna layer 14 is smaller than the maximum depth of the groove), and the height difference portion between the two may be filled with glue to fix the first antenna layer 14, and at the same time, the second glass substrate 15 and the first glass substrate 12 can be closely attached, which helps to improve the quality and performance of the package structure. In addition, other parts of the semiconductor package structure of the present embodiment are the same as those of the semiconductor package structure of the first embodiment, and specific reference is made to the first embodiment, which is not repeated for brevity.
EXAMPLE III
As shown in fig. 9, the present invention further provides a method for manufacturing a semiconductor package structure, which can be used to manufacture the semiconductor package structure in the first embodiment, so that the description of the related structure in the first embodiment is fully applicable to the present embodiment, and for the sake of brevity, the same contents in the first embodiment are not repeated as much as possible, and refer to the first embodiment.
As an example, the preparation method comprises the steps of:
s1: providing a first glass substrate 12, wherein the first glass substrate 12 has a first surface and a second surface opposite to the first surface, and a redistribution layer 11 is formed on the first surface of the first glass substrate 12, wherein the redistribution layer 11 includes a dielectric layer 111 and a metal connection layer 112 located in the dielectric layer 111;
s2: forming a metal connection post 13, wherein the metal connection post 13 penetrates through the first glass substrate 12 and is exposed on the second surface of the first glass substrate 12, and the metal connection post 13 is electrically connected with the metal connection layer 112;
s3: forming a first antenna layer 14 on the second surface of the first glass substrate 12, wherein the first antenna layer 14 is electrically connected to the metal connection stud 13, and the obtained structure is as shown in fig. 10;
S4: providing a second glass substrate 15, wherein the second glass has a first surface and a second surface opposite to the first surface, and forming a second antenna layer 16 on the first surface of the second glass substrate 15, and the obtained structure is shown in fig. 11;
s5: bonding the first glass substrate 12 on which the first antenna layer 14 is formed and the second glass substrate 15 on which the second antenna layer 16 is formed to obtain a bonding sheet, wherein a surface on which the first antenna layer 14 is located and a second surface of the second glass substrate 15 are bonding surfaces, and the obtained structure is as shown in fig. 12;
s6: bonding the surface of the redistribution layer 11 of the bonding sheet away from the first glass substrate 12 with a chip 18, wherein the chip 18 is electrically connected with the metal connection layer 112;
s7: forming a metal bump 17 on the surface of the redistribution layer 11 away from the first glass substrate 12, wherein the metal bump 17 is electrically connected to the metal connection layer 112.
As an example, before forming the redistribution layer 11, a step of cleaning the first glass substrate 12 is further included to improve the cleanliness of the first glass substrate 12, and improve the performance of the package structure, for example, by performing dry cleaning such as purging, or by performing cleaning by using methods such as ultrasonic cleaning and drying, which is not strictly limited in this embodiment. In other examples, the first surface of the first glass substrate 12 may be roughened to have an uneven surface, so as to increase the bonding area between the first glass substrate 12 and the redistribution layer 11 to make the bonding between the two layers tighter. It should be noted that the first surface and the second surface are only for the convenience of description and are not particularly significant.
By way of example, the material of the dielectric layer 111 includes, but is not limited to, one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the method for forming the dielectric layer 111 includes, but is not limited to, a chemical vapor deposition process; methods of forming the metal connection layer 112 include, but are not limited to, electroplating or physical vapor deposition; the material of the metal connection layer 112 includes, but is not limited to, one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. The number of layers of the dielectric layer 111 and the metal layer may be a single layer, or 2 or more layers, but it is necessary to ensure electrical connection between the metal connection layers 112.
As an example, the metal connection stud 13 may be formed by forming a through hole penetrating through the first glass substrate 12 by laser etching at a position of the first glass substrate 12 corresponding to the position to be connected to the metal connection layer 112, and then filling metal into the through hole by using a physical vapor deposition method or an electroplating method to form the metal connection stud 13. The adopted laser can be ultraviolet laser or fiber laser, and the advantages of the adopted laser etching compared with the conventional plasma etching are many, such as high etching speed, high etching precision, accurate control of the etching process, no need of chemical corrosion, reduction of environmental pollution, reduction of etching cost and the like; the first glass substrate 12 has a transparent characteristic due to the glass, so that a mask is not required to be used in the process of forming the metal connection post 13, and the production cost can be effectively reduced.
In one example, the step of forming the first antenna layer 14 on the second surface of the first glass substrate 12 includes:
forming a first antenna metal layer on the second surface of the first glass substrate 12;
performing photolithography etching on the first antenna metal layer to separate the first antenna metal layer into a plurality of antennas 141 distributed at intervals;
a protective layer 19 is formed in the gap between the antennas 141.
As an example, the method for forming the first antenna metal layer includes, but is not limited to, electroplating or physical vapor deposition, such as evaporation, and the material of the first antenna metal layer includes, but is not limited to, one or more of copper, aluminum, and silver, such as a composite metal layer that is a silver-plated layer on the surface of a copper layer; the material of the protection layer 19 includes, but is not limited to, one of polyimide, silicone, and epoxy, and the method for forming the protection layer 19 includes, but is not limited to, one or more of ink-jet, dispensing, compression molding, transfer molding, liquid-sealing, vacuum lamination, and spin coating.
In an example, the process of forming the first antenna layer 14 further includes a step of forming an alignment mark on the first antenna layer 14, and the alignment mark is used for alignment in the process of attaching the first glass substrate 12 to the second glass substrate 15. The material of the alignment mark may be the same as that of the first antenna layer 14, and the number of the alignment mark may be one or more, and the alignment mark is generally located at the periphery of the antenna 141 of the first antenna layer 14.
Of course, in another example, the protection layer 19 may be formed before the second surface of the first glass substrate 12, and the first antenna layer 14 may be formed by a physical vapor deposition method or an electroplating method after the shape of the first antenna layer 14 is defined on the protection layer 19, which is not limited in this embodiment.
As an example, the second antenna layer 16 may be formed by forming a second antenna metal layer on the second glass substrate 15 by an electroplating method or a physical vapor deposition method, and then etching the second antenna metal layer by photolithography to obtain the second antenna layer 16 with a desired shape, where the material of the second antenna metal layer includes, but is not limited to, one or more of copper, aluminum, and silver, such as a composite metal layer that is a silver-plated layer on the surface of a copper layer.
For example, after the surfaces to be bonded of the first glass substrate 12 and the second glass substrate 15 are coated with glue, the first glass substrate 12 and the second glass substrate 15 are bonded, and after the bonding, the first glass substrate 12 and the second glass substrate 15 are preferably cured and molded by an ultraviolet curing or thermal curing process.
As an example, the chip 18 and the metal connection layer 112 may be electrically connected through a wire bonding process.
As an example, before forming the metal bump 17, a step of forming an underfill layer 20 filled between the chip 18 and the redistribution layer 11 after bonding the chip 18 and the redistribution layer 11 is further included. The underfill layer 20 may improve the bonding strength of the chip 18 to the redistribution layer 11 and protect the redistribution layer 11. The material of the underfill layer 20 includes, but is not limited to, one or more of polyimide, silicone, and epoxy, and the method for forming the underfill layer 20 includes, but is not limited to, one or more of inkjet, dispensing, compression molding, transfer molding, liquid encapsulation, vacuum lamination, and spin coating.
The semiconductor package structure prepared by this example is shown in fig. 1.
Example four
The present embodiment further provides another method for manufacturing a semiconductor package structure, which is used to manufacture the semiconductor package structure in the second embodiment. The manufacturing method of the present embodiment is different from the third embodiment in that, in the semiconductor package structure manufactured in the third embodiment, the first antenna layers 14 are formed on the upper surface of the first glass substrate 12, and gaps existing between the antennas 141 of the first antenna layers 14 are filled with the protective layer 19 to include the first antenna layers 14; in the semiconductor package structure prepared in this embodiment, the first glass substrate 12 has the trench formed therein, and the first antenna layer 14 is formed in the trench, and the trench may be formed by photolithography etching or by laser etching, preferably by laser etching, which can effectively reduce the etching cost, so that the first glass substrate 12 between the trenches forms a good protection for the first antenna layer 14 without making the protection layer 19. The first antenna layer 14 is exposed from the surface of the first glass substrate 12, i.e., the first antenna layer 14 is embedded in the first glass substrate 12. As an example, the upper surface of the first antenna layer 14 is preferably not higher than the upper surface of the first glass substrate 12, for example, the upper surfaces of the two may be flush or the upper surface of the first antenna layer 14 is lower than the upper surface of the first glass substrate 12, and a height difference portion between the two may be filled with glue to fix the first antenna layer 14, and at the same time, the second glass substrate 15 and the first glass substrate 12 are closely attached, which helps to improve the quality and performance of the package structure. The second antenna layer 16 may also be formed in the same manner as the first antenna layer 14, that is, a groove corresponding to the second antenna layer 16 is formed in the second glass substrate 15 by laser etching, and then a metal is filled in the groove by electroplating or evaporation to form the second antenna layer 16. In addition, other steps of the preparation method of this embodiment are the same as those in embodiment three, and specific reference is made to embodiment three, which is not repeated for brevity.
The semiconductor package structure prepared by this embodiment is shown in fig. 2.
As described above, the present invention provides a semiconductor package structure and a method for manufacturing the same, the semiconductor package structure includes a redistribution layer having a first surface and a second surface opposite to the first surface, the redistribution layer including a dielectric layer and a metal connection layer located in the dielectric layer; a first glass substrate on a second surface of the rewiring layer; the metal connecting column penetrates through the first glass substrate and is electrically connected with the metal connecting layer; the first antenna layer is positioned on the surface, away from the rewiring layer, of the first glass substrate, and the first antenna layer is electrically connected with the metal connecting column; a second glass substrate covering the first antenna layer; the second antenna layer is positioned on the surface, away from the first antenna layer, of the second glass substrate; the metal bump is positioned on the first surface of the rewiring layer and is electrically connected with the metal connecting layer; and the chip is positioned on the first surface of the rewiring layer and is electrically connected with the metal connecting layer. The semiconductor packaging structure of the invention adopts the rewiring layer and the multilayer glass substrate to realize the integration of two or more antenna metal layers, which is beneficial to reducing the volume of the packaging structure, improving the integration level of devices, simultaneously reducing the cost and improving the performance of the packaging structure. By adopting the preparation method, a carrier is not required to be used for transferring in the packaging process, the alignment in the packaging process is simpler, the preparation process is facilitated to be simplified, and the production cost is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A semiconductor package structure, comprising:
the rewiring layer is provided with a first surface and a second surface opposite to the first surface and comprises a dielectric layer and a metal connecting layer positioned in the dielectric layer;
a first glass substrate on a second surface of the rewiring layer;
the metal connecting column penetrates through the first glass substrate and is electrically connected with the metal connecting layer;
the first antenna layer is positioned on the surface, away from the rewiring layer, of the first glass substrate, and the first antenna layer is electrically connected with the metal connecting column;
a second glass substrate covering the first antenna layer;
The second antenna layer is positioned on the surface, away from the first antenna layer, of the second glass substrate;
the metal bump is positioned on the first surface of the rewiring layer and is electrically connected with the metal connecting layer; and
and the chip is positioned on the first surface of the rewiring layer and is electrically connected with the metal connecting layer.
2. The semiconductor package structure of claim 1, wherein: the first antenna layer comprises a plurality of antennas which are distributed at intervals, and the semiconductor packaging structure further comprises a protective layer located between the antennas.
3. The semiconductor package structure of claim 2, wherein: the second antenna layer comprises a plurality of antennas which are distributed at intervals, the number of the antennas included in the first antenna layer is the same as that of the antennas included in the second antenna layer, and the antennas of the first antenna layer and the antennas of the second antenna layer are arranged in a one-to-one correspondence mode.
4. The semiconductor package structure of claim 1, wherein: the semiconductor packaging structure further comprises an underfill layer filled between the chip and the rewiring layer.
5. The semiconductor package structure according to any one of claims 1 to 4, wherein: the first antenna layer is also provided with an alignment mark, and the first antenna layer and the second antenna layer are aligned through the alignment mark.
6. A preparation method of a semiconductor packaging structure is characterized by comprising the following steps:
1) providing a first glass substrate, wherein the first glass substrate is provided with a first surface and a second surface opposite to the first surface, and a rewiring layer is formed on the first surface of the first glass substrate and comprises a dielectric layer and a metal connecting layer positioned in the dielectric layer;
2) forming a metal connecting column, wherein the metal connecting column penetrates through the first glass substrate and is exposed on the second surface of the first glass substrate, and the metal connecting column is electrically connected with the metal connecting layer;
3) forming a first antenna layer on the second surface of the first glass substrate, wherein the first antenna layer is electrically connected with the metal connecting column;
4) providing a second glass substrate, wherein the second glass substrate is provided with a first surface and a second surface opposite to the first surface, and a second antenna layer is formed on the first surface of the second glass substrate;
5) attaching the first glass substrate with the first antenna layer and the second glass substrate with the second antenna layer to obtain an attachment sheet, wherein the surface of the first antenna layer and the second surface of the second glass substrate are attachment surfaces;
6) Bonding the surface, away from the first glass substrate, of the rewiring layer of the attaching sheet with a chip, wherein the chip is electrically connected with the metal connecting layer;
7) and forming a metal bump on the surface of the rewiring layer, which is far away from the first glass substrate, wherein the metal bump is electrically connected with the metal connecting layer.
7. The method of claim 6, wherein: the preparation method further comprises the step of curing and molding the first glass substrate and the second glass substrate by adopting an ultraviolet curing or thermosetting process after the first glass substrate and the second glass substrate are attached.
8. The method of claim 6, wherein: the manufacturing method further includes a step of forming an underfill layer filled between the chip and the rewiring layer after bonding the chip and the rewiring layer.
9. The method according to claim 6, wherein the step of forming the first antenna layer on the second surface of the first glass substrate comprises:
forming a first antenna metal layer on the second surface of the first glass substrate;
etching the first antenna metal layer to separate the first antenna metal layer into a plurality of antennas distributed at intervals;
And forming a protective layer in the gap between the antennas.
10. The production method according to any one of claims 6 to 9, characterized in that: the preparation method further comprises the step of forming an alignment mark on the first antenna layer, and alignment is realized through the alignment mark in the process of attaching the first glass substrate and the second glass substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910426712.2A CN111987062A (en) | 2019-05-22 | 2019-05-22 | Semiconductor packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910426712.2A CN111987062A (en) | 2019-05-22 | 2019-05-22 | Semiconductor packaging structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111987062A true CN111987062A (en) | 2020-11-24 |
Family
ID=73436375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910426712.2A Pending CN111987062A (en) | 2019-05-22 | 2019-05-22 | Semiconductor packaging structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111987062A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022246599A1 (en) * | 2021-05-24 | 2022-12-01 | 华为技术有限公司 | Packaging structure and manufacturing method therefor, and electronic device |
-
2019
- 2019-05-22 CN CN201910426712.2A patent/CN111987062A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022246599A1 (en) * | 2021-05-24 | 2022-12-01 | 华为技术有限公司 | Packaging structure and manufacturing method therefor, and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9881859B2 (en) | Substrate block for PoP package | |
| TWI684260B (en) | Electronic package and method for fabricating the same | |
| US10916829B2 (en) | Semiconductor package structure having antenna module | |
| CN109755202B (en) | Electronic package and manufacturing method thereof | |
| CN108336494B (en) | Antenna packaging structure and packaging method | |
| EP3772100B1 (en) | Semiconductor package structure including antenna | |
| CN110858576B (en) | Flip chip package substrate and method for fabricating the same | |
| CN113497009A (en) | Semiconductor packaging structure and preparation method thereof | |
| US20080224276A1 (en) | Semiconductor device package | |
| CN114899155A (en) | Multi-type multi-quantity chip three-dimensional stacking integrated packaging structure and manufacturing method thereof | |
| CN113497008A (en) | Semiconductor packaging structure and preparation method thereof | |
| CN112713098A (en) | Antenna packaging structure and packaging method | |
| CN112713097A (en) | Antenna packaging structure and packaging method | |
| CN211376638U (en) | Semiconductor packaging structure | |
| CN112054005B (en) | Electronic package and manufacturing method thereof | |
| CN209804651U (en) | Semiconductor packaging structure | |
| CN111987062A (en) | Semiconductor packaging structure and preparation method thereof | |
| CN112018091A (en) | Semiconductor packaging structure and preparation method thereof | |
| CN107622981B (en) | Electronic package and manufacturing method thereof | |
| CN210692485U (en) | Antenna packaging structure | |
| US11121065B2 (en) | Semiconductor packaging structure with antenna assembly | |
| CN211088260U (en) | Antenna packaging structure | |
| TW201709353A (en) | Thin film based fan out and multi die package platform | |
| US20190181105A1 (en) | Semiconductor packaging structure having antenna module | |
| TW202137342A (en) | Chip embedded substrate structure, chip package structure and methods of manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Applicant after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Applicant before: SJ Semiconductor (Jiangyin) Corp. |