CN111986998B - LDMOS device and preparation method thereof - Google Patents
LDMOS device and preparation method thereof Download PDFInfo
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- CN111986998B CN111986998B CN202010984316.4A CN202010984316A CN111986998B CN 111986998 B CN111986998 B CN 111986998B CN 202010984316 A CN202010984316 A CN 202010984316A CN 111986998 B CN111986998 B CN 111986998B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 214
- 229910052751 metal Inorganic materials 0.000 claims abstract description 97
- 239000002184 metal Substances 0.000 claims abstract description 97
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 210000000746 body region Anatomy 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 16
- 229910052721 tungsten Inorganic materials 0.000 claims description 16
- 239000010937 tungsten Substances 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000695274 Processa Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002500 effect on skin Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The application discloses an LDMOS device and a preparation method thereof, and the device comprises: a silicon substrate; the epitaxial layer is formed on the silicon substrate, the thickness of the epitaxial layer is larger than 30 micrometers, a drift region and a channel region are formed in the epitaxial layer, a source region and a body region are formed in the drift region, and a drain region is formed on one side of the channel region; a gate oxide layer formed on the epitaxial layer; a gate formed on the gate oxide layer; a first metal silicide layer formed on the gate electrode; an oxide layer formed on the first metal silicide layer and the epitaxial layer; a second metal silicide layer formed on the oxide layer; an interlayer dielectric formed on the oxide layer and the second metal silicide layer; and the deep contact hole is formed in the interlayer medium, the epitaxial layer and the silicon substrate, and the bottom end of the deep contact hole is in contact with the silicon substrate. According to the method and the device, the technical effect of reducing high-frequency loss can be achieved without arranging a high-resistivity substrate, and therefore the contact hole and the high-resistivity substrate are not required to be connected through a TSV (through silicon Via) process.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a laterally-diffused metal-oxide semiconductor (LDMOS) device and a method for manufacturing the same.
Background
The LDMOS device, especially a Radio Frequency (RF) LDMOS device, is widely applied to the radio frequency high power field such as a base station, a broadcast television, etc., and is usually synthesized with other devices, and the output power of the product can reach more than 500 watts (W). Among them, a chip product applied to the fifth generation mobile communication technology (5 th generation mobile networks,5 g) needs to increase a signal bandwidth from 40 megahertz (MHz) of Long Term Evolution (LTE) to 200MHz, and thus, a high requirement is provided for a device performance under a high frequency.
Under high frequency, the performance of the LDMOS device is directly influenced by the loss of the capacitor and the inductor, the skin effect of the resistance wire becomes more and more obvious along with the increase of the frequency, the resistance of the lead wire becomes larger, and the loss of the inductor is increased; meanwhile, in order to reduce thermal resistance, the LDMOS device usually adopts a heavily doped substrate, and the loss caused by the heavily doped substrate is also obvious at high frequency.
In the related art, in order to reduce inductance loss at high frequency, a thick metal layer or a high conductivity copper wire is generally used in a contact hole of an LDMOS device, and in order to reduce substrate loss, a substrate with high resistivity (e.g., a glass substrate) is generally used, and the contact hole and the substrate are connected through a Through Silicon Via (TSV) process.
However, the process of connecting the contact hole and the substrate through the TSV process is complicated and has a low yield, resulting in a high manufacturing cost of the device.
Disclosure of Invention
The application provides an LDMOS device and a preparation method thereof, and can solve the problem that the manufacturing cost of the LDMOS device provided in the related technology is high.
On one hand, the embodiment of the application provides a preparation method of an LDMOS device, which comprises the following steps:
forming an epitaxial layer on a silicon substrate, wherein the thickness of the epitaxial layer is more than 30 microns;
sequentially forming a gate oxide layer, a gate and a first metal silicide layer on the epitaxial layer;
forming a drift region in the epitaxial layer by ion implantation;
forming a channel region in the epitaxial layer by ion implantation;
forming a source region and a body region in the channel region by ion implantation, and forming a drain region on one side of the drift region in the epitaxial layer;
forming an oxide layer on the first metal silicide layer and the epitaxial layer, and forming a second metal silicide layer on the oxide layer;
forming an interlayer dielectric on the oxide layer and the second metal silicide layer;
and forming a deep contact hole in the interlayer medium, the epitaxial layer and the silicon substrate, wherein the bottom end of the deep contact hole is in contact with the silicon substrate.
Optionally, the forming a deep contact hole in the interlayer dielectric, the epitaxial layer, and the silicon substrate includes:
forming a trench in the interlayer dielectric;
forming at least two through holes in the epitaxial layer and the silicon substrate;
and filling a metal tungsten layer in the groove and the through hole, and flattening the metal tungsten layer to form the deep contact hole.
Optionally, a plurality of deep contact holes are formed in the silicon substrate, the deep contact holes are rectangular in plan view, the silicon substrate includes a plurality of unit regions, deep contact holes distributed in parallel are formed in each unit region, and the deep contact holes between each unit region are perpendicular to each other.
Optionally, the sequentially forming a gate oxide layer, a gate electrode and a first metal silicide layer on the epitaxial layer includes:
forming an oxide on the epitaxial layer through a furnace tube oxidation process;
forming a polysilicon layer on the oxide;
forming a metal layer on the polysilicon layer, reacting the metal layer with the polysilicon layer through heat treatment to generate metal silicide, and flattening the metal layer to remove redundant metal layer;
and defining a region corresponding to the grid electrode by a photoetching process, etching to remove the metal silicide, the polysilicon layer and the oxide in the exposed region, forming the first metal silicide layer by using the residual metal silicide, forming the grid electrode by using the residual polysilicon layer, and forming the grid oxide layer by using the residual oxide.
In another aspect, an embodiment of the present application provides an LDMOS device, including:
a silicon substrate;
the epitaxial layer is formed on the silicon substrate, the thickness of the epitaxial layer is larger than 30 micrometers, a drift region and a channel region are formed in the epitaxial layer, an active region and a body region are formed in the channel region, and a drain region is formed on one side of the drift region;
the gate oxide layer is formed on the epitaxial layer;
the grid electrode is formed on the grid oxide layer;
a first metal silicide layer formed on the gate electrode;
an oxide layer formed on the first metal silicide layer and the epitaxial layer;
a second metal silicide layer formed on the oxide layer;
an interlayer dielectric formed on the oxide layer and the second metal silicide layer;
and the deep contact hole is formed in the interlayer medium, the epitaxial layer and the silicon substrate, and the bottom end of the deep contact hole is in contact with the silicon substrate.
Optionally, the deep contact hole comprises tungsten.
Optionally, a plurality of deep contact holes are formed in the silicon substrate, the deep contact holes are rectangular in plan view, the silicon substrate includes a plurality of regions, deep contact holes are formed in each region and distributed in parallel, and the deep contact holes between each region are perpendicular to each other.
Optionally, the first metal silicide layer includes titanium metal silicide.
Optionally, the second metal silicide layer includes tungsten metal silicide.
Optionally, the depth of the deep contact hole is greater than 40 microns.
The technical scheme at least comprises the following advantages:
the epitaxial layer with the thickness larger than 30 micrometers is formed on the silicon substrate, the deep contact holes are formed in the interlayer medium, the epitaxial layer and the silicon substrate, and the source region of the device is connected with the silicon substrate through the deep contact holes.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings used in the detailed description or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing an LDMOS device according to an exemplary embodiment of the present application;
fig. 2 to 7 are schematic diagrams illustrating a process of manufacturing an LDMOS device according to an exemplary embodiment of the present application;
fig. 8 is a top view of a deep contact hole layout of an LDMOS device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for manufacturing an LDMOS device, which may be used in the manufacture of an RFLDMOS device, according to an exemplary embodiment of the present application is shown, and the method includes:
Referring to fig. 2, a schematic cross-sectional view of an epitaxial layer formed on a silicon substrate is shown. As shown in fig. 2, the X axis and the Y axis are defined by a plane in which the surface of the substrate 210 is located, and the Z axis is defined by a direction in which the thickness of the substrate 210 is located. In the embodiment of the present application, the epitaxial layer 220 having a thickness h1 greater than 30 μm may be grown on the silicon substrate 210 by epitaxial growth. The doped ions in the silicon substrate 210 and the epitaxial layer 220 are the first type of ions, and the silicon substrate 210 is a heavily doped substrate with a doping concentration of ions greater than that of the epitaxial layer 220.
And 102, sequentially forming a gate oxide layer, a gate electrode and a first metal silicide layer on the epitaxial layer.
In step 103, a drift region is formed in the epitaxial layer by ion implantation.
At step 104, a channel region is formed in the epitaxial layer by ion implantation.
And 105, forming a source region and a body region in the channel region through ion implantation, and forming a drain region on one side of the drift region in the epitaxial layer.
And 106, forming an oxide layer on the first metal silicide layer and the epitaxial layer, and forming a second metal silicide layer on the oxide layer.
In step 107, an interlayer dielectric is formed over the oxide layer and the second metal silicide layer.
Referring to fig. 3, a schematic cross-sectional view of the resulting structure is shown prior to forming the deep contact hole. As shown in fig. 3, a channel region 201 and a drift region 202 are formed in an epitaxial layer 220, an active region 203 and a body region 204 are formed in the channel region 201, a drain region 205 is formed on one side of the drift region 202, a gate oxide layer 230 is formed on the epitaxial layer 220, a gate 240 is formed on the gate oxide layer 230, a first metal silicide layer 251 is formed on the gate 240, an oxide layer 260 is formed on the epitaxial layer 220 and the first metal silicide layer 251, and a second metal silicide layer 252 is formed on the oxide layer 260.
Optionally, in this embodiment of the present application, step 102 includes but is not limited to: forming an oxide on the epitaxial layer 220 by a furnace oxidation process; forming a polysilicon layer on the oxide; forming a metal layer on the polycrystalline silicon layer, reacting the metal layer with the polycrystalline silicon layer through heat treatment to generate metal silicide, and flattening the metal layer to remove redundant metal layer; the region corresponding to the gate 240 is defined through a photolithography process, and the metal silicide, the polysilicon layer and the oxide in the exposed region are removed through etching, the remaining metal silicide forms the first metal silicide layer 251, the remaining polysilicon layer forms the gate 240, and the remaining oxide forms the gate oxide layer 230. Wherein the first metal silicide layer 251 includes titanium silicide.
Illustratively, after forming the gate oxide layer 230, the gate electrode 240 and the first metal silicide layer 251, a second type of ion implantation may be performed to form the channel region 201, a first type of ion implantation may be performed to form the drift region 202, a second type of ion implantation may be performed to form the source region 203 and the drain region 205, and a first type of ion implantation may be performed to form the body region 204.
Illustratively, an oxide layer 260 may be formed on the epitaxial layer 220 by a Chemical Vapor Deposition (CVD) process, a metal layer may be formed on the oxide layer 260, the metal layer may react with the polysilicon layer by a thermal process to form a metal silicide, the metal layer may be planarized to remove an excess metal layer, a region corresponding to the second metal silicide layer 252 may be defined by a photolithography process, the metal silicide in the exposed region may be removed by etching, the remaining metal silicide may form the second metal silicide layer 252, and the oxide layer 260 and the second metal silicide layer 252 may be formed by a CVD processA CVD process is deposited to form interlayer dielectric 270. Wherein the second metal silicide layer 252 comprises tungsten metal silicide; the interlayer dielectric 270 comprises a high dielectric constant material (a material having a dielectric constant k greater than 4, such as silicon dioxide, siO) 2 )。
Optionally, in this application, before forming the oxide layer 260, the method further includes: a third metal silicide layer 253 is formed in source region 203 and body region 204 and a fourth metal silicide layer 254 is formed in drain region 205. The method for forming the third metal silicide layer 253 and the fourth metal silicide layer 254 can refer to the above embodiments, and is not described herein again.
And step 108, forming a deep contact hole in the interlayer medium, the epitaxial layer and the silicon substrate, wherein the bottom end of the deep contact hole is in contact with the silicon substrate.
Optionally, step 108 includes, but is not limited to: forming a trench in the interlayer dielectric; forming at least two through holes in the epitaxial layer and the silicon substrate; and filling a metal tungsten layer in the groove and the through hole, and flattening the metal tungsten layer to form a deep contact hole.
Referring to fig. 4, a cross-sectional view of forming a trench in an interlayer dielectric is shown. For example, as shown in fig. 4, a region corresponding to the trench 271 may be defined on the interlayer dielectric 270 through a photolithography process, and etching is performed to remove the interlayer dielectric in the exposed region, so as to form the trench 271, where the epitaxial layer 220 at the bottom of the trench 271 is exposed.
Referring to fig. 5, a cross-sectional schematic view of at least two vias formed in an epitaxial layer and a silicon substrate is shown. Illustratively, as shown in fig. 5, regions corresponding to at least two through holes 221 (two through holes 221 are exemplarily illustrated in fig. 5) may be defined on the epitaxial layer 220 through a photolithography process, and etching is performed to remove the epitaxial layer 220 in the exposed regions and the silicon substrate 210 at a target depth, so as to form the through holes 221.
Optionally, in this embodiment of the application, before filling the metal tungsten layer in the trench and the via hole, the method further includes: a barrier layer is grown on the sidewalls of the trench and via.
Referring to fig. 6, a schematic cross-sectional view of a diffusion barrier layer grown on the sidewalls of the trench and via is shown; referring to FIG. 7, a schematic cross-sectional view of the formation of a deep contact hole is shown. Illustratively, as shown in fig. 6, the sidewalls of the trench 271 and via 221 are grown with a diffusion barrier 281; as shown in fig. 7, the deep contact hole 280 may be obtained by filling a metal tungsten layer in the trench 271 and the via hole 221 and performing a planarization process on the metal tungsten layer. Optionally, the depth h2 of the deep contact hole 280 is greater than 40 microns.
Referring to fig. 8, a top view of an alternative deep contact hole distribution is shown. As shown in fig. 7, a plurality of deep contact holes 280 are formed in the silicon substrate 210, the deep contact holes 280 are rectangular in a plan view, the silicon substrate 210 includes a plurality of cell regions 211, the deep contact holes 280 are formed in each cell region 211 and are arranged in parallel, and the deep contact holes 280 are perpendicular to each other between each cell region 211. By setting the deep contact holes 280 between each cell region 211 to be perpendicular to each other, the problem of substrate warpage caused by the parallel deep contact holes distributed on the substrate in the related art can be solved, and the yield is improved.
To sum up, in the embodiment of the application, the epitaxial layer with the thickness larger than 30 micrometers is formed on the silicon substrate, the deep contact hole is formed in the interlayer medium, the epitaxial layer and the silicon substrate, and the source region of the device is connected with the silicon substrate through the deep contact hole.
Referring to fig. 7, a schematic cross-sectional view of an LDMOS device provided in an exemplary embodiment of the present application is shown. As shown in fig. 7, the LDMOS device includes:
a silicon substrate 210;
an epitaxial layer 220 formed on the silicon substrate 210 and having a thickness greater than 30 μm, wherein a channel region 201 and a drift region 202 are formed, an active region 203 and a body region 204 are formed in the channel region 201, and a drain region 205 is formed on one side of the drift region 202;
a gate oxide layer 230 formed on the epitaxial layer 220;
a gate electrode 240 formed on the gate oxide layer 230;
a first metal silicide layer 251 formed on the gate electrode 230;
an oxide layer 260 formed on the first metal silicide layer 251 and the epitaxial layer 220;
a second metal silicide layer 252 formed on the oxide layer 260;
an interlayer dielectric 270 formed on the oxide layer 260 and the second metal silicide layer 251;
and a deep contact hole 280 formed in the interlayer dielectric 270, the epitaxial layer 220 and the silicon substrate 210, the bottom end of which is in contact with the silicon substrate 210.
Optionally, the deep contact hole 280 comprises tungsten.
Alternatively, referring to fig. 8, a plurality of deep contact holes 280 are formed in the silicon substrate 210, the deep contact holes 280 are rectangular in a top view, the silicon substrate 210 includes a plurality of regions 211, the deep contact holes 280 are formed in each region 211 and are distributed in parallel, and the deep contact holes 280 in each region 211 are perpendicular to each other.
Optionally, the first metal silicide layer 251 includes titanium metal silicide.
Optionally, the second metal silicide layer 252 includes tungsten metal silicide.
Optionally, the depth h2 of the deep contact hole 280 is greater than 40 microns.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A preparation method of an LDMOS device is characterized by comprising the following steps:
forming an epitaxial layer on a silicon substrate, wherein the thickness of the epitaxial layer is more than 30 microns;
sequentially forming a gate oxide layer, a gate and a first metal silicide layer on the epitaxial layer;
forming a drift region in the epitaxial layer by ion implantation;
forming a channel region in the epitaxial layer by ion implantation;
forming a source region and a body region in the channel region by ion implantation, and forming a drain region on one side of the drift region in the epitaxial layer;
forming an oxide layer on the first metal silicide layer and the epitaxial layer, and forming a second metal silicide layer on the oxide layer;
forming an interlayer dielectric on the oxide layer and the second metal silicide layer;
and forming a deep contact hole in the interlayer medium, the epitaxial layer and the silicon substrate, wherein the bottom end of the deep contact hole is in contact with the silicon substrate.
2. The method of claim 1, wherein said forming deep contact holes in said interlayer dielectric, said epitaxial layer and said silicon substrate comprises:
forming a trench in the interlayer dielectric;
forming at least two through holes in the epitaxial layer and the silicon substrate;
and filling a metal tungsten layer in the groove and the through hole, and flattening the metal tungsten layer to form the deep contact hole.
3. The method of claim 2, wherein the silicon substrate has a plurality of deep contact holes formed therein, the deep contact holes having a rectangular shape in plan view, the silicon substrate includes a plurality of cell regions, each of the cell regions has deep contact holes formed therein and arranged in parallel with each other, and the deep contact holes between each of the cell regions are perpendicular to each other.
4. The method of any of claims 1 to 3, wherein sequentially forming a gate oxide layer, a gate electrode and a first metal silicide layer on the epitaxial layer comprises:
forming an oxide on the epitaxial layer through a furnace tube oxidation process;
forming a polysilicon layer on the oxide;
forming a metal layer on the polysilicon layer, reacting the metal layer with the polysilicon layer through heat treatment to generate metal silicide, and flattening the metal layer to remove redundant metal layer;
and defining a region corresponding to the grid electrode by a photoetching process, etching to remove the metal silicide, the polysilicon layer and the oxide in the exposed region, forming the first metal silicide layer by the residual metal silicide, forming the grid electrode by the residual polysilicon layer, and forming the grid oxide layer by the residual oxide.
5. An LDMOS device, comprising:
a silicon substrate;
the epitaxial layer is formed on the silicon substrate, the thickness of the epitaxial layer is larger than 30 micrometers, a drift region and a channel region are formed in the epitaxial layer, an active region and a body region are formed in the channel region, and a drain region is formed on one side of the drift region;
the gate oxide layer is formed on the epitaxial layer;
the grid electrode is formed on the grid oxide layer;
a first metal silicide layer formed on the gate electrode;
an oxide layer formed on the first metal silicide layer and the epitaxial layer;
a second metal silicide layer formed on the oxide layer;
an interlayer dielectric formed on the oxide layer and the second metal silicide layer;
and the deep contact hole is formed in the interlayer medium, the epitaxial layer and the silicon substrate, and the bottom end of the deep contact hole is in contact with the silicon substrate.
6. The device of claim 5, wherein the deep contact hole comprises tungsten.
7. The device of claim 6, wherein the silicon substrate has a plurality of deep contact holes formed thereon, the deep contact holes having a rectangular shape in plan view, the silicon substrate having a plurality of regions, each region having deep contact holes formed therein and arranged in parallel with each other, the deep contact holes between each region being perpendicular to each other.
8. The device of any of claims 5 to 7, wherein the first metal silicide layer comprises titanium metal silicide.
9. The device of claim 8, wherein the second metal silicide layer comprises tungsten metal silicide.
10. The device of claim 9, wherein the deep contact hole has a depth greater than 40 microns.
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| CN202010984316.4A CN111986998B (en) | 2020-09-18 | 2020-09-18 | LDMOS device and preparation method thereof |
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| CN202010984316.4A CN111986998B (en) | 2020-09-18 | 2020-09-18 | LDMOS device and preparation method thereof |
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