CN111984573A - Resetting method of PCIE Switch expansion chip of controller - Google Patents

Resetting method of PCIE Switch expansion chip of controller Download PDF

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Publication number
CN111984573A
CN111984573A CN202010821240.3A CN202010821240A CN111984573A CN 111984573 A CN111984573 A CN 111984573A CN 202010821240 A CN202010821240 A CN 202010821240A CN 111984573 A CN111984573 A CN 111984573A
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China
Prior art keywords
pcie switch
reset
expansion chip
chip
switch expansion
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CN202010821240.3A
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Chinese (zh)
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孔维宾
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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Priority to CN202010821240.3A priority Critical patent/CN111984573A/en
Publication of CN111984573A publication Critical patent/CN111984573A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The invention discloses a reset method of a PCIE Switch expansion chip of a controller, which comprises the following steps: receiving a PCIE Switch extended chip reset request; generating PCIE Switch expansion chip reset enabling information; and sending the PCIE Switch expansion chip reset enabling information to the target PCIE Switch expansion chip through the target complex programmable logic device so as to reset the target PCIE Switch expansion chip. By applying the technical scheme provided by the embodiment of the invention, the reset efficiency of the Switch expansion chip is improved, the probability of insufficient bandwidth in the process of establishing the cluster after the abnormal controller is repaired is greatly reduced, and the data integrity is improved. The invention also discloses a resetting device, equipment and a storage medium of the PCIE Switch expansion chip of the controller, and the resetting device, the equipment and the storage medium have corresponding technical effects.

Description

Resetting method of PCIE Switch expansion chip of controller
Technical Field
The present invention relates to the field of computer application technologies, and in particular, to a method, an apparatus, a device, and a computer-readable storage medium for resetting a PCIE Switch expansion chip of a controller.
Background
In storage server industry applications, there is a need to use cooperation between two or more controllers (nodes), such as the QPI bus in the Intel/AMD X86 architecture design. However, in some Central Processing Units (CPUs), especially architectures of domestic CPUs (such as the architecture of the feiteng FT2000+/64 core ARM V8), such as the architecture, if two controllers need to work cooperatively, another Non-Transparent bridge (NTB) technology based on PCI Express (Peripheral Component Interconnect Express) is required to realize direct communication between two motherboards (processors) having independent IO/Memory domains.
Referring to fig. 1, fig. 1 is a non-transparent bridge bus topology diagram based on PCIE between controllers in an embodiment of the present invention. The system is a FT2000 +/64-core ARM V8 architecture, supports an ARM64 instruction set, does not support a QPI bus, cannot realize connection between two controllers, and adopts a PCIE-based non-transparent bridge technology to realize connection between the two controllers. The non-transparent bridge port between the dual-control is connected to the upstream port of the PCIE Switch expansion chip through the RC of the CPU of the controller Node1, the bandwidth is GEN3 x8, and the downstream port is connected to the PCIE Switch of the controller Node2 through the backplane and connected back to back, that is, the controller Node2 and the controller Node1 realize symmetric connection.
The controller for establishing the backup connection may have some controller abnormality, and when the controller is abnormal, the PCIE Switch expansion chip in the other normal controllers needs to be reset, so as to clear data in the PCIE Switch expansion chip, so that after the abnormal controller is repaired, normal cluster establishment can be continued.
The existing reset mode of a PCIE Switch expansion chip is to use a PCIE in-band management hotrescet scheme, that is, a CPU issues hotrescet, and issues the hotrescet to the PCIE Switch expansion chip through a PCIE link, and a downlink port performs transparent transmission through a TS1/TS2 sequence in a PCIE protocol. However, when hotrescets are performed for multiple times, the problem that x8 cannot be negotiated between the CPU and the Switch expansion chip is probabilistically caused, and cases such as x1, x2, and x4 occur in negotiation bandwidth, which causes insufficient bandwidth in the process of establishing a cluster after an abnormal controller is repaired, and data loss is caused.
In summary, how to effectively solve the problems of insufficient bandwidth, data loss and the like in the process of establishing a cluster after an abnormal controller is repaired due to the existing controller PCIE Switch expansion chip reset mode is a problem that needs to be solved urgently by a person skilled in the art at present.
Disclosure of Invention
The invention aims to provide a reset method of a PCIE Switch expansion chip of a controller, which greatly reduces the probability of the occurrence of insufficient bandwidth in the process of establishing a cluster after an abnormal controller is repaired and improves the data integrity; another object of the present invention is to provide a resetting apparatus, device and computer-readable storage medium for a PCIE Switch expansion chip of a controller.
In order to solve the technical problems, the invention provides the following technical scheme:
a reset method of a PCIE Switch extended chip of a controller comprises the following steps:
receiving a PCIE Switch extended chip reset request;
generating PCIE Switch expansion chip reset enabling information;
and sending the PCIE Switch expansion chip reset enabling information to a target PCIE Switch expansion chip through a target complex programmable logic device so as to reset the target PCIE Switch expansion chip.
In a specific embodiment of the present invention, receiving a PCIE Switch extended chip reset request includes:
and receiving a PCIE Switch extended chip reset request sent by the backup controller when the backup controller end is abnormal.
In a specific embodiment of the present invention, generating the PCIE Switch extension chip reset enable information includes:
and generating the reset enabling information of the PCIE Switch expansion chip by setting a target GPIO interface as an enabling state position.
In a specific embodiment of the present invention, sending the PCIE Switch expansion chip reset enable information to a target PCIE Switch expansion chip through a target complex programmable logic device includes:
filtering the reset enabling information of the PCIE Switch expansion chip by the target complex programmable logic device to obtain the reset enabling information of the target PCIE Switch expansion chip;
and sending the reset enabling information of the target PCIE Switch expansion chip to a perset pin of the target PCIE Switch expansion chip.
A reset device of a PCIE Switch extended chip of a controller comprises:
a request receiving module, configured to receive a PCIE Switch expansion chip reset request;
the enabling information generating module is used for generating PCIE Switch expansion chip reset enabling information;
and the chip reset module is used for sending the PCIE Switch expansion chip reset enabling information to a target PCIE Switch expansion chip through a target complex programmable logic device so as to reset the target PCIE Switch expansion chip.
In a specific embodiment of the present invention, the request receiving module is specifically a module that receives a PCIE Switch extension chip reset request sent when an abnormality occurs at the backup controller end.
In a specific embodiment of the present invention, the enabling information generating module is specifically a module that generates the reset enabling information of the PCIE Switch expansion chip by setting a target GPIO interface to an enabling state bit.
In a specific embodiment of the present invention, the chip reset module includes an information sending sub-module, and the information sending sub-module includes:
the filtering processing unit is used for filtering the reset enabling information of the PCIE Switch expansion chip through the target complex programmable logic device to obtain the reset enabling information of the target PCIE Switch expansion chip;
an information sending unit, configured to send the reset enable information of the target PCIE Switch expansion chip to the perset pin of the target PCIE Switch expansion chip.
A reset device of a controller PCIE Switch extended chip comprises:
a memory for storing a computer program;
and the processor is used for implementing the steps of the reset method of the PCIE Switch expansion chip of the controller when executing the computer program.
A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the reset method for a PCIE Switch expansion chip of a controller as described above.
By applying the method provided by the embodiment of the invention, a reset request of the PCIE Switch expansion chip is received; generating PCIE Switch expansion chip reset enabling information; and sending the PCIE Switch expansion chip reset enabling information to the target PCIE Switch expansion chip through the target complex programmable logic device so as to reset the target PCIE Switch expansion chip. By utilizing the target complex programmable logic device which is respectively in communication connection with the CPU and the target PCIE Switch expansion chip, the CPU bypasses the target complex programmable logic device to reset the target PCIE Switch expansion chip, thereby forming a coloreset scheme, improving the resetting efficiency of the Switch expansion chip, greatly reducing the probability of the occurrence of the phenomenon of insufficient bandwidth in the process of establishing a cluster after an abnormal controller is repaired, and improving the data integrity.
Correspondingly, the embodiment of the present invention further provides a resetting device, an apparatus, and a computer-readable storage medium for a PCIE Switch expansion chip of a controller, which correspond to the resetting method for a PCIE Switch expansion chip of the controller described above, and the technical effects described above are achieved, and details are not described here.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a topology diagram of a non-transparent bridge bus based on PCIE between controllers in an embodiment of the present invention;
fig. 2 is a flowchart illustrating an implementation of a reset method for a PCIE Switch expansion chip of a controller according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating another implementation of a reset method for a PCIE Switch expansion chip of a controller in an embodiment of the present invention;
fig. 4 is a block diagram of a reset system of a PCIE Switch expansion chip of a controller in an embodiment of the present invention;
fig. 5 is a block diagram of a reset device of a PCIE Switch expansion chip of a controller according to an embodiment of the present invention;
fig. 6 is a block diagram of a reset device of a PCIE Switch expansion chip of a controller in an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 2, fig. 2 is a flowchart of an implementation of a reset method for a PCIE Switch expansion chip of a controller in the embodiment of the present invention, where the method may include the following steps:
s201: and receiving a PCIE Switch extended chip reset request.
When one of the controllers which are backups of each other is abnormal, the abnormal controller generates a PCIE Switch expansion chip reset request, sends the PCIE Switch expansion chip reset request to the normal controller, and the normal controller receives the PCIE Switch expansion chip reset request.
In addition, the controllers which are backuped mutually can mutually detect whether other controllers which form backup relation with the controllers are abnormal or not, so that when the abnormal controllers have great problems and cannot send out abnormal prompt information to the outside, the normal controllers which are backuped mutually with the abnormal controllers can also timely detect the abnormal condition.
S202: and generating PCIE Switch extended chip reset enabling information.
After receiving the reset request of the PCIE Switch expansion chip, the CPU in the normal controller, which is in a backup relationship with the abnormal controller, generates PCIE Switch expansion chip reset enable information. For example, the PCIE Switch extension chip reset enable information may be controlled to be generated through level high and low control.
S203: and sending the PCIE Switch expansion chip reset enabling information to the target PCIE Switch expansion chip through the target complex programmable logic device so as to reset the target PCIE Switch expansion chip.
And establishing communication connections between the target complex programmable logic device and the CPU and between the target complex programmable logic device and the target PCIE Switch expansion chip respectively in advance. After the reset enabling information of the PCIE Switch expansion chip is generated, the reset enabling information of the PCIE Switch expansion chip is sent to the target PCIE Switch expansion chip through the target complex programmable logic device, and therefore the reset operation of the target PCIE Switch expansion chip is achieved.
The target complex programmable logic device which is respectively in communication connection with the CPU and the target PCIE Switch expansion chip is utilized, and the CPU bypasses the target complex programmable logic device to reset the target PCIE Switch expansion chip, so that a coloreset scheme is formed, the resetting efficiency of the PCIE Switch expansion chip is improved, the problem of speed reduction caused in the PCIE negotiation process of the CPU and the Switch when the PCIE Switch expansion chip is reset through the hoteset scheme in the prior art is solved, the probability of insufficient bandwidth in the process of establishing the cluster after the abnormal controller is repaired is greatly reduced, and the data integrity is improved.
By applying the method provided by the embodiment of the invention, a reset request of the PCIE Switch expansion chip is received; generating PCIE Switch expansion chip reset enabling information; and sending the PCIE Switch expansion chip reset enabling information to the target PCIE Switch expansion chip through the target complex programmable logic device so as to reset the target PCIE Switch expansion chip. By utilizing the target complex programmable logic device which is respectively in communication connection with the CPU and the target PCIE Switch expansion chip, the CPU bypasses the target complex programmable logic device to reset the target PCIE Switch expansion chip, thereby forming a coloreset scheme, improving the resetting efficiency of the PCIE Switch expansion chip, greatly reducing the probability of insufficient bandwidth in the process of establishing a cluster after an abnormal controller is repaired, and improving the data integrity.
It should be noted that, based on the first embodiment, the embodiment of the present invention further provides a corresponding improvement scheme. In the following embodiments, steps that are the same as or correspond to those in the first embodiment may be referred to each other, and corresponding advantageous effects may also be referred to each other, which are not described in detail in the following modified embodiments.
Example two:
referring to fig. 3, fig. 3 is a flowchart of another implementation of a reset method for a PCIE Switch expansion chip of a controller in the embodiment of the present invention, where the method may include the following steps:
s301: and receiving a PCIE Switch extended chip reset request sent by the backup controller when the backup controller end is abnormal.
When one of the controllers which are backups of each other is abnormal, the abnormal controller generates a reset request of the PCIE Switch expansion chip. The backup controller is the controller with the abnormality, and the backup controller and the current normal controller are mutually backed up. The method comprises the steps that a backup controller sends a PCIE Switch expansion chip reset request to a normal controller which is mutually backup with the backup controller, and the normal controller receives the PCIE Switch expansion chip reset request sent when the backup controller end is abnormal.
S302: and generating PCIE Switch expansion chip reset enabling information by setting the target GPIO interface as an enabling state position.
Referring to fig. 4, fig. 4 is a block diagram of a reset system of a PCIE Switch expansion chip of a controller in the embodiment of the present invention. The perset pin of the PCIE Switch expansion chip in the controller is connected to a target Complex programmable logic device (cpld) pin of the controller, and the GPIO interface of the CPU is connected to the Complex programmable logic device. And resetting the PCIE Switch expansion chip by the CPU bypassing the complex programmable logic device. After receiving a PCIE Switch extension chip reset request sent when an abnormality occurs at a backup controller end, a CPU of a normal controller generates PCIE Switch extension chip reset enabling information by setting a target GPIO interface to an enabling state position, for example, generating PCIE Switch extension chip reset enabling information by pulling down a GPIO interface for 100 ms.
S303: and filtering the reset enabling information of the PCIE Switch expansion chip by the target complex programmable logic device to obtain the reset enabling information of the target PCIE Switch expansion chip.
After generating the reset enabling information of the PCIE Switch expansion chip, the reset enabling information of the PCIE Switch expansion chip is filtered through the target complex programmable logic device to obtain the reset enabling information of the target PCIE Switch expansion chip, and the reset enabling information of the PCIE Switch expansion chip generated by the CPU end is filtered through the target complex programmable logic device to obtain more stable reset enabling information of the target PCIE Switch expansion chip, so that the accuracy of the subsequent reset operation of the target PCIE Switch expansion chip is improved, and the probability of misoperation is greatly reduced.
S304: and sending the reset enabling information of the target PCIE Switch expansion chip to a perset pin of the target PCIE Switch expansion chip so as to reset the target PCIE Switch expansion chip.
After filtering processing is performed on the reset enabling information of the PCIE Switch expansion chip generated by the CPU end through the target complex programmable logic device to obtain the reset enabling information of the target PCIE Switch expansion chip, the reset enabling information of the target PCIE Switch expansion chip is sent to a perset pin of the target PCIE Switch expansion chip, and therefore resetting operation of the target PCIE Switch expansion chip is achieved.
The target complex programmable logic device which is respectively in communication connection with the CPU and the target PCIE Switch expansion chip is utilized, and the CPU bypasses the target complex programmable logic device to reset the target PCIE Switch expansion chip, so that a coloreset scheme is formed, the resetting efficiency of the PCIE Switch expansion chip is improved, the problem of speed reduction caused in the PCIE negotiation process of the CPU and the Switch when the PCIE Switch expansion chip is reset through the hoteset scheme in the prior art is solved, the probability of insufficient bandwidth in the process of establishing the cluster after the abnormal controller is repaired is greatly reduced, and the data integrity is improved.
Corresponding to the above method embodiment, an embodiment of the present invention further provides a reset device for a PCIE Switch expansion chip of a controller, where the reset device for the PCIE Switch expansion chip of the controller described below and the reset method for the PCIE Switch expansion chip of the controller described above may be referred to correspondingly.
Referring to fig. 5, fig. 5 is a block diagram of a reset device of a PCIE Switch expansion chip of a controller in the embodiment of the present invention, where the device may include:
a request receiving module 51, configured to receive a PCIE Switch expansion chip reset request;
an enable information generating module 52, configured to generate PCIE Switch expansion chip reset enable information;
the chip reset module 53 is configured to send the PCIE Switch expansion chip reset enable information to the target PCIE Switch expansion chip through the target complex programmable logic device, so as to perform a reset operation on the target PCIE Switch expansion chip.
The device provided by the embodiment of the invention is applied to receive the reset request of the PCIE Switch expansion chip; generating PCIE Switch expansion chip reset enabling information; and sending the PCIE Switch expansion chip reset enabling information to the target PCIE Switch expansion chip through the target complex programmable logic device so as to reset the target PCIE Switch expansion chip. By utilizing the target complex programmable logic device which is respectively in communication connection with the CPU and the target PCIE Switch expansion chip, the CPU bypasses the target complex programmable logic device to reset the target PCIE Switch expansion chip, thereby forming a coloreset scheme, improving the resetting efficiency of the PCIE Switch expansion chip, greatly reducing the probability of insufficient bandwidth in the process of establishing a cluster after an abnormal controller is repaired, and improving the data integrity.
In a specific embodiment of the present invention, the request receiving module 51 is specifically a module that receives a PCIE Switch extended chip reset request sent when an exception occurs at the backup controller end.
In a specific embodiment of the present invention, the enabling information generating module 52 is specifically a module that generates the PCIE Switch expansion chip reset enabling information by setting the target GPIO interface to the enabling state bit.
In one embodiment of the present invention, the chip reset module 53 includes an information sending submodule, and the information sending submodule includes:
the filtering processing unit is used for filtering the reset enabling information of the PCIE Switch expansion chip through the target complex programmable logic device to obtain the reset enabling information of the target PCIE Switch expansion chip;
and the information sending unit is used for sending the reset enabling information of the target PCIE Switch expansion chip to the perset pin of the target PCIE Switch expansion chip.
Corresponding to the above method embodiment, referring to fig. 6, fig. 6 is a schematic diagram of a reset device of a PCIE Switch expansion chip of a controller provided in the present invention, where the device may include:
a memory 61 for storing a computer program;
the processor 62, when executing the computer program stored in the memory 61, may implement the following steps:
receiving a PCIE Switch extended chip reset request; generating PCIE Switch expansion chip reset enabling information; and sending the PCIE Switch expansion chip reset enabling information to the target PCIE Switch expansion chip through the target complex programmable logic device so as to reset the target PCIE Switch expansion chip.
For the introduction of the device provided by the present invention, please refer to the above method embodiment, which is not described herein again.
Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the steps of:
receiving a PCIE Switch extended chip reset request; generating PCIE Switch expansion chip reset enabling information; and sending the PCIE Switch expansion chip reset enabling information to the target PCIE Switch expansion chip through the target complex programmable logic device so as to reset the target PCIE Switch expansion chip.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
For the introduction of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments, which are not described herein again.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device, the apparatus and the computer-readable storage medium disclosed in the embodiments correspond to the method disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims (10)

1. A reset method of a PCIE Switch extended chip of a controller is characterized by comprising the following steps:
receiving a PCIE Switch extended chip reset request;
generating PCIE Switch expansion chip reset enabling information;
and sending the PCIE Switch expansion chip reset enabling information to a target PCIE Switch expansion chip through a target complex programmable logic device so as to reset the target PCIE Switch expansion chip.
2. The method of claim 1, wherein receiving a PCIE Switch extension chip reset request comprises:
and receiving a PCIE Switch extended chip reset request sent by the backup controller when the backup controller end is abnormal.
3. The method according to claim 1 or 2, wherein generating PCIE Switch extension chip reset enable information includes:
and generating the reset enabling information of the PCIE Switch expansion chip by setting a target GPIO interface as an enabling state position.
4. The method of claim 3, wherein sending the PCIE Switch expansion chip reset enable information to a target PCIE Switch expansion chip through a target complex programmable logic device comprises:
filtering the reset enabling information of the PCIE Switch expansion chip by the target complex programmable logic device to obtain the reset enabling information of the target PCIE Switch expansion chip;
and sending the reset enabling information of the target PCIE Switch expansion chip to a perset pin of the target PCIE Switch expansion chip.
5. A reset device of a PCIE Switch extended chip of a controller is characterized by comprising:
a request receiving module, configured to receive a PCIE Switch expansion chip reset request;
the enabling information generating module is used for generating PCIE Switch expansion chip reset enabling information;
and the chip reset module is used for sending the PCIE Switch expansion chip reset enabling information to a target PCIE Switch expansion chip through a target complex programmable logic device so as to reset the target PCIE Switch expansion chip.
6. The apparatus according to claim 5, wherein the request receiving module is specifically a module that receives a PCIE Switch extension chip reset request sent when an abnormality occurs at a backup controller end.
7. The reset device of a PCIE Switch expansion chip of the controller according to claim 5 or 6, wherein the enabling information generating module is specifically a module that generates the PCIE Switch expansion chip reset enabling information by setting a target GPIO interface to an enabling state bit.
8. The device according to claim 7, wherein the chip reset module includes an information sending sub-module, and the information sending sub-module includes:
the filtering processing unit is used for filtering the reset enabling information of the PCIE Switch expansion chip through the target complex programmable logic device to obtain the reset enabling information of the target PCIE Switch expansion chip;
an information sending unit, configured to send the reset enable information of the target PCIE Switch expansion chip to the perset pin of the target PCIE Switch expansion chip.
9. A reset device of a PCIE Switch extended chip of a controller is characterized by comprising:
a memory for storing a computer program;
a processor configured to implement the steps of the reset method of the PCIE Switch expansion chip of the controller according to any one of claims 1 to 4 when executing the computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps of the method for resetting a PCIE Switch expansion chip of a controller according to any one of claims 1 to 4.
CN202010821240.3A 2020-08-14 2020-08-14 Resetting method of PCIE Switch expansion chip of controller Withdrawn CN111984573A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113177063A (en) * 2021-04-29 2021-07-27 山东英信计算机技术有限公司 Thermal reset method and related device of PCI bus equipment
WO2023142367A1 (en) * 2022-01-26 2023-08-03 苏州浪潮智能科技有限公司 Hot-restart method and system for pci device, and related assembly
WO2024113818A1 (en) * 2022-11-30 2024-06-06 苏州元脑智能科技有限公司 Switch reset system and method, non-volatile readable storage medium, and electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113177063A (en) * 2021-04-29 2021-07-27 山东英信计算机技术有限公司 Thermal reset method and related device of PCI bus equipment
CN113177063B (en) * 2021-04-29 2023-04-07 山东英信计算机技术有限公司 Thermal reset method and related device of PCI bus equipment
WO2023142367A1 (en) * 2022-01-26 2023-08-03 苏州浪潮智能科技有限公司 Hot-restart method and system for pci device, and related assembly
WO2024113818A1 (en) * 2022-11-30 2024-06-06 苏州元脑智能科技有限公司 Switch reset system and method, non-volatile readable storage medium, and electronic device

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