CN111984556B - Mainboard and mainboard resource sharing method - Google Patents
Mainboard and mainboard resource sharing method Download PDFInfo
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- CN111984556B CN111984556B CN202010828595.5A CN202010828595A CN111984556B CN 111984556 B CN111984556 B CN 111984556B CN 202010828595 A CN202010828595 A CN 202010828595A CN 111984556 B CN111984556 B CN 111984556B
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- 238000001514 detection method Methods 0.000 claims abstract description 28
- 238000003780 insertion Methods 0.000 claims abstract description 8
- 230000037431 insertion Effects 0.000 claims abstract description 8
- 238000013468 resource allocation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 238000004590 computer program Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000010365 information processing Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The embodiment of the application provides a mainboard and a mainboard resource allocation method, wherein the mainboard comprises: a PCIe resource; the interface unit and the slot are arranged in pair, the interface unit is configured to be inserted into a hard disk, and the slot is configured to be inserted into an insertion card; the on-position detection circuit is configured to acquire an on-position signal of one of the hard disk and the plug-in card, wherein the on-position signal is used for indicating that the hard disk is inserted into the interface unit or the plug-in card is inserted into the slot; control circuitry configured to allocate at least part of the PCIe resources to an in-place object in dependence on the in-place signal; wherein the in-place object comprises the hard disk or the add-in card. Some embodiments of the application determine whether the plug-in card is in place or the hard disk is in place at different times through the in-place detection circuit, dynamically allocate PCIe resources to the in-place objects, and improve PCIe resource utilization rate on the motherboard in a time division multiplexing manner.
Description
Technical Field
The present application relates to the field of computer resource sharing, and in particular, to a motherboard and a motherboard resource sharing method.
Background
With the great diversity of science and technology, the processing speed of a computer is faster and faster, the types of interfaces in the computer are richer and more buses are supported. For example, most Personal Computers (PCs) support an m.2nvme interface unit and a PCIe (PCI-Express) expansion slot, which are high-speed serial computer expansion bus standards, and in an implementation mode, the m.2nvme interface unit and the PCIe expansion slot separately occupy PCIe resources.
In the related art, an interface unit (for example, an m.2NVMe interface unit, where m.2 is a host interface scheme and supports protocols such as SATA and PCIe; NVMe is called Non-Volatile Memory expression, which is named as "Non-Volatile Memory host controller interface specification", m.2 is an interface, and NVMe is a storage compliant specification) and a slot (for example, a PCIe expansion slot) only have a disadvantage that PCIe resources are not fully utilized all the time. This is because, when the PCIe resource is allocated to one interface unit in the related art, the motherboard allocates the corresponding PCIe resource to the hard disk regardless of whether the hard disk is inserted into the interface unit, which causes resource waste.
Disclosure of Invention
An object of the embodiments of the present application is to provide a motherboard, a motherboard resource sharing method, and a computer, where a hard disk or a plug-in card according to some embodiments of the present application may multiplex PCIe resources of the motherboard in a time-sharing manner, fully utilize the PCIe resources, and can adaptively adjust the PCIe resources. For example, some embodiments of the present application may allocate PCIe resources as appropriate depending on whether m.2nvme's hard disk or add-in card is installed.
In a first aspect, some embodiments of the present application provide a motherboard, comprising: a PCIe resource; the interface unit and the slot are arranged in pair, the interface unit is configured to be inserted into a hard disk, and the slot is configured to be inserted into an insertion card; the on-site detection circuit is configured to acquire an on-site signal of an on-site object, wherein the on-site object comprises the hard disk inserted into the interface unit or the plug-in card inserted into the slot; control circuitry configured to allocate at least part of the PCIe resources to an in-place object in dependence on the in-place signal; wherein the in-place object includes the hard disk inserted into the interface unit or the plug-in card inserted into the slot.
Some embodiments of the application determine whether the plug-in card is in place or the hard disk is in place through the in-place detection circuit, and allocate PCIe resources to the in-place objects, so that the PCIe resource utilization rate on the motherboard is improved.
In some embodiments, the presence detection circuit is configured to set two mutually exclusive presence signals for insertion of the hard disk into the interface unit and insertion of the add-in card into the slot, respectively.
Some embodiments of the present application may determine the in-place object at the current time by setting two different in-place signals for the plug-in card inserted into the slot and the hard disk inserted into the interface unit, respectively.
In some embodiments, the two mutually exclusive in-bit signals comprise a high level signal and a low level signal, respectively.
According to the embodiments of the application, the level of the first node after the plug-in card is inserted or the level of the second node after the hard disk is inserted is used for determining whether the plug-in card or the hard disk is inserted currently through the pull-up circuit, so that the accuracy and the speed of the detection of the in-place object are improved.
In some embodiments, the motherboard further comprises: and the height limiting unit is configured to be arranged between the interface unit and the slot which are arranged in pair, and the sum of the height limiting unit and the height of a hard disk inserted into the interface unit is greater than the height of the lower surface of the plug-in card after the plug-in card is inserted into the slot.
Some embodiments of the application ensure that the corresponding slot cannot be inserted into the plug-in card after the interface unit is inserted into the hard disk through the height limiting unit, so as to ensure that only one of the hard disk or the plug-in card is in place.
In some embodiments, the motherboard further comprises: a height limiting unit configured to be disposed between the interface unit and the slot, the height limiting unit including an upper surface contacting a lower surface of the card after the card is inserted into the slot.
Some embodiments of the application guarantee that the corresponding slot cannot be inserted into the plug-in card after the interface unit is inserted into the hard disk by limiting the height of the height limiting unit to be the same as the lower surface of the inserted plug-in card, so that time-sharing multiplexing of the in-place object to PCIe resources is realized.
In some embodiments, the height limiting unit comprises: the hard disk drive comprises a stud or a gasket, wherein the stud is also used for fixing one end of the hard disk.
Some embodiments of the present application use studs and shims as height limiting units, thereby achieving the goal of having only one object in place.
In some embodiments, the motherboard includes a plurality of sets of the paired interface units and slots; wherein gaskets are arranged between the interface units and the slots which are arranged in pairs and correspond to part of the interface units and the slots which are arranged in pairs; studs are arranged between the interface units and the slots which are arranged in pairs and correspond to the rest groups in the plurality of groups of interface units and slots which are arranged in pairs.
Some embodiments of the application can respectively set gaskets or studs between different interface units and slots to realize height limiting units, and promote the technical purpose of flexibly setting the technical scheme according to application scenarios. For example, when a hard disk needs to be fixed by a stud, the stud is used as a height limiting unit, and a gasket can be used to realize the function of the height limiting unit in other occasions.
In some embodiments, the interface unit comprises an m.2 interface unit and the slots comprise PCIe expansion slots.
Some embodiments of the application can achieve the technical purpose that the m.2 interface unit and the PCIe expansion slot share PCIe resources in a time-sharing manner.
In a second aspect, some embodiments of the present application provide a motherboard resource sharing method, including: determining an in-place object by acquiring level characteristics of nodes corresponding to an interface unit and a slot which are arranged in pair, wherein the in-place object comprises a hard disk inserted into the interface unit or a plug-in card inserted into the slot; allocating PCIe resources to the determined in-place object; wherein the PCIe resource comprises a PCIe bus.
In a third aspect, some embodiments of the present application provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, may implement the method of the second aspect described above.
In a fourth aspect, some embodiments of the present application provide an information processing apparatus comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor, when executing the program, may implement the method of the second aspect.
In a fifth aspect, some embodiments of the present application provide a computer comprising the motherboard of the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a top view of a motherboard provided in an embodiment of the present application;
fig. 2 is a top view of a motherboard with a plug-in card and a hard disk inserted therein according to an embodiment of the present disclosure;
fig. 3 is a diagram illustrating a relationship between a height-limiting unit and a lower surface of an inserted card according to an embodiment of the present application;
fig. 4 is a schematic diagram illustrating a card insertion state in which a card is inserted after a hard disk is inserted according to an embodiment of the present application;
fig. 5 is a schematic diagram of a connection structure of a part of the in-place detection circuit and the control unit according to an embodiment of the present disclosure;
fig. 6 is a flowchart of a motherboard resource sharing method according to an embodiment of the present application;
fig. 7 is a block diagram of a computer according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Some embodiments of the present application may enable PCIe resources to be fully utilized by detecting the in-place object in real time or periodically and allocating PCIe resources to the in-place object, for example, in some embodiments, the PCIe expansion slot and the m.2nvme interface of the embodiments of the present application may reasonably multiplex PCIe resources.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a motherboard 100 according to some embodiments of the present application. As can be seen from fig. 1, the main board 100 according to some embodiments of the present application includes a plurality of pairs of interface units and slots, for example, fig. 1 shows three pairs of interface units and slots, specifically, a first set of interface units and slots including a first interface unit 101 and a first slot 201, a second set of interface units and slots including a second interface unit 102 and a second slot 202, and a third set of interface units and slots including a third interface unit 103 and a third slot 203. As can be seen from fig. 1, height limiting units (e.g., a first height limiting unit 301 located between the first set of interface units and the slot, a second height limiting unit 302 located between the second set of interface units and the slot, and a third height limiting unit 303 located between the third set of interface units and the slot) are further included between the interface units and the slot included in each set of interface units and the slot. It can also be seen from fig. 1 that some embodiments of the present application provide a respective in-place detection circuit for each set of interface units and slots, specifically, a first in-place detection circuit 401, a second in-place detection circuit 402, and a third in-place detection circuit 403 as shown in fig. 1.
The height limiting single opening of some embodiments of the present application may include a washer or a stud. As an example, a gasket is arranged between the interface units and the slots corresponding to the partial groups in the plurality of groups of interface units and slots arranged in pairs; studs are arranged between the interface units and the slots which are arranged in pairs and correspond to the rest groups in the plurality of groups of interface units and slots which are arranged in pairs. For example, a gasket is disposed between the first interface unit 101 and the first socket 201 included in the first set of interface units and sockets of fig. 1, a stud is disposed between the second interface unit 102 and the second socket 202 included in the second set of interface units and sockets of fig. 1, and a gasket is disposed between the third interface unit and the third socket included in the third set of interface units and sockets.
The following exemplifies the technical solution of some embodiments of the present application with a set of interface units and sockets arranged in pairs.
As shown in fig. 1, some embodiments of the present application provide a motherboard 100, where the motherboard 100 includes: a PCIe resource 600; pairs of interface units and slots (e.g., three pairs or three pairs of interface units and slots of fig. 1). Taking a first set of paired interface units and slots as an example, the first interface unit 101 of fig. 1 is configured to be inserted into a hard disk, and the first slot 201 is configured to be inserted into a plug-in card; a first presence detection circuit 401 configured to obtain a presence signal indicating that one of the hard disk and the add-in card is in place (i.e., a presence detection circuit configured to obtain a presence signal indicating that a presence object is in place), wherein the presence signal is used to indicate that the hard disk is inserted into the first interface unit 101 or that the add-in card is inserted into the first slot 201; control circuitry 500 configured to allocate at least part of the PCIe resources to an in-place object in dependence on the in-place signal; the in-place object includes the hard disk inserted into the first interface unit 101 or the plug-in card inserted into the first slot 201.
In order to determine the specific in-place object at the present moment, in some embodiments of the present application, the first in-place detection circuit 401 is configured to set two mutually exclusive in-place signals for inserting the hard disk into the first interface unit 101 and inserting the add-in card into the first slot 201, respectively. For example, the corresponding bit signal inserted into the hard disk is at a high level, and the corresponding bit signal inserted into the plug-in card is at a low level. For example, the two mutually exclusive in-bit signals include a high level signal and a low level signal, respectively.
In some embodiments, the height limiting unit comprises: the hard disk drive comprises a stud or a gasket, wherein the stud is also used for fixing one end of the hard disk. In some embodiments, the interface unit comprises an m.2 interface unit and the slots comprise PCIe expansion slots.
The height characteristics of the height-limiting unit are exemplarily described below with reference to fig. 2 and 3, and the on-site detection circuit is not shown in the motherboard of fig. 2 for the sake of simplicity and clarity of the drawing, but it should be understood by those skilled in the art that the on-site detection circuit detects an on-site object after inserting a plug-in card into the interface unit or the slot under the teaching and teaching of fig. 1.
As shown in fig. 2, the difference between fig. 2 and fig. 1 is that part of the interface unit of fig. 2 is inserted into the hard disk, and part of the slot of fig. 2 is inserted into the plug-in card. Specifically, a first interface unit 101 of the first set of paired interface units and slots of fig. 2 is inserted into the hard disk 111, a second slot 202 of the second set of paired interface units and slots is inserted into the first add-in card 212, a third interface unit 103 of the third set of paired interface units and slots is inserted into the second hard disk 113, and a third slot is inserted into the second add-in card 213.
In some embodiments of the present application, the control circuit 500 obtains, by using the first in-place detection circuit 401 shown in fig. 1, that only the first interface unit 101 in the first group of interface units and slots is inserted into the hard disk at the current time, that is, the in-place object in the first group of interface units and slots is the hard disk 111, and then the control circuit 500 allocates the PCIe resource 600 to the hard disk 111 and the first interface unit 101 where the hard disk 111 is located (for example, the solid line in fig. 2 indicates the allocation situation of the PCIe resource in the first group of interface units and slots at the current time).
In some embodiments of the present application, the control circuit 500 obtains, by the second in-place detection circuit 402 shown in fig. 1, that only the second slot 202 of the second group of interface units and slots is inserted with a hard disk at the current time (and the second interface unit 102 set corresponding to the second group of interface units and slots is not inserted with a hard disk), that is, the in-place object in the second group of interface units and slots is the add-in card 212, and then the control circuit 500 allocates the PCIe resource 600 to the add-in card 212 and the second slot 202 in which the add-in card is located (for example, the solid line in fig. 2 indicates the allocation situation of the PCIe resource in the second group of interface units and slots at the current time).
It is to be understood that the height-limiting unit in some embodiments of the present application is configured to be disposed between the interface unit and the slot, and the height-limiting unit includes an upper surface contacting a lower surface of the card after the card is inserted into the slot. For example, if the second set of interface units and the second slot 202 of the second set of interface units and the first card 212 are inserted and the second interface unit 102 is not inserted into the hard disk, the left view of the corresponding motherboard 100 is shown in fig. 3. Fig. 3 shows motherboard 100 including backplane 104, second slot 202 located above backplane 104, first card 212 inserted into second slot 202, and height-limiting unit 302. it can be seen from fig. 3 that after first card 212 is inserted into second slot 202, the lower surface of first card 212 contacts the upper surface of height-limiting unit 302, i.e. the lower surface of first card is very close to the upper surface of height-limiting unit.
The control circuit 500 according to some embodiments of the present application obtains, through the third presence detection circuit 403 shown in fig. 1, the current hard disk of the third interface unit 103 in the third group of interface units and slots, and the second add-in card 213 inserted into the third slot 203 paired with the third interface unit 103 cannot be detected by the presence detection circuit because it is not inserted in place. The control circuit 500 will allocate PCIe resources 600 to the second hard disk 113 and the third interface unit 103 where it is located (without allocating PCIe resources to the third slot and the second add-in card 213 inserted in the third slot, as shown by the solid line in fig. 2). It should be noted that fig. 2 shows, by solid lines, that PCIe resources are allocated to the corresponding hard disk or add-in card, and shows, by dotted lines, that PCIe resources are not provided to the corresponding interface unit or slot and the inserted object.
In some embodiments, the motherboard 100 of some embodiments of the present application includes a height limiting unit configured to be disposed between the paired interface unit and the slot, and a sum of heights of the height limiting unit and a hard disk inserted into the interface unit is greater than a height of a lower surface of the card after the card is inserted into the slot. These embodiments are illustrated below in conjunction with fig. 2 and 4. As shown in fig. 2, when a second hard disk 113 is inserted into a third interface unit 103 and a second add-in card 213 is inserted into a third slot 203 in a third set of interface units and slots according to some embodiments of the present application, a left or right view of the motherboard 100 is shown in fig. 4. As can be seen from fig. 4, the second card 213 cannot be inserted into the third slot 203 because the sum of the heights of the third height limiting unit 303 and the second hard disk 113 is greater than the height of the lower surface of the second card 213 inserted into the third slot 203. Therefore, if the third presence detecting circuit is used for detection, the detected presence object is the second hard disk 113 inserted by the third interface unit 303. Accordingly, the control circuit 500 allocates the PCIe resource 600 to the second hard disk 113 and the third interface unit 103 where it is located (as the solid line in fig. 2 indicates the allocation of the PCIe resource in the third group of interface units and slots at the present moment), and the third slot and the second add-in card 213 thereon cannot be allocated to the PCIe resource. It should be noted that, if the third interface unit 103 is not inserted into the second hard disk 113, the corresponding third slot 203 may be inserted into the add-in card 213, that is, after the third slot 203 is inserted into the add-in card 213, the lower surface of the add-in card 213 is located above the third height-limiting unit 303.
A schematic diagram of a portion of the connections of the control circuit 500 and the presence detection circuit is illustrated below in conjunction with fig. 5.
The interface unit of some embodiments of the present application is an interface unit that can be inserted into an m.2nvme hard disk, and the slot is an expansion slot that can be inserted into a pci ex4 plug-in card. The in-place signals inserted into the M.2NVMe hard disk and the PCIex4 plug-in card can be set to be high-level and low-level signals respectively. That Is, when the interface unit (e.g., m.2nvme interface) Is plugged into the hard disk, the voltage signal of the Is _ m.2nvme _ ok node shown in fig. 5 Is pulled low and becomes low, so that the presence detection circuit detects the presence signal of the hard disk, the control circuit 500 uses the PCIe resource to the interface unit plugged into the m.2nvme hard disk, and the corresponding slot (e.g., PCIe expansion slot) cannot be used; when a plug-in card Is inserted into a slot (e.g., PCIe expansion slot), the signal of the Is _ pci 4_ ok node in fig. 5 Is pulled high and becomes high, the presence detection circuit detects the plug-in card presence signal, the control circuit 500 gives PCIe resources to the slot of the PCIe ex4, and the corresponding interface unit cannot be used. The presence detection circuit of fig. 5 further includes a first resistor R1, a second resistor R2, and a third resistor R3, wherein GND represents ground. According to some embodiments of the present application, it is determined, through two mutually exclusive in-place signal detections, whether an interface unit in a pair of an interface unit and a slot or the slot needs to occupy PCIe resources. Some embodiments of the present application are designed on the motherboard structure to ensure that one of the paired interface units and the sockets is connected (refer to the height limiting unit in the text specifically). That is, the height-limiting unit (e.g., a stud) for supporting a hard disk on the interface unit of some embodiments of the present application must be higher than the socket (e.g., PCIe expansion socket) and just touch the bottom of the paddle card. Therefore, some embodiments of the present application can normally and individually install the hard disk of the interface unit through the height limiting unit; meanwhile, when the interface unit is not inserted into the hard disk, the PCIe plug-in card can be normally inserted in the expansion slot in place, and if the interface unit is provided with the hard disk of the m.2nvme interface, the PCIe plug-in card is inserted, and the PCIe plug-in card cannot be inserted in place (as shown in fig. 4).
Some embodiments of the application fully utilize the PCIe resources that the CPU can provide, can adaptively adjust the PCIe resources, and reasonably allocate the PCIe resources according to whether a hard disk or a plug-in card is installed.
As shown in fig. 6, some embodiments of the present application provide a motherboard resource sharing method, where the method includes: s101, determining an in-place object by acquiring level characteristics of nodes corresponding to an interface unit and a slot which are arranged in pair, wherein the in-place object comprises a hard disk inserted into the interface unit or a plug-in card inserted into the slot; s102, distributing PCIe resources to the determined in-place objects; wherein the PCIe resource comprises a PCIe bus.
It should be noted that, reference may be made to the above description for processing details related to each step in the motherboard resource sharing method, and redundant description is not repeated here.
Some embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, may implement the method described in fig. 6.
Some embodiments of the present application provide an information processing apparatus comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor when executing the program may implement the method of fig. 6.
As shown in fig. 7, some embodiments of the present application further provide a computer, which includes the motherboard 100 of fig. 1, on which a memory 510, a processor 520, and a bus 530 are further disposed. For other units included in the motherboard 100, please refer to fig. 1 and the related description, which are not described herein for further details.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (8)
1. A motherboard, comprising:
a PCIe resource;
the interface unit and the slot are arranged in pair, the interface unit is configured to be inserted into a hard disk, and the slot is configured to be inserted into an insertion card;
the height limiting unit is configured to be arranged between the interface unit and the slot which are arranged in pair, and the sum of the height limiting unit and the height of a hard disk inserted into the interface unit is larger than the height of the lower surface of the plug-in card after the plug-in card is inserted into the slot;
the on-site detection circuit is configured to acquire an on-site signal of an on-site object, wherein the on-site object comprises the hard disk inserted into the interface unit or the plug-in card inserted into the slot;
control circuitry configured to allocate at least part of the PCIe resources to the in-place object in dependence on the in-place signal.
2. The motherboard of claim 1, wherein the presence detection circuit is configured to set two mutually exclusive presence signals for insertion of the hard disk into the interface unit and insertion of the add-in card into the slot, respectively.
3. A motherboard according to claim 2, wherein said two mutually exclusive in-place signals comprise a high level signal and a low level signal respectively.
4. The motherboard of claim 1, wherein the height-limiting unit includes an upper surface that contacts a lower surface of the card after the card is inserted into the slot.
5. A motherboard according to claim 1, characterized in that the height limiting unit comprises: the hard disk drive comprises a stud or a gasket, wherein the stud is also used for fixing one end of the hard disk.
6. The motherboard of claim 1, wherein the motherboard includes a plurality of sets of the paired interface units and sockets; wherein,
gaskets are arranged between the interface units and the slots which are arranged in pairs and correspond to part of the interface units and the slots which are arranged in pairs;
studs are arranged between the interface units and the slots which are arranged in pairs and correspond to the rest groups in the plurality of groups of interface units and slots which are arranged in pairs.
7. The motherboard of claim 1, wherein the interface unit comprises an m.2 interface unit and the slots comprise PCIe expansion slots.
8. A computer, characterized in that the computer comprises a motherboard according to any of claims 1-7, and a memory and a processor located on the motherboard.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979423A (en) * | 2005-11-30 | 2007-06-13 | 迈普（四川）通信技术有限公司 | Multi-processor load distribution-regulation method |
| CN103455379A (en) * | 2013-09-05 | 2013-12-18 | 华为技术有限公司 | Resource allocation method and system |
| CN104503933A (en) * | 2014-12-03 | 2015-04-08 | 浪潮集团有限公司 | PCIE automatic switching design based on multi-path server system |
| CN106980588A (en) * | 2016-01-18 | 2017-07-25 | 中兴通讯股份有限公司 | A kind of equipment heat treatment method and device |
| CN107408095A (en) * | 2015-01-28 | 2017-11-28 | 惠普发展公司，有限责任合伙企业 | The redirection of channel resource |
| CN108763124A (en) * | 2018-05-23 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of PCIE Riser cards |
| CN109976475A (en) * | 2019-05-15 | 2019-07-05 | 苏州浪潮智能科技有限公司 | A kind of fixed structure and heat dissipating method being conducive to M.2 Hard disk heat radiation |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201711305A (en) * | 2015-09-10 | 2017-03-16 | 宜鼎國際股份有限公司 | M.2 interface connector and M.2 interface seat insertedly provided thereof |
| KR20170040897A (en) * | 2015-10-06 | 2017-04-14 | 주식회사 스토리지안 | Ssd doubler with multiple interface ports and the multi-device bay system for it |
| CN107724286A (en) * | 2017-11-22 | 2018-02-23 | 高月江 | A kind of adjustable road height-limiting frame of road construction |
-
2020
- 2020-08-17 CN CN202010828595.5A patent/CN111984556B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979423A (en) * | 2005-11-30 | 2007-06-13 | 迈普（四川）通信技术有限公司 | Multi-processor load distribution-regulation method |
| CN103455379A (en) * | 2013-09-05 | 2013-12-18 | 华为技术有限公司 | Resource allocation method and system |
| CN104503933A (en) * | 2014-12-03 | 2015-04-08 | 浪潮集团有限公司 | PCIE automatic switching design based on multi-path server system |
| CN107408095A (en) * | 2015-01-28 | 2017-11-28 | 惠普发展公司，有限责任合伙企业 | The redirection of channel resource |
| CN106980588A (en) * | 2016-01-18 | 2017-07-25 | 中兴通讯股份有限公司 | A kind of equipment heat treatment method and device |
| CN108763124A (en) * | 2018-05-23 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of PCIE Riser cards |
| CN109976475A (en) * | 2019-05-15 | 2019-07-05 | 苏州浪潮智能科技有限公司 | A kind of fixed structure and heat dissipating method being conducive to M.2 Hard disk heat radiation |
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