CN111984486A

CN111984486A - CPU network interface performance test board, test system and test method

Info

Publication number: CN111984486A
Application number: CN202010991816.0A
Authority: CN
Inventors: 孙瑛琪; 杨晓君; 张腾; 袁飞; 孙浩天
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-09-18
Filing date: 2020-09-18
Publication date: 2020-11-24

Abstract

The embodiment of the application discloses a CPU network interface performance test board, a test system and a test method, relates to the technical field of boards, and aims to improve the accuracy of testing the CPU network interface performance. The CPU network interface performance test board card comprises: the system comprises a printed circuit board, a first connecting finger, a secondary driving unit and a first group of optical modules, wherein the printed circuit board is provided with the first connecting finger, the secondary driving unit and the first group of optical modules; the first golden finger is provided with a first group of network pins, the first group of network pins are connected with a first row of terminals, the secondary driving unit is respectively connected with a second row of terminals and a third row of terminals, and the first group of optical modules is connected with a fourth row of terminals; the first row of terminals is adjacent to the second row of terminals, and the third row of terminals is adjacent to the fourth row of terminals. The method and the device are suitable for testing the performance of the CPU network interface.

Description

CPU network interface performance test board, test system and test method

Technical Field

The application relates to the technical field of board cards, in particular to a board card for testing the performance of a CPU network interface, a testing system and a testing method.

Background

With the technical development of the CPU chip design, the high-speed interface integrated on the CPU can be configured into different protocol types through software, so as to implement different interface functions, that is, the same signal can be configured into PCIe, can be configured into a network (SFI, KR, etc.), and can also be configured into a SATA storage interface, etc.

In the final product, generally, hardware is designed to have a fixed interface function, software is configured to have a corresponding interface protocol, but in the development of a CPU, a plurality of tests are required to be performed on a CPU network interface to evaluate the performance of the CPU network interface, in the existing test technology, the CPU network interface is led to a PCIe slot and is tested by means of a PCIe standard test fixture, but only an SMA interface is arranged on the PCIe standard test fixture, and signal quality test and loopback test can be performed through SMA, but because an optical module is not arranged on the PCIe test fixture, signal quality test and loopback test under the condition that an optical module is arranged on a test link cannot be performed by means of the optical module test fixture, and service pressure test cannot be performed, and evaluation of the performance of the CPU network interface requires the plurality of tests to correspondingly obtain signal quality and network performance indexes, so as to perform comprehensive evaluation, because the test items performed in the prior art are less, the accuracy of testing the performance of the CPU network interface in the prior art is lower.

Disclosure of Invention

In view of this, embodiments of the present application provide a board for testing the performance of a CPU network interface, a test system, and a test method, which are convenient for improving the accuracy of testing the performance of the CPU network interface.

The embodiment of the application provides a CPU network interface performance test board, including: the system comprises a printed circuit board, a first connecting finger, a secondary driving unit and a first group of optical modules, wherein the printed circuit board is provided with the first connecting finger, the secondary driving unit and the first group of optical modules; the first golden finger is provided with a first group of network pins, the first group of network pins are connected with a first row of terminals, the secondary driving unit is respectively connected with a second row of terminals and a third row of terminals, and the first group of optical modules is connected with a fourth row of terminals; the first row of terminals is adjacent to the second row of terminals, and the third row of terminals is adjacent to the fourth row of terminals.

According to a specific implementation manner of the embodiment of the present application, the first group of network pins includes N groups of sub-network pins, two input pins of each group of sub-network pins are respectively and correspondingly connected to the first terminal and the second terminal of the first row of terminals, and two output pins of each group of sub-network pins are respectively and correspondingly connected to the third terminal and the fourth terminal of the first row of terminals; wherein N is an integer of 1 or more.

According to a specific implementation manner of the embodiment of the application, the secondary driving unit comprises a first secondary driving unit and a second secondary driving unit, the first secondary driving unit and the second secondary driving unit are arranged on the printed circuit board side by side, and input pins of the first secondary driving unit and output pins of the second secondary driving unit are connected with the second row of terminals; and the output pin of the first secondary driving unit is connected with the input pin of the second secondary driving unit and the third row of terminals.

According to a specific implementation manner of the embodiment of the application, the secondary driving unit further includes a third secondary driving unit and a fourth secondary driving unit, the third secondary driving unit and the fourth secondary driving unit are arranged on the printed circuit board side by side with the first secondary driving unit, and input pins of the third secondary driving unit and output pins of the fourth secondary driving unit are connected with the second row of terminals; and the output pin of the third secondary driving unit and the input pin of the fourth secondary driving unit are connected with the third row of terminals.

According to a specific implementation manner of the embodiment of the present application, the first group of optical modules includes K optical modules, the K optical modules are arranged on the printed circuit board side by side, two input ends of each optical module are respectively connected to the first terminal and the second terminal in the fourth row of terminals, and two output ends of each optical module are respectively connected to the third terminal and the fourth terminal in the fourth row of terminals; wherein K is an integer of 1 or more.

According to a specific implementation manner of the embodiment of the application, the printed circuit board is further provided with a first system management bus, the first system management bus is connected with a first conversion chip, and the first conversion chip is correspondingly connected with each optical module in the first group of optical modules respectively after the first system management bus is divided into N paths.

According to a specific implementation manner of the embodiment of the application, the first system management bus is further connected with a first conversion I/O interface chip and a second conversion I/O interface chip; the I/O interface of the first conversion I/O interface chip is connected with an in-place signal end, a transmission enabling control signal end, a transmission failure indication signal end and/or a reception loss indication signal end of the first group of optical modules; and the I/O interface of the second conversion I/O interface chip is connected with the LED indicator lamp.

According to a specific implementation manner of the embodiment of the application, the secondary driving unit is further connected to the first system management bus.

According to a specific implementation manner of the embodiment of the application, one end of the first system management bus, which is close to the first golden finger, is connected with a first jump cap selectable connector; a second jump cap selectable connector and a third jump cap selectable connector are arranged on the printed circuit board and adjacent to the first jump cap selectable connector; the second jump cap selectable connector is connected with a first pin of the first golden finger, the third jump cap selectable connector is connected with a second pin of the first golden finger, the first pin of the first golden finger is used for being connected to a substrate management controller on a mainboard, and the second pin of the first golden finger is used for being connected to a CPU on the mainboard.

According to a specific implementation manner of the embodiment of the application, a second golden finger and a second group of optical modules are arranged on the printed circuit board; and a second group of network pins are arranged on the second golden finger and connected with the second group of optical modules.

According to a specific implementation manner of the embodiment of the present application, the second group of network pins includes Q groups of sub-network pins, the second group of optical modules includes Q optical modules, each group of sub-network pins is correspondingly connected to each optical module, two input pins of each group of sub-network pins are respectively correspondingly connected to two output terminals of the corresponding optical module, and two output pins of each group of sub-network pins are respectively correspondingly connected to two input terminals of the corresponding optical module; wherein Q is an integer of 1 or more.

According to a specific implementation manner of the embodiment of the application, the printed circuit board is further provided with a second system management bus, the second system management bus is connected with a second conversion chip, and the second conversion chip is correspondingly connected with each optical module in the second group of optical modules respectively after the second system management bus is divided into N paths.

According to a specific implementation manner of the embodiment of the application, a third-to-I/O interface chip and a fourth-to-I/O interface chip are further connected to the second system management bus; the I/O interface of the third conversion I/O interface chip is connected with the in-place signal end, the transmission enabling control signal end, the transmission failure indication signal end and/or the reception loss indication signal end of the second group of optical modules; and the I/O interface of the fourth conversion I/O interface chip is connected with the LED indicator lamp.

According to a specific implementation manner of the embodiment of the application, one end of the second system management bus, which is close to the second gold finger, is connected to the fourth hop-cap optional connector; a fifth jump cap selectable connector and a sixth jump cap selectable connector are arranged on the printed circuit board and adjacent to the fourth jump cap selectable connector; the fifth jump cap selectable connector is connected with the first pin of the second golden finger, the sixth jump cap selectable connector is connected with the second pin of the second golden finger, the first pin of the second golden finger is used for being connected to a substrate management controller on a mainboard, and the second pin of the second golden finger is used for being connected to a CPU on the mainboard.

According to a specific implementation manner of the embodiment of the present application, the first group of optical modules and the second group of optical modules are a plurality of SFP + optical modules arranged side by side, respectively.

The present application further provides a CPU network interface performance test system, including: the CPU network interface performance testing board is inserted into the PCIE slot, wherein the CPU network interface performance testing board is the CPU network interface performance testing board in any one of the implementation modes.

The application also provides a method for testing the performance of the CPU network interface, which comprises the following steps: a CPU network port on a mainboard sends network test data to a first group of optical modules on a test board card inserted in a PCIE slot on the mainboard to perform service pressure test, loop test and/or signal quality test; the test board card is the CPU network interface performance test board card in any one of the above implementation modes; the first row of terminals and the fourth row of terminals on the test board are connected, so that the first group of network pins are connected with the first group of optical modules; and determining the performance of the CPU network interface according to the test result.

According to a specific implementation manner of the embodiment of the application, the method further includes: and the first row of terminals and the second row of terminals on the test board card are connected, and the third row of terminals and the fourth row of terminals are connected, so that the secondary drive unit is connected between the first group of network pins and the first group of optical modules, and a service pressure test, a loop test and/or a signal quality test with the secondary drive unit are/is carried out.

According to a specific implementation manner of the embodiment of the application, the method further includes: monitoring status information of the first group of optical modules or the second group of optical modules.

According to the CPU network interface performance test board card, the test system and the test method provided by the embodiment of the application, a first golden finger, a secondary driving unit and a first group of optical modules are arranged on a printed circuit board; the first golden finger is provided with a first group of network pins, the first group of network pins are connected with a first row of terminals, the secondary driving unit is respectively connected with a second row of terminals and a third row of terminals, and the first group of optical modules is connected with a fourth row of terminals; the first row of terminals and the second row of terminals are arranged adjacently, the third row of terminals and the fourth row of terminals are arranged adjacently, the first group of network pins of the test board card of the embodiment are connected with the corresponding pins on the mainboard, and the first group of network pins are connected with the first group of optical modules, so that the signal quality test, the loop test and the service pressure test under the condition that the optical modules exist on a test link can be realized, the loop test and the signal quality test can be carried out by the first row of terminals, and the performance of the CPU network interface is evaluated according to the test results of a plurality of test items, so that the accuracy of testing the performance of the CPU network interface is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a CPU network interface performance test board according to an embodiment of the present application;

fig. 2 is a schematic diagram of a link connection of a CPU network interface performance test board according to an embodiment of the present application;

fig. 3 is an SMBus link topology diagram in a test board according to an embodiment of the present application;

fig. 4 is an SMBus link topology diagram in a test board according to another embodiment of the present application;

fig. 5 is a schematic flowchart of a method for testing the performance of a CPU network interface according to an embodiment of the present application.

Detailed Description

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1 and fig. 2, the CPU network interface performance test board of this embodiment may include:

the system comprises a printed circuit board 1, wherein a first golden finger 2, a secondary driving unit 3 and a first group of optical modules 4 are arranged on the printed circuit board 1; the first golden finger 2 is provided with a first group of network pins 5, the first group of network pins 5 are connected with a first row of terminals 6, the secondary driving unit 3 is respectively connected with a second row of terminals 7 and a third row of terminals 8, the first group of optical modules 4 are connected with a fourth row of terminals 9, the first row of terminals 6 are arranged adjacent to the second row of terminals 7, and the third row of terminals 8 are arranged adjacent to the fourth row of terminals 9.

The CPU network interface performance may include a driving capability of the CPU network interface.

Printed circuit boards 1(PCB boards), also known as Printed circuit boards, are providers of electrical connections for electronic components. A printed circuit board in general may refer to a bare board, i.e. a circuit board without mounted components.

The first gold Finger 2, which may be composed of a plurality of gold-plated conductive contacts, is called "gold Finger" or Finger because the surface is plated with gold and the conductive contacts are arranged like fingers, wherein the conductive contacts may also be called pins. The size and shape of the gold Finger can be determined according to actual conditions, and in one example, the gold Finger 2 is in a standard PCIE Finger form. The conductive contact pads on the first gold finger 2 may be configured as network pins that may transmit high speed network data, and in one example, the first set of network pins 5 on the gold finger 2 may be XGBE pins.

The first group of network pins 5 may include a group of sub-network pins, and may also include multiple groups of network pins, in one example, the first group of network pins includes N groups of sub-network pins, two input pins of each group of sub-network pins are respectively connected to the first terminal and the second terminal of the first row of terminals, and two output pins of each group of sub-network pins are respectively connected to the third terminal and the fourth terminal of the first row of terminals; wherein N is an integer of 1 or more.

A secondary driving unit 3, which may include a retimer Re-timer and a driver Re-driver; in the signal transmission of a high-speed serial channel, the Re-driver and the Re-timer can be used for ensuring the quality of the signal transmission; re-timer is to reconstruct the signal of the previous stage and then send out, produce the clock, and has recovered the data; the Re-driver only enhances the original signal and supplements energy in the physical layer.

The first group of optical modules 4 is configured to transmit data sent by the motherboard CPU to an external device, or receive data sent by the external device, and may also be configured to transmit data sent by the motherboard CPU to the test board card of this embodiment again. The first set of light modules may comprise one or more than two light modules.

The first row of terminals 6, the second row of terminals 7, the third row of terminals 8 and/or the fourth row of terminals 9 may be terminals on a connector, and in one example, the first row of terminals 6, the second row of terminals 7, the third row of terminals 8 and/or the fourth row of terminals 9 may be terminals on a radio frequency connector, and may specifically be terminals of an SMA radio frequency coaxial connector.

The CPU network interface may be configured to a corresponding network protocol for testing, in this embodiment, the CPU network interface is configured to a network protocol corresponding to the optical module, and specifically, the PU network interface may be an SFP + network interface for testing; the performance of the CPU network interface may be determined by signal quality and network performance indicators. The method can be carried out in the following specific situations: 1. the performance test can be carried out when a network interface of a CPU receives and transmits data; 2. the performance test can be carried out when data is received and sent between two network interfaces of a CPU; 3. the performance test can also be carried out when one network interface of one CPU sends data and one network interface of the other CPU receives data; 4. and a performance test of sending data by one network interface of the CPU and evaluating the sent data can be performed.

In the embodiment, a printed circuit board is provided with a first golden finger, a secondary driving unit and a first group of optical modules; the first golden finger is provided with a first group of network pins, the first group of network pins are connected with a first row of terminals, the secondary driving unit is respectively connected with a second row of terminals and a third row of terminals, and the first group of optical modules is connected with a fourth row of terminals; the first row of terminals and the second row of terminals are arranged adjacent to each other, the third row of terminals and the fourth row of terminals are arranged adjacent to each other, signal quality test, loop test and service pressure test under the condition that an optical module is arranged on a test link can be realized by connecting the first group of network pins of the test board card of the embodiment with corresponding pins on the mainboard and connecting the first group of network pins with the first group of optical module, loop test and signal quality test can be further performed by the first row of terminals, and the performance of the CPU network interface can be evaluated according to the test results of a plurality of test items, so that the accuracy of testing the performance of the CPU network interface can be improved The performance of the CPU network interface is evaluated, and other network protocol configured test items can be carried out, that is, one test board supports a plurality of test items, thereby enriching the functions of the test board, and in addition, because the first group of network pins are connected with the first row of terminals, the secondary driving unit is respectively connected with the third row of terminals and the fourth row of terminals, and the first group of optical modules are connected with the fourth row of terminals, thus, the functional modular design of the first group of network pins, the secondary driving unit and the first group of optical modules is realized, so that the above-mentioned modules can be flexibly combined according to test items, and, since the secondary driving unit is integrated, when the test is carried out, the secondary driving unit can be selected to be connected into the test link in series or not according to the test requirement, so that the early-stage evaluation of the whole server product can be facilitated.

The present application further includes a second secondary driving unit, which is substantially the same as the first secondary driving unit, and is different from the first secondary driving unit, wherein the second secondary driving unit includes a first secondary driving unit and a second secondary driving unit, the first secondary driving unit and the second secondary driving unit are disposed on the printed circuit board side by side, and an input pin of the first secondary driving unit and an output pin of the second secondary driving unit are connected to the second row of terminals; and the output pin of the first secondary driving unit is connected with the input pin of the second secondary driving unit and the third row of terminals.

The first secondary driving unit and the second secondary driving unit can be the same type of chip, such as a retimer Re-timer or a driver Re-driver.

In this embodiment, the secondary driving unit includes a first secondary driving unit and a second secondary driving unit, the first secondary driving unit and the second secondary driving unit are arranged on the printed circuit board side by side, and the input pins of the first secondary driving unit and the output pins of the second secondary driving unit are connected to the second row of terminals; the output pins of the first secondary driving unit and the input pins of the second secondary driving unit are connected with the third row of terminals, and when the test board card of the embodiment is used for carrying out loopback test of serially connecting the two secondary driving units, the two secondary driving units can flexibly and respectively process respective input signals.

Another embodiment of the present application is substantially the same as the above embodiments, except that the secondary driving unit of the present embodiment further includes: the third secondary driving unit, the fourth secondary driving unit and the first secondary driving unit are arranged on the printed circuit board side by side, and input pins of the third secondary driving unit and output pins of the fourth secondary driving unit are connected with the second row of terminals; and the output pin of the third secondary driving unit and the input pin of the fourth secondary driving unit are connected with the third row of terminals.

The third secondary driving unit and the fourth secondary driving unit may be the same type of chip, such as a retimer Re-timer or a driver Re-driver, in one example, the first secondary driving unit and the second secondary driving unit may be the retimer Re-timer, and the third secondary driving unit and the fourth secondary driving unit may be the driver Re-driver.

In the embodiment, by arranging the third secondary driving unit and the fourth secondary driving unit, the type of the secondary driving unit realizing specific functions can be selected according to actual conditions during testing, such as selecting a proper scheme in Re-timer and Re-driver.

The present further embodiment is substantially the same as the above embodiments, except that the first group of optical modules 4 of the present embodiment includes K optical modules 40, the K optical modules are arranged on the printed circuit board 1 side by side, two input ends of each optical module 40 are respectively connected to the first terminal and the second terminal in the fourth row of terminals 9, and two output ends of each optical module 40 are respectively connected to the third terminal and the fourth terminal in the fourth row of terminals 9; wherein K is an integer of 1 or more.

The two input ends of each optical module are respectively and correspondingly connected with the first terminal and the second terminal in the fourth row of terminals, and the two output ends of each optical module are respectively and correspondingly connected with the third terminal and the fourth terminal in the fourth row of terminals, so that the test board card of the embodiment can realize transmission of differential signals, specifically, each optical module comprises pins for receiving and sending signals, wherein the received signals and the sent signals are differential signals.

Referring to fig. 3, in order to obtain the internal information of the first group of optical modules, the present application still further embodiment is basically the same as the above embodiment, except that the printed circuit board 1 of the test board of the present embodiment is further provided with a first system management bus, the first system management bus is connected to a first conversion chip 10, and the first conversion chip 10 is correspondingly connected to each optical module in the first group of optical modules 4 after dividing the first system management bus into N paths.

The first System Management Bus (SMBus) provides a control Bus for System and power Management tasks, and with the SMBus System, messages sent and received between devices are all through the SMBus, rather than using separate control lines, which can save the pin count of the devices. Further, using the SMBus, the device may also provide its production information, tell the system its model, part number, etc., save its status for a pending event, report a different class of errors, receive control parameters, and return its status, etc.

The first conversion chip 10 may divide the first system management bus into N paths, where N is greater than or equal to 2; the N optical modules are respectively and correspondingly connected with the optical modules in the first group of optical modules 4, so that when the optical module is used, internal data of each optical module, such as information of the working temperature of the optical module, can be conveniently acquired.

In one example, the first conversion chip may be a system management bus expansion chip, and the specific model may be 9546.

In order to facilitate monitoring of the states of the first group of optical modules and to facilitate visual understanding of the states of the test board, another embodiment of the present application is basically the same as the above embodiment, except that in the test board of the present embodiment, the first system management bus is further connected with a first conversion I/O interface chip 11 and a second conversion I/O interface chip 12; the I/O interface of the first conversion I/O interface chip 11 is connected with an in-place signal end, a transmission enabling control signal end, a transmission failure signal end and/or a reception loss signal end of the first group of optical modules 4; the I/O interface of the second conversion I/O interface chip 12 is connected with an LED indicator light 13.

The first I/O interface chip 11 may be a chip with an input/output expansion function, and specifically may be a 9555 chip, and may connect an I/O interface of the first I/O interface chip to in-place (MODABS), transmission enable control (TXDIS), transmission failure indication (TXFAULT), and reception loss indication (RXLOS) signal pins of the first group of optical modules 4, so as to monitor the status of the first group of optical modules 4.

The second conversion I/O interface chip 12 may be a chip with an input/output expansion function, and specifically may be a 9555 chip; the I/O interface of the second I/O interface chip 12 is connected to the LED indicator 13, and the working status of the test board can be indicated by the on/off status of one LED indicator, the color of the LED indicator, the on/off status of two or more LED indicators, the color of the LED indicator, and different combination statuses thereof, such as whether the board card is working normally and what fault occurs when a fault occurs, and the statuses can be associated with the status of the indicator, such as green when working normally, red when abnormal occurs, or normal when flashing occurs, and abnormal when not flashing occurs.

To facilitate storing and reading the test information, in one example, a first eeprom is also coupled to the first system management bus.

The first Electrically Erasable Programmable Read Only Memory (EEPROM) is a memory chip with no data loss after power failure, and can store board information in the EEPROM so as to read the board information, and further, can configure an interface protocol supported by the board as a CPU network interface protocol according to the board information.

In order to facilitate and flexibly configure the secondary driving unit, in one example, the secondary driving unit 3 is further connected to the first system management bus.

In the present embodiment, by connecting the secondary drive unit 3 to the first system management bus, the performance of the secondary drive unit can be configured.

In order to flexibly select the configuration management of the equipment connected on the first system management bus by the CPU or the baseboard management controller, one end of the first system management bus close to the first golden finger 2 is connected with the first jump cap optional connector 13; a second jumper cap optional connector 15 and a third jumper cap optional connector 16 are arranged on the printed circuit board 1 and adjacent to the first jumper cap optional connector 14; the second jump cap selectable connector 15 is connected with the first pin 2a of the first golden finger 2, the third jump cap selectable connector 16 is connected with the second pin 2b of the first golden finger 3, the first pin 2a of the first golden finger 2 is used for being connected to a substrate management controller on a mainboard, and the second pin 2b of the first golden finger 3 is used for being connected to a CPU on the mainboard.

The PCIE Finger standard defines only one SMBUS signal, which can be connected to the CPU or BMC. There are also a plurality of Reserved (RSVD, Reserved) but undefined pins on the PCIE Finger, and some motherboards define part of the RSVD pins as SMBUS. In an example, the first pin 2a and the second pin 2b on the test board card of the present embodiment may define RSVD pins on a gold finger as an SMBUS signal pin.

The first jumper alternative connector 14, the second jumper alternative connector 15, and/or the second jumper alternative connector 16 may be 3pin connectors.

A Baseboard Management Controller (BMC) has monitoring and control functions, and the operation objects are system hardware, for example, by monitoring the temperature, voltage, fan, power supply, etc. of the system and performing corresponding adjustment work, so as to ensure that the system is in a healthy state. The information and log records of various hardware can be recorded for prompting the user and positioning of subsequent problems; the BMC is an independent system, and does not depend on other hardware (such as a CPU, a memory, and the like) on the system, nor on the BIOS, the OS, and the like (but the BMC may interact with the BIOS and the OS, which may have a better platform management effect, and system management software under the OS may cooperate with the BMC to achieve a better management effect).

When in use, the first jumper cap optional connector 14 and the second jumper cap optional connector 15 can be connected through a jumper cap according to requirements, and the first jumper cap optional connector 14 and the third jumper cap optional connector 16 can also be connected through a jumper cap.

The test board card of this embodiment may be in a PCIE card form, and in order to be conveniently applied to the inside of the standard chassis, the test board card of this embodiment may be designed according to the size of the standard PCIE card, for example, the test board card has the same size as a full-height half-length card of the standard PCIE, and further, in order to save cost and be closer to the actual situation, see fig. 1, an embodiment of the present application is basically the same as the above embodiment, but the difference is that a second gold finger 17 and a second group of optical modules 18 are arranged on the printed circuit board 1; wherein, a second group of network pins 19 is arranged on the second golden finger 17, and the second group of network pins 19 is connected with a second group of optical modules 18.

The second group of network pins may include Q groups of sub-network pins, the second group of optical modules includes Q optical modules 180, each group of sub-network pins is correspondingly connected to each optical module, wherein two input pins of each group of sub-network pins are respectively correspondingly connected to two output terminals of the corresponding optical module, and two output pins of each group of sub-network pins are respectively correspondingly connected to two input terminals of the corresponding optical module; wherein Q is an integer of 1 or more.

The second group of network pins 19 may be XGBE high-speed pins, and the two input pins of each group of sub-network pins are respectively and correspondingly connected to the two output ends of the corresponding optical module, and the two output pins of each group of sub-network pins are respectively and correspondingly connected to the two input ends of the corresponding optical module, so that the test board of this embodiment can implement transmission of differential signals, specifically, each group of sub-network pins includes a pin for receiving and sending signals, where the received signal and the sent signal are both differential signals.

Referring to fig. 4, in order to obtain the internal information of the second group of optical modules, the present application still further embodiment is basically the same as the above embodiment, except that the printed circuit board 1 of the test board of the present embodiment is further provided with a second system management bus, the second system management bus is connected to a second conversion chip 20, and the second conversion chip 20 is correspondingly connected to each optical module in the second group of optical modules 18 after dividing the second system management bus into N paths.

The second System Management Bus (SMBus) provides a control Bus for System and power Management tasks, and with the SMBus System, messages sent and received between devices are all through the SMBus, rather than using separate control lines, which can save the pin count of the devices. Further, using the SMBus, the device may also provide its production information, tell the system its model, part number, etc., save its status for a pending event, report a different class of errors, receive control parameters, and return its status, etc.

The second conversion chip 20 may divide the second system management bus into N paths, where N is greater than or equal to 2; the N optical modules are connected to the corresponding optical modules in the second group of optical modules 18, so that internal data of each optical module, such as operating temperature of the optical module, can be conveniently obtained during use.

In one example, the second conversion chip 20 may be a system management bus expansion chip, and the specific model may be 9546.

In order to facilitate monitoring the state of the second group of optical modules 18 and visually knowing the state of the test board, a further embodiment of the present application is basically the same as the above embodiments, except that in the test board of the present embodiment, the second system management bus is further connected with a third-to-I/O interface chip 21 and a fourth-to-I/O interface chip 22; the I/O interface of the third conversion I/O interface chip 21 is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and the reception loss indication signal terminal of the second group optical module 18; the I/O interface of the fourth-turn I/O interface chip 22 is connected with an LED indicator lamp 23.

The third conversion I/O interface chip 21 may be a chip with an input/output expansion function, specifically, a 9555 chip, and may connect an IO interface of the third conversion I/O interface chip 21 to in-place (MODABS), transmission enable control (TXDIS), transmission failure (TXFAULT), and reception loss (RXLOS) signal pins of the second group of optical modules 18, so as to monitor states of the second group of optical modules 18.

The fourth conversion I/O interface chip 22 may be a chip with an input/output expansion function, and specifically may be a 9555 chip; the I/O interface of the fourth conversion I/O interface chip 22 is connected to the LED indicator 23, and the working status of the test board can be indicated by the on/off status of one LED indicator, the color of the LED indicator, the on/off status of two or more LED indicators, the color of the LED indicator, and different combinations thereof, such as whether the board card is working normally and what fault occurs when a fault occurs, and these statuses can be associated with the status of the indicator, such as green when working normally, red when abnormal occurs, or normal when flashing occurs, and abnormal when not flashing occurs.

In order to store and read the test information, in one example, a second electrified erasable programmable read-only memory is connected to the second system management bus.

The second Electrically Erasable Programmable Read Only Memory (EEPROM) is a memory chip with no data loss after power failure, and can store the board information in the EEPROM so as to read the board information, and further, can configure an interface protocol supported by the board as a CPU network interface protocol according to the board information.

In order to flexibly select the configuration management of the equipment connected on the second system management bus by the CPU or the baseboard management controller, one end of the second system management bus close to the second golden finger 17 is connected with the fourth jump cap optional connector 24; a fifth jump cap option connector 25 and a sixth jump cap option connector 26 are arranged on the printed circuit board 1 adjacent to the fourth jump cap option connector 24; the fifth jump cap selectable connector 25 is connected to the first pin 17a of the second gold finger 17, the sixth jump cap selectable connector 26 is connected to the second pin 17b of the second gold finger 17, the first pin 17a of the second gold finger 17 is used for being connected to a substrate management controller on a motherboard, and the second pin 17b of the second gold finger 17 is used for being connected to a CPU on the motherboard.

Fourth jumper alternative connector 24, fifth jumper alternative connector 25, and/or sixth jumper alternative connector 26 may be 3pin connectors.

In one example, the first group of optical modules and the second group of optical modules are a plurality of SFP + optical modules arranged side by side, respectively.

The SFP + optical module can be an enhanced small pluggable transceiver optical module, and is provided with an interface for plugging an optical cable, and the optical cable can be inserted into the interface to test the performance of the CPU network interface.

Referring to fig. 1, an embodiment of the present application further provides a CPU network interface performance testing system, including: the system comprises a mainboard and a CPU network interface performance test board card, wherein the mainboard is provided with a CPU chip and a PCIE slot connected with the CPU chip, and the CPU network interface performance test board card is inserted into the PCIE slot, wherein the CPU network interface performance test board card is the CPU network interface performance test board card in the embodiment.

The main board is called main board (main board), system board (system board) or mother board (thermal board), the main board is generally rectangular circuit board, on which the main circuit system forming the computer is mounted, and generally there are elements of BIOS chip, I/O control chip, keyboard and panel control switch interface, indicator lamp plug-in unit, expansion slot, main board and direct current power supply plug-in unit of plug-in card and CPU chip socket, etc.; the CPU is mounted in a CPU chip socket.

In one example, a PCIE slot on the motherboard is a PCIE slot configurable to be a protocol corresponding to the CPU network interface; in another example, the BIOS configures signals of the corresponding PCIe slot into a protocol corresponding to the optical module, and may specifically be a protocol corresponding to SFP +.

In this embodiment, a CPU chip and a PCIE slot connected to the CPU chip are disposed on a motherboard, and the CPU network interface adaptability test board is inserted into the PCIE slot, where the CPU network interface performance test board is the CPU network interface performance test board described in the foregoing embodiment, and the first group of network pins is connected to the first group of optical modules, so that signal quality test, loop test, and service pressure test under the condition that optical modules are present on a test link can be implemented, and the loop test and the signal quality test can be performed by the first row of terminals.

Referring to fig. 2 and fig. 5, an embodiment of the present application further provides a method for testing performance of a CPU network interface, including:

step 101, a CPU network interface on a mainboard sends network test data to a test board card inserted in a PCIE slot on the mainboard to perform service pressure test, loop test and signal quality test; the test board card is the CPU network interface performance test board card in the embodiment; and the first row of terminals and the fourth row of terminals on the test board are connected so as to connect the first group of network pins with the first group of optical modules.

The CPU network interface can be a CPU network interface configured with a network protocol corresponding to the optical module; network test data, which may include a plurality of data packets; the network test data sent by the CPU network interface of this embodiment may be data sent at a certain rate, such as 100M, 1000M, 10G, and so on.

When a service pressure test is performed, the first group of optical modules in this embodiment receives network test data sent from the CPU network interface, and sends the received network test data sent from the CPU network interface to a test system having a third group of optical modules and a CPU connected to the third group of SFP + optical modules, and according to the above process, after a predetermined time elapses at a certain transmission rate, network performance indexes, such as an error rate, a time delay, and/or a packet loss rate, are determined according to the test data sent by the CPU network interface and the test data received by another CPU network interface.

When a loop-back test is performed, the external input/output port of one optical module in the first group of optical modules is connected through an optical fiber or a copper cable. The CPU network interface on the mainboard sends network test data to the test board card, the optical module receives the network test data sent from the CPU network interface and sends the network test data to the CPU network interface through an optical fiber or a copper cable and a first golden finger, the CPU network interface receives the transmitted network test data, network performance indexes such as bit error rate, time delay and/or packet loss rate are determined according to the network test data sent by the CPU network interface and the network test data received by the CPU network interface, and then the performance of the CPU network interface is determined according to the network performance indexes; the external input port of one optical module a in the first group of optical modules may be connected to the external output interface of another optical module B through an optical fiber or a copper cable, the CPU network interface on the motherboard transmits network test data to the test board card, the optical module a receives the network test data transmitted from the CPU network interface, the optical module B receives the test data transmitted from the optical module a through the optical fiber or the copper cable, and then transmits the test data to the CPU network interface, the CPU network interface receives the network test data transmitted from the optical module B, and network performance indexes such as an error rate, a time delay, and/or a packet loss rate are determined according to the network test data transmitted by the CPU network interface and the network test data received by the CPU network interface.

The loop back test may also be: (1) performing a near-end loop test of a CPU network interface, correspondingly connecting a first row of terminals connected with the CPU network interface on a test board, sending network test data by the CPU network interface, receiving the network test data by the CPU after passing through a first golden finger and the first row of terminals, and determining network performance indexes such as an error rate, a time delay and/or a packet loss rate according to the network test data sent by the CPU network interface and the received network test data; (2) the method comprises the steps of carrying out near-end loop tests on two CPU network interfaces, correspondingly connecting a first row of terminals connected with the CPU network interfaces on a test board, sending network test data by a CPU network interface a, receiving the network test data by a CPU network interface b after the network test data passes through a first golden finger and the first row of terminals, and determining network performance indexes such as bit error rate, time delay and/or packet loss rate according to the network test data sent by the CPU network interface a and the network test data received by the CPU network interface b.

When a signal quality test is carried out, an optical module test fixture is installed in one optical module in a first group of optical modules, the optical module test fixture is connected with an oscilloscope, a CPU network interface on a mainboard sends network test data to a test board card, the optical modules receive the network test data sent from the CPU network interface, the network test data are input into the oscilloscope through the optical module test fixture, and the high-speed oscilloscope carries out eye pattern test analysis to determine the signal quality. In one example, the optical module test fixture is an SFP + test fixture.

The signal quality test can also be realized by connecting the first row of terminals connected with the CPU network interface with an oscilloscope, and performing eye pattern test analysis on the high-speed oscilloscope to determine the signal quality.

And step 102, determining the performance of the CPU network interface according to the test result.

The performance of the CPU network interface can be comprehensively verified or evaluated according to the results of the service pressure test, the loop back test and the signal quality test.

The present application further provides a testing method, which is substantially the same as the above embodiments, and includes: the first row of terminals on the test board card is connected with the second row of terminals, and the third row of terminals is connected with the fourth row of terminals, so that the secondary drive unit is connected between the first group of network pins and the first group of optical modules, and the service pressure test, the loop test and the signal quality test with the secondary drive unit are performed according to the method of the embodiment.

Under the condition that the performance of the CPU network interface is insufficient, a secondary drive chip can be added to perform relevant tests, and according to test data and the performance of the secondary drive chip in the tests, the performance of the CPU network interface is correspondingly improved or reference is provided for mainboard design and convenience is provided for early evaluation of a whole server product.

In order to monitor the optical module during the performance test of the CPU network interface, the method of this embodiment further includes: monitoring status information of the first group of optical modules or the second group of optical modules.

The in-place signal end, the transmission enable control signal end, the transmission failure indication signal end and/or the reception loss indication signal end of the first group of optical modules or the second network interface can be monitored, and the internal state of the first group of optical modules or the second network interface can also be monitored; the monitoring can be performed through the first conversion chip or the second conversion chip.

The CPU network interface can be configured into other network protocols (protocols other than the optical module corresponding protocol), loop test and signal quality test can be carried out: (1) performing a near-end loop test of a CPU network interface, correspondingly connecting a first row of terminals connected with the CPU network interface on a test board, sending network test data by the CPU network interface, receiving the network test data by the CPU after passing through a first golden finger and the first row of terminals, and determining network performance indexes such as an error rate, a time delay and/or a packet loss rate according to the network test data sent by the CPU network interface and the received network test data; (2) performing near-end loop tests of two CPU network interfaces, correspondingly connecting a first row of terminals connected with the CPU network interfaces on a test board, sending network test data by a CPU network interface a, receiving the network test data by a CPU network interface b after the network test data passes through a first golden finger and the first row of terminals, and determining network performance indexes such as bit error rate, time delay and/or packet loss rate and the like according to the network test data sent by the CPU network interface a and the network test data received by the CPU network interface b; (3) and connecting the first row of terminals connected with the CPU network interface with an oscilloscope, and carrying out eye pattern test analysis by the high-speed oscilloscope so as to determine the signal quality.

And verifying and evaluating the performance of the CPU network interface according to the test results.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A CPU network interface performance test board card is characterized by comprising: the system comprises a printed circuit board, a first connecting finger, a secondary driving unit and a first group of optical modules, wherein the printed circuit board is provided with the first connecting finger, the secondary driving unit and the first group of optical modules; the first golden finger is provided with a first group of network pins, the first group of network pins are connected with a first row of terminals, the secondary driving unit is respectively connected with a second row of terminals and a third row of terminals, and the first group of optical modules is connected with a fourth row of terminals; the first row of terminals and the second row of terminals are arranged adjacently, and the third row of terminals and the fourth row of terminals are arranged adjacently.

2. The test board of claim 1, wherein the first set of network pins includes N sets of sub-network pins, two input pins of each set of sub-network pins are respectively connected to the first terminal and the second terminal of the first row of terminals, and two output pins of each set of sub-network pins are respectively connected to the third terminal and the fourth terminal of the first row of terminals; wherein N is an integer of 1 or more.

3. The test board card of claim 1, wherein the secondary driving unit comprises a first secondary driving unit and a second secondary driving unit, the first secondary driving unit and the second secondary driving unit are arranged on the printed circuit board side by side, and input pins of the first secondary driving unit and output pins of the second secondary driving unit are connected with the second row of terminals; and the output pin of the first secondary driving unit is connected with the input pin of the second secondary driving unit and the third row of terminals.

4. The test board card of claim 1, wherein the secondary driving unit further comprises a third secondary driving unit and a fourth secondary driving unit, the third secondary driving unit and the fourth secondary driving unit are arranged on the printed circuit board side by side with the first secondary driving unit, and input pins of the third secondary driving unit and output pins of the fourth secondary driving unit are connected with the second row of terminals; and the output pin of the third secondary driving unit and the input pin of the fourth secondary driving unit are connected with the third row of terminals.

5. The test board of claim 1, wherein the first set of optical modules includes K optical modules, the K optical modules are arranged side by side on the printed circuit board, two input ends of each optical module are respectively connected to the first terminal and the second terminal in the fourth row of terminals, and two output ends of each optical module are respectively connected to the third terminal and the fourth terminal in the fourth row of terminals; wherein K is an integer of 1 or more.

6. The test board card of claim 1, wherein the printed circuit board is further provided with a first system management bus, the first system management bus is connected with a first conversion chip, and the first conversion chip is correspondingly connected with each optical module in the first group of optical modules after dividing the first system management bus into N paths.

7. The test board of claim 6, wherein the first system management bus further has a first I/O interface conversion chip and a second I/O interface conversion chip connected thereto;

the I/O interface of the first conversion I/O interface chip is connected with an in-place signal end, a transmission enabling control signal end, a transmission failure indication signal end and/or a reception loss indication signal end of the first group of optical modules;

and the I/O interface of the second conversion I/O interface chip is connected with the LED indicator lamp.

8. The test board of claim 6, wherein the secondary drive unit is further connected to the first system management bus.

9. The test board of claim 6, wherein an end of the first system management bus proximate to the first gold finger is connected to a first jumper cap option connector;

a second jump cap selectable connector and a third jump cap selectable connector are arranged on the printed circuit board and adjacent to the first jump cap selectable connector; the second jump cap selectable connector is connected with a first pin of the first golden finger, the third jump cap selectable connector is connected with a second pin of the first golden finger, the first pin of the first golden finger is used for being connected to a substrate management controller on a mainboard, and the second pin of the first golden finger is used for being connected to a CPU on the mainboard.

10. The test board card of claim 1, wherein a second gold finger and a second group of optical modules are disposed on the printed circuit board; and a second group of network pins are arranged on the second golden finger and connected with the second group of optical modules.

11. The test board of claim 10, wherein the second group of network pins comprises Q groups of sub-network pins, and the second group of optical modules comprises Q optical modules, and each group of sub-network pins is correspondingly connected to each optical module, wherein two input pins of each group of sub-network pins are respectively correspondingly connected to two outputs of the corresponding optical module, and two output pins of each group of sub-network pins are respectively correspondingly connected to two inputs of the corresponding optical module; wherein Q is an integer of 1 or more.

12. The test board card of claim 10, wherein the printed circuit board is further provided with a second system management bus, the second system management bus is connected to a second conversion chip, and the second conversion chip is correspondingly connected to each optical module in the second group of optical modules after dividing the second system management bus into N paths.

13. The test board of claim 12, wherein a third-to-I/O interface chip and a fourth-to-I/O interface chip are further connected to the second system management bus;

the I/O interface of the third conversion I/O interface chip is connected with the in-place signal end, the transmission enabling control signal end, the transmission failure indication signal end and/or the reception loss indication signal end of the second group of optical modules;

and the I/O interface of the fourth conversion I/O interface chip is connected with the LED indicator lamp.

14. The test board of claim 12, wherein an end of the second system management bus proximate to the second gold finger is connected to a fourth hop-cap option connector;

a fifth jump cap selectable connector and a sixth jump cap selectable connector are arranged on the printed circuit board and adjacent to the fourth jump cap selectable connector; the fifth jump cap selectable connector is connected with the first pin of the second golden finger, the sixth jump cap selectable connector is connected with the second pin of the second golden finger, the first pin of the second golden finger is used for being connected to a substrate management controller on a mainboard, and the second pin of the second golden finger is used for being connected to a CPU on the mainboard.

15. The test board of claim 10, wherein the first and second groups of optical modules are each a plurality of SFP + optical modules arranged side-by-side.

16. A CPU network interface performance testing system, comprising: the device comprises a mainboard and a CPU network interface performance test board card, wherein the mainboard is provided with a CPU chip and a PCIE slot connected with the CPU chip, and the CPU network interface performance test board card is inserted into the PCIE slot, wherein the CPU network interface performance test board card is the CPU network interface performance test board card in any one of the claims 1-15.

17. A CPU network interface performance test method is characterized by comprising the following steps:

a CPU network port on a mainboard sends network test data to a first group of optical modules on a test board card inserted in a PCIE slot on the mainboard to perform service pressure test, loop test and/or signal quality test; the test board is the CPU network interface performance test board of any one of the claims 1-15; the first row of terminals and the fourth row of terminals on the test board are connected, so that the first group of network pins are connected with the first group of optical modules;

and determining the performance of the CPU network interface according to the test result.

18. The test method of claim 17, further comprising:

and the first row of terminals and the second row of terminals on the test board card are connected, and the third row of terminals and the fourth row of terminals are connected, so that the secondary drive unit is connected between the first group of network pins and the first group of optical modules, and a service pressure test, a loop test and/or a signal quality test with the secondary drive unit are/is carried out.

19. The test method of claim 17, further comprising: monitoring status information of the first group of optical modules or the second group of optical modules.