CN111969061B - LDMOS structure and manufacturing method thereof - Google Patents
LDMOS structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 210000000746 body region Anatomy 0.000 claims abstract description 32
- 230000001965 increasing effect Effects 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 111
- 230000008859 change Effects 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 150000002500 ions Chemical class 0.000 description 15
- 229910044991 metal oxide Inorganic materials 0.000 description 12
- 150000004706 metal oxides Chemical class 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000010267 cellular communication Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS structure and a manufacturing method thereof, aiming at solving the contradiction problem between the breakdown voltage and the on-resistance of an LDMOS device in the prior art, and the technical key point is that the LDMOS structure comprises a semiconductor substrate; a well region in the semiconductor substrate; a body region located at one side of the well region of the semiconductor substrate; the grid structure comprises a grid dielectric layer and a polysilicon gate which are formed in a superposition mode; the source electrode structure is positioned on the surface of the body region and aligned with the first side surface of the polysilicon gate; the drain electrode structure is positioned on the surface of the well region and is close to the second side surface of the polysilicon gate; the drift region is positioned at the junction area of the gate structure and the drain structure, and the doping concentration of the drift region is gradually increased along the transverse direction from the gate structure. According to the scheme, the doping concentration of the drift region is changed gradually in the transverse direction, so that the breakdown voltage of the LDMOS device is increased, the on-resistance is not increased too much, and the performance and the reliability of the LDMOS device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS structure and a manufacturing method thereof.
Background
LDMOS (LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR; laterally diffused metal oxide semiconductor) is developed for 900MHz cellular telephone technology, and the growing market of cellular communication ensures the application of LDMOS transistors, and the technology of LDMOS is mature, and the cost is reduced, so that the LDMOS transistor will replace the bipolar transistor technology in most cases in the future. Compared with a bipolar transistor, the gain of the LDMOS tube is higher, the gain of the LDMOS tube can reach more than 14dB, the gain of the bipolar transistor is 5-6 dB, and the gain of a PA module adopting the LDMOS tube can reach about 60 dB. This shows that for the same output power, a cell phone employing an LDMOS tube requires fewer devices, thereby increasing the reliability of the power amplifier.
The doping profile of the drift region directly affects the breakdown voltage and on-resistance of the LDMOS device. A large number of researchers have studied the doping profile of this region, such as a stacked LDD structure, a double-layer RESURF structure, etc., and have a certain positive effect on optimization of breakdown voltage and on-resistance, but the effect is limited. With the progress of technology, further requirements on the performance of the LDMOS device are further demanded, and an LDMOS device with large breakdown voltage and small on-resistance is urgently needed.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defect that the breakdown voltage and the on-resistance of the LDMOS device in the prior art cannot reach the expectations, so as to provide an LDMOS structure and a manufacturing method thereof.
The first aspect of the present invention provides an LDMOS structure, including:
A semiconductor substrate;
A well region located in the semiconductor substrate;
the body region is positioned at one side of the well region of the semiconductor substrate, the junction depth of the body region is smaller than that of the well region, and the body region and the well region are overlapped transversely;
the gate structure comprises a polysilicon gate and a gate dielectric layer which are formed in a superposition way, wherein the gate dielectric layer covers the surface of the body region, and the second side surface of the gate dielectric layer extends to the surface of the well region; the surface of the body region covered by the gate dielectric layer is used for forming a channel;
The source electrode structure is positioned on the surface of the body region and aligned with the first side surface of the gate dielectric layer;
the drain electrode structure is positioned on the surface of the well region and is close to the second side surface of the gate dielectric layer;
And the drift region is positioned at the junction area of the gate structure and the drain structure, and the doping concentration of the drift region is gradually increased along the transverse direction from the gate structure.
Optionally, the rate of change of the doping concentration of the drift region as it increases gradually in the lateral direction from the gate structure varies with the increase of the doping concentration.
The second scheme of the invention provides a manufacturing method based on the LDMOS structure, which comprises the following steps:
Forming a well region in the semiconductor substrate, and forming a body region in the semiconductor substrate at one side of the well region;
forming a grid structure crossing over part of the body region and the well region, forming a source electrode structure on the body region at one side of the grid structure, and forming a drain electrode structure on the well region at the other side of the grid structure;
Forming a drift region in the well region in the junction region of the gate structure and the drain structure, and forming barrier layers on the well region at two sides of the drift region;
doping the drift region;
Forming a dielectric layer covering the drift region in the junction region of the gate structure and the drain structure;
performing inclined ion implantation on the dielectric layer to dope the surface layer of the dielectric layer, wherein the doping depth is deeper along with the farther away from the body region, and forming a doped dielectric layer;
Etching or corroding the doped dielectric layer to form a residual dielectric layer with gradually changing height;
And carrying out high-temperature annealing on the drift region to form a drift region with doping concentration gradually increasing along the transverse direction from the grid structure, and removing the residual dielectric layer and the barrier layer.
Optionally, when the oblique ions are implanted, the oblique ions are obliquely downwards incident along the direction from the gate structure to the drain structure, and the incidence direction of the oblique ions forms an included angle with the horizontal direction.
Optionally, the included angle is 15-60 °.
Optionally, the ion source of the tilted ion is BF 2, the energy of the BF 2 implantation is 3-30KeV, and the dose is 1e 13-1e14/cm2; or (b)
The ion source of the inclined ion is boron, the energy of the boron implantation is 3-6KeV, and the dosage is 1e 13-1e14/cm2.
Optionally, the dielectric layer is an initial dielectric layer after forming and before performing oblique ion implantation, and the initial dielectric layer is doped.
Optionally, when forming a dielectric layer covering the drift region in the junction region of the gate structure and the drain structure, the forming temperature of the dielectric layer is 50-150 degrees.
Optionally, the rate of change of the doping concentration of the drift region as it increases gradually in the lateral direction from the gate structure varies with the increase of the doping concentration.
Optionally, the rate of change of the remaining dielectric layer when the height is gradually changed varies with the change of the height.
The technical scheme of the invention has the following advantages:
1. according to the LDMOS structure provided by the invention, the doping concentration of the drift region is controlled to continuously change along the transverse direction, and the doping concentration is gradually increased from the grid electrode structure, so that the breakdown voltage of the LDMOS device is increased, the on-resistance is not increased too much, and the performance and the reliability of the LDMOS device are improved.
2. According to the manufacturing method of the LDMOS structure, the drift region is doped, the dielectric layer covered on the drift region is formed in a low-temperature state, and inclined ion implantation is carried out on the dielectric layer, so that the surface layer of the dielectric layer is doped, the doping depth is deeper along with the fact that the doping depth is farther from the grid structure, and finally the doped dielectric layer is formed; etching or etching the doped dielectric layer to remove the doped dielectric layer, wherein in the etching or etching process, the etching or etching rate of the undoped dielectric layer is zero, and the etching or etching rate of the lightly doped dielectric layer is slower, so that a residual dielectric layer with gradually changing height is finally formed; and the drift region is subjected to high-temperature annealing, the doped impurities can be activated by the high-temperature annealing, the impurities in the drift region can diffuse into the dielectric layer due to the diffusion of the impurities, the total amount of the impurities diffused at different positions in the drift region is different due to the difference of the thickness in the residual dielectric layer, and finally the drift region gradually increasing along the transverse direction is formed, so that the breakdown voltage of the LDMOS device with the drift region gradually increasing along the transverse direction is increased, the on-resistance is not increased too much, and the performance and the reliability of the LDMOS device are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram showing an ideal doping mode of a drift region in an LDMOS structure according to the present invention;
fig. 2 is a schematic structural diagram of an LDMOS structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an LDMOS structure according to another embodiment of the present invention;
FIG. 4 is a flow chart of a method of fabricating an LDMOS structure of the present invention;
FIG. 5 is a schematic diagram of the structure of step S4 in FIG. 4;
FIG. 6 is a schematic diagram of the structure of step S5 in FIG. 4;
FIG. 7 is a schematic diagram of the structure of step S6 in FIG. 4;
fig. 8 is a schematic structural diagram of step S7 in fig. 4.
Reference numerals illustrate:
1. a semiconductor substrate; 2. a well region; 3. a body region; 4. a gate structure; 41. a polysilicon gate; 42. a gate dielectric layer; 5. a source electrode structure; 6. a drain structure; 7. a drift region; 8. a dielectric layer; 81. doping the dielectric layer; 82. a residual dielectric layer; 9. a barrier layer; 10. a channel.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Lateral diffusion metal oxide semiconductor (abbreviated as LDMOS) is a semiconductor device with better performance than bipolar transistor, so the application prospect of the lateral diffusion metal oxide semiconductor is relatively better, but the doping distribution of the drift region in the lateral diffusion metal oxide semiconductor directly affects the breakdown voltage and on-resistance of the lateral diffusion metal oxide semiconductor device, so the application of the lateral diffusion metal oxide semiconductor is limited. Researchers have studied the doping profile of the drift region and made related improvements such as stacked LDD structures, double layer RESURF structures, etc., but these changes have limited effect on optimization of breakdown voltage and on-resistance.
The applicant has found through research that, as shown in fig. 1, one of ideal doping modes of a drift region in a laterally diffused metal oxide semiconductor is shown, when the doping distribution of the drift region is gradually increased in doping concentration as seen from a lateral structure from a gate structure to a drain structure (i.e., the drift region), the breakdown voltage and the on-resistance of the laterally diffused metal oxide semiconductor are large.
Example 1:
An LDMOS structure, as shown in fig. 2, comprises a semiconductor substrate 1, preferably the semiconductor substrate 1 is P-doped and the semiconductor substrate 1 is a silicon substrate. The well region 2 is a P-type well region formed by diffusion on the semiconductor substrate 1. The junction depth of the P-type doped body region 3 is smaller than that of the well region 2, and the body region 3 and the well region 2 transversely overlap. The gate structure 4 is formed by overlapping the polysilicon gate 41 and the gate dielectric layer 42, wherein the gate dielectric layer 42 covers the surface of the body region 3 and the second side surface of the gate dielectric layer 42 extends to the surface of the well region 2; the surface of the body region 3 covered by the gate dielectric layer 42 is used to form a channel, which is P-doped, and when turned on, the channel may extend to the second side of the gate dielectric layer 42, and the well region 2 covered by the gate dielectric layer 42 is an accumulation layer region. Preferably, the gate dielectric layer 42 is a gate oxide layer. A source structure 5 comprised of heavy N + regions is formed on the surface of body region 3 and self-aligned to a first side of gate dielectric layer 42. A drain structure 6 comprised of heavy N + regions is formed on the surface of well region 2 and adjacent to the second side of gate dielectric layer 42. The drift region 7 in the region where the gate structure 4 and the drain structure 6 meet has a doping concentration gradually increasing in the lateral direction from the gate structure 4.
The drift region 7 is arranged in the well region 2 of the junction region of the gate structure 4 and the drain structure 6, the depth of the drift region 7 is smaller than that of the well region 2, edges at two ends of the drift region 7 are respectively overlapped with edges corresponding to the gate structure 4 and the drain structure 6, the existence of the drift region 7 improves the accumulation distribution of impurity ions in the well region 2 and the drain structure 6 in the region, the uniformity of impurity ion distribution is improved, the resistance of the surface region of the well region 2 is reduced, the influence of a local high-resistance region on the threshold voltage is prevented, and when the LDMOS transistor works, the on resistance on a conduction path between a drain region and a source region is reduced, so that the working current of the LDMOS transistor is increased when the same working voltage as the prior art is applied to the drain region.
As an alternative implementation manner of the embodiment of the present invention, as shown in fig. 3, when the well region 2 in the LDMOS structure is doped with N-type, the channel 10 formed on the surface of the gate dielectric layer 42 covering the body region 3 extends to the second side surface of the gate dielectric layer 42, so as to avoid that the gate dielectric layer 42 overlaps with the well region 2 to generate a larger parasitic gate-drain capacitance. Note that, when the well region 2 is doped P-type, the gate dielectric layer 42 may not overlap with the well region 2, which is not limited in the present invention.
Specifically, the value of the change rate of the doping concentration in the drift region 7 when gradually increasing from the gate structure 4 in the lateral direction may be constant or may be non-constant, and the change rate shown in fig. 1 is constant. The laterally diffused metal oxide semiconductor formed has the advantages of the present invention as long as the doping concentration in the drift region 7 is continuously varied. When the value of the change rate is non-constant, the value of the change rate may be arbitrarily changed with an increase in the doping concentration, for example, the value of the change rate may be increased, decreased in time, increased in time, or the like.
Example 2:
a manufacturing method of the LDMOS structure is shown in FIG. 4, and comprises the following steps:
S1, preparing a semiconductor substrate 1, forming a well region 2 in the semiconductor substrate 1, and forming a body region 3 in the semiconductor substrate 1 at one side of the well region 2;
S2, forming a gate structure 4 which spans over part of the body region 3 and the well region 2, forming a source electrode structure 5 on the body region 3 at one side of the gate structure 4, and forming a drain electrode structure 6 on the well region 2 at the other side of the gate structure 4;
S3, forming a drift region 7 in the well region 2 in the junction region of the gate structure 4 and the drain structure 6, and forming a barrier layer 9 on the well region 2 at two sides of the drift region 7;
In the above step S3, the barrier layer 9 may be a specially designed mask structure, and the mask structure may be one or more of silicon nitride (SiN), silicon oxynitride (SiON), photoresist, and the like. Meanwhile, the blocking layer 9 may be fabricated before the drift region 7, where the fabrication sequence of the blocking layer 9 and the drift region 7 is not limited, and the blocking layer 9 is not necessarily formed after the well region 2, the body region 3, the gate structure 4, the source structure 5, the drain structure 6, and other structures, that is, the order of the forming steps of the blocking layer in the process flow of fabricating the ldmos is not particularly limited, and may be adjusted by those skilled in the art according to public-use requirements. The barrier layer 9 can avoid the influence of subsequent steps on regions outside the drift region 7.
S4, doping the drift region 7;
In the above step S4, as shown in fig. 5, fig. 5 shows a doping process perpendicular or nearly perpendicular to the drift region 7, and the doping method used in this process may be conventional doping methods such as ion implantation or diffusion.
S5, forming a dielectric layer 8 covering the drift region 7 in the junction area of the gate structure 4 and the drain structure 6;
In the above step S5, as shown in fig. 6, fig. 6 shows that the dielectric layer 8 is covered on the drift region 7. The dielectric layer 8 is formed at a low temperature, and the forming temperature of the dielectric layer 8 can be 50-150 ℃, so that the drift region 7 is not affected during low-temperature forming. The formed dielectric layer is called an initial dielectric layer, the initial dielectric layer is undoped or doped, and the doped initial dielectric layer is lightly doped. In this step and the subsequent steps, the barrier layer 9 may be used continuously with the barrier layer formed in step S4, or the barrier layer may be newly manufactured.
S6, performing inclined ion implantation on the dielectric layer 8 so as to dope the surface layer of the dielectric layer 8, wherein the doping depth is deeper along with the farther away from the body region 3, and forming a doped dielectric layer 81;
in the above step S6, as shown in fig. 7, fig. 7 shows a process of doping the dielectric layer 8 with oblique ions to form a doped dielectric layer 81. In the case of oblique ion implantation, oblique ions are incident obliquely downward in the direction from the gate structure 4 to the drain structure 6, and the semiconductor substrate 1 does not rotate during ion implantation. In this step, the specific tilt angle, the ion implantation energy and dose, etc., can be determined by one skilled in the art according to the specific process. For example, the included angle between the incidence direction of the inclined ions and the horizontal direction is 15-60 degrees, the injected ion source is boron difluoride (BF 2), the energy of boron difluoride injection is 3-30KeV, and the dosage is 1e 13-1e14/cm2; or the ion source of the inclined ion is boron, the energy of the boron implantation is 3-6KeV, and the dosage is 1e 13-1e14/cm2.
S7, etching or corroding the doped dielectric layer 81 to form a residual dielectric layer 82 with gradually changing height;
In the above steps, as shown in fig. 8, fig. 8 shows that the remaining dielectric layer 82 is formed after etching or etching and removing the doped dielectric layer 81. In this step, the initial dielectric layer (undoped or lightly doped dielectric layer) is etched or etched at zero or slower speed by wet or dry method, and the doped dielectric layer is etched or etched at fast speed, so that the remaining dielectric layer 82 with gradually changing height is finally formed, and the height of the remaining dielectric layer 82 gradually decreases from the gate structure 4 to the drain structure 6. The rate of change in the gradual change in the height of the remaining dielectric layer 82 need not be constant, but may be non-constant, as long as the height is continuously changing. When the value of the change rate is non-constant, the value of the change rate may arbitrarily change with a decrease in height, for example, the value of the change rate may be increased, decreased, or a change such as a time increase or a time decrease.
And S8, performing high-temperature annealing on the drift region 7 to form the drift region 7 with the doping concentration gradually increasing from the gate structure 4 along the transverse direction, and removing the residual dielectric layer 82 and the barrier layer 9.
In the above step S8, the doped impurities are activated by high temperature annealing the drift region 7. The high temperature annealing may cause impurity diffusion, and during annealing, impurities in the drift region 7 may diffuse into the remaining dielectric layer 82, and due to the different thickness of the remaining dielectric layer 82, the total amount of impurities diffused at different positions in the drift region 7 may be different, thereby forming the drift region 7 with gradually changing doping concentration. The rate of change of the doping concentration of the drift region 7 gradually increasing in the lateral direction is not necessarily constant, but may be non-constant, and the object of the present invention can be achieved as long as the doping concentration of the drift region 7 continuously changes. When the value of the rate of change is non-constant, the value of the rate of change may be arbitrarily changed with an increase in the doping concentration, for example, the value of the rate of change may be increased, decreased, or decreased in time.
In the steps S1 to S8 indicated in the above embodiment, the manufacturing method is not limited to the above-described steps, and the order of the steps may be changed appropriately.
The drift region 7 with the doping concentration gradually changing along the transverse direction from the gate structure 4 is formed through a series of steps, and the doping concentration is gradually increased from the gate structure 4, so that the transverse diffusion metal oxide semiconductor device with large breakdown voltage and without too much increase of on-resistance is finally obtained, and the performance and the reliability of the transverse diffusion metal oxide semiconductor device are improved. At the same time, the object of the invention is achieved to some extent or under certain conditions when the doping concentration of the drift region 7 is gradually reduced in the lateral direction from the gate structure 4.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (8)
1. The manufacturing method of the LDMOS structure is characterized in that the LDMOS structure comprises the following steps: a semiconductor substrate (1); a well region (2) located in the semiconductor substrate (1); the body region (3) is positioned at one side of the well region (2) of the semiconductor substrate (1), the junction depth of the body region (3) is smaller than that of the well region (2), and the body region (3) and the well region (2) are transversely overlapped; the grid structure (4) comprises a polysilicon grid (41) and a grid dielectric layer (42) which are formed in a superposition mode, the grid dielectric layer (42) covers the surface of the body region (3), and the second side face of the grid dielectric layer (42) extends to the surface of the well region (2); a source structure (5) located on the surface of the body region (3) and aligned with the first side of the gate dielectric layer (42); the drain electrode structure (6) is positioned on the surface of the well region (2) and is close to the second side surface of the gate dielectric layer (42); -a drift region (7) between the gate structure (4), the drain structure (6) and having a doping concentration gradually increasing in a lateral direction from the gate structure (4);
The manufacturing method of the LDMOS structure comprises the following steps:
forming a well region (2) in a semiconductor substrate (1), and forming a body region (3) in the semiconductor substrate (1) at one side of the well region (2);
Forming a gate structure (4) which spans over part of the body region (3) and the well region (2), forming a source electrode structure (5) on the body region (3) at one side of the gate structure (4), and forming a drain electrode structure (6) on the well region (2) at the other side of the gate structure (4);
Forming a drift region (7) positioned in the well region (2) between the gate structure (4) and the drain structure (6), and forming barrier layers (9) positioned on the well region (2) at two sides of the drift region (7);
-doping the drift region (7);
Forming a dielectric layer (8) covering the drift region (7) in the junction region of the gate structure (4) and the drain structure (6);
Performing oblique ion implantation on the dielectric layer (8) to dope the surface layer of the dielectric layer (8), wherein the doping depth is deeper along with the further the isolated region (3), and a doped dielectric layer (81) is formed, when the oblique ion implantation is performed, the oblique ion is obliquely downwards incident along the direction from the gate structure (4) to the drain structure (6), and the incidence direction of the oblique ion has an included angle with the horizontal direction;
Etching or etching the doped dielectric layer (81) to form a remaining dielectric layer (82) of progressively varying height;
and carrying out high-temperature annealing on the drift region (7) to form the drift region (7) with the doping concentration gradually increasing from the gate structure (4) along the transverse direction, and removing the residual dielectric layer (82) and the barrier layer (9).
2. The method of fabricating the LDMOS structure of claim 1 wherein said included angle is 15-60 °.
3. The method of fabricating an LDMOS structure according to any one of claims 1-2, wherein the ion source of the tilted ion is boron difluoride, the energy of the boron difluoride implantation is 3-30KeV, and the dose is 1e 13-1e14/cm2; or (b)
The ion source of the inclined ion is boron, the energy of the boron implantation is 3-6KeV, and the dosage is 1e 13-1e14/cm2.
4. The method of manufacturing an LDMOS structure according to claim 1, characterized in that the dielectric layer (8) is an initial dielectric layer after forming and before performing the angled ion implantation, said initial dielectric layer being doped.
5. The method of manufacturing an LDMOS structure according to claim 1, wherein when forming a dielectric layer (8) covering the drift region (7) in the junction region of the gate structure (4) and the drain structure (6), the forming temperature of the dielectric layer (8) is 50-150 degrees.
6. The method of manufacturing an LDMOS structure according to any of claims 1-2 and 4-5, wherein the rate of change of the doping concentration of the drift region (7) when increasing gradually in the lateral direction from the gate structure (4) varies with an increasing doping concentration.
7. The method of fabricating the LDMOS structure as recited in any of claims 1-2 and 4-5, wherein a rate of change of the remaining dielectric layer (82) when the height is gradually changed varies with the change of the height.
8. Method for manufacturing an LDMOS structure according to claim 1, characterized in that the rate of change of the doping concentration of the drift region (7) gradually increases in the lateral direction from the gate structure (4) as the doping concentration increases.
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