CN111965961B - Positioning method and positioning mark for photoetching process - Google Patents

Positioning method and positioning mark for photoetching process Download PDF

Info

Publication number
CN111965961B
CN111965961B CN202010895384.3A CN202010895384A CN111965961B CN 111965961 B CN111965961 B CN 111965961B CN 202010895384 A CN202010895384 A CN 202010895384A CN 111965961 B CN111965961 B CN 111965961B
Authority
CN
China
Prior art keywords
positioning
positioning mark
side edge
mask
intersection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010895384.3A
Other languages
Chinese (zh)
Other versions
CN111965961A (en
Inventor
刘召军
蒋府龙
刘亚莹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southwest University of Science and Technology
Original Assignee
Southwest University of Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southwest University of Science and Technology filed Critical Southwest University of Science and Technology
Priority to CN202010895384.3A priority Critical patent/CN111965961B/en
Publication of CN111965961A publication Critical patent/CN111965961A/en
Application granted granted Critical
Publication of CN111965961B publication Critical patent/CN111965961B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

The embodiment of the invention discloses a positioning method and a positioning mark for a photoetching process, wherein the method comprises the following steps: obtaining a first positioning mark formed by a first photomask manufacturing process, wherein the first positioning mark comprises a first side edge and a second side edge which are parallel to each other; obtaining a second positioning mark formed by a second photomask manufacturing process, wherein the second positioning mark comprises a third side edge and a fourth side edge, the third side edge is parallel to the first side edge, and the intersecting angle of the fourth side edge and the second side edge is less than 45 degrees; and determining the deviation between the third side edge and the first side edge according to the intersection angle and the intersection position of the fourth side edge and the second side edge. According to the invention, the offset of the photoetching pattern in one direction is amplified by comparing the first positioning mark with the second positioning mark and utilizing the intersection relation of the two layers of positioning marks, so that the technical problem that a semiconductor device cannot be accurately positioned due to limitation of the limit of human eyes and the alignment precision of equipment is solved, and the technical effect of intelligently improving the photoetching positioning precision is realized.

Description

Positioning method and positioning mark for photoetching process
Technical Field
The embodiment of the invention relates to a semiconductor technology, in particular to a positioning method and a positioning mark for a photoetching process.
Background
The photolithography process refers to a process of removing a specific portion of a thin film on the surface of a wafer through a series of production steps. The photolithography process first creates a pattern on the wafer surface that is as close as possible to the dimensions required in the design rules, and then correctly positions the pattern on the wafer surface. Because the final pattern is built up by stacking multiple masks in a specific order on the wafer surface, if the positioning is not accurate enough each time, the whole circuit will fail. Therefore, how to better perform positioning and calibration becomes an important research project in the photolithography process.
At present, most of the adopted photoetching process positioning methods are realized by transmitting a mask pattern and a pattern on a wafer into a display system through a microscopic imaging system in photoetching equipment and then manually aligning or automatically aligning the mask pattern and the wafer by equipment.
Disclosure of Invention
The invention provides a positioning method and a positioning mark for a photoetching process, which are used for intelligently improving photoetching positioning precision and improving precision and quality of a semiconductor finished product.
In a first aspect, an embodiment of the present invention provides a positioning method for a photolithography process, including:
acquiring a first positioning mark formed by a first photomask manufacturing process, wherein the first positioning mark comprises a first side edge and a second side edge which are parallel to each other;
obtaining a second positioning mark formed by a second photomask manufacturing process, wherein the second positioning mark comprises a third side and a fourth side, the third side is parallel to the first side, and the intersecting angle of the fourth side and the second side is less than 45 degrees;
and determining the deviation between the third side edge and the first side edge according to the intersection angle and the intersection position of the fourth side edge and the second side edge.
Optionally, the determining the deviation between the third side edge and the first side edge according to the intersection angle and the intersection position of the fourth side edge and the second side edge includes:
determining the intersection angle and the intersection position of the fourth side and the second side based on a preset plane coordinate system, wherein the preset plane coordinate system is a two-dimensional coordinate system which takes the first side as one coordinate axis, takes the direction vertical to the first side as the other coordinate axis and takes the end point of the first side as the origin;
determining the distance between the intersection position of the fourth side edge and the second side edge along the direction parallel to the first side edge according to the intersection angle and the intersection position of the fourth side edge and the second side edge;
determining a deviation between the third side and the first side based on the spacing.
Optionally, the first positioning identifier comprises a cross positioning identification pattern or a symmetrical polygon positioning identification pattern with adjacent sides perpendicular to each other, and the second positioning identifier comprises a symmetrical polygon positioning identification pattern with slopes on the sides.
Optionally, the first positioning mark and the second positioning mark have different graphic shapes, and a length of the second side edge of the first positioning mark in the first side edge direction is less than or equal to a length of the fourth side edge of the second positioning mark in the first side edge direction.
Optionally, the first positioning identifier is located on the bottom metal plate or covers on the bottom mask of the bottom metal plate, and the second positioning identifier is located on the bottom metal plate or covers adjacent to the bottom mask on the top mask of the bottom metal plate.
Optionally, the first positioning mark and the second positioning mark are respectively formed on the adjacent bottom layer mask and the top layer mask by means of photolithography, electron beam or corrosive solvent, and the masks are used for forming corresponding photolithography patterns on the surface of the metal layer covering the substrate.
Optionally, the length of the exposure window of the bottom layer mask is different from that of the exposure window of the top layer mask.
Optionally, first location sign still includes the fifth side, and second location sign still includes the sixth side, the fifth side with the second side is parallel, the sixth side with predetermine the coordinate system the contained angle of a coordinate axis with the fourth side with predetermine the coordinate system the contained angle of coordinate axis is the same, the fifth side with the sixth side is crossing, the length of fifth side is greater than the length of sixth side.
Optionally, the deviation between the third side and the first side is determined by the following formula:
h＝2a*cotθ
wherein h is the pitch, a is the deviation, and θ is the intersection angle.
In a second aspect, an embodiment of the present invention further provides a positioning mark for a photolithography process, including:
the first positioning mark is arranged on the first photomask and comprises a first side edge and a second side edge which are parallel to each other;
set up in the second location sign of second light shield, including third side and fourth side, the third side with first side is parallel, the crossing angle of fourth side and second side is less than 45 degrees.
According to the invention, the offset of the photoetching graph in one direction is amplified by comparing the first positioning mark and the second positioning mark on the adjacent metal layers or the same circuit substrate and utilizing the intersection relation of the two positioning marks, so that the technical problem that a semiconductor device cannot be accurately positioned due to limitation of human eyes and equipment alignment precision is solved, and the technical effects of intelligently improving the photoetching positioning precision and improving the precision and quality of a semiconductor finished product are realized.
Drawings
FIG. 1 is a flowchart of a positioning method for a photolithography process according to an embodiment of the present invention;
fig. 2a is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2b is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 3a is a schematic diagram of a first positioning identifier according to an embodiment of the present invention;
fig. 3b is a schematic structural diagram of another semiconductor device according to the first embodiment of the present invention;
fig. 3c is a schematic diagram of a second positioning identifier according to an embodiment of the present invention;
fig. 4a is a schematic diagram of a first positioning identifier and a second positioning identifier according to an embodiment of the present invention;
fig. 4b is a schematic diagram of another first positioning identifier and a second positioning identifier according to a first embodiment of the present invention;
FIG. 5 is a flowchart of a positioning method for a photolithography process according to a second embodiment of the present invention;
fig. 6a is a schematic diagram of a second positioning identifier according to a second embodiment of the present invention;
fig. 6b is a schematic diagram of a first positioning identifier and a second positioning identifier according to a second embodiment of the present invention;
fig. 7 is a schematic structural diagram of a mask according to a second embodiment of the present invention;
fig. 8a is a schematic diagram of a first positioning identifier according to a second embodiment of the present invention;
fig. 8b is a schematic diagram of another first positioning identifier and a second positioning identifier according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "plurality", "batch" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
The photolithography process refers to a process of removing a specific portion of a thin film on a wafer surface through a series of production steps. The photolithography process first creates a pattern on the wafer surface that is as close as possible to the dimensions required in the design rules, and then correctly positions the pattern on the wafer surface. Because the final pattern is built up by stacking multiple masks in a specific order on the wafer surface, if the positioning is not accurate enough each time, the whole circuit will fail. Therefore, how to better perform positioning and calibration becomes an important research project in the photolithography process.
Example one
Fig. 1 is a flowchart of a positioning method for a photolithography process according to an embodiment of the present invention, where the method is applicable to a photolithography process performed on a semiconductor material, and the method can be executed by a processor. As shown in fig. 1, the positioning method for photolithography process of this embodiment includes:
step S110, a first positioning mark formed by a first photomask process is obtained, where the first positioning mark includes a first side and a second side that are parallel to each other.
The photomask manufacturing process refers to a manufacturing process of drawing an electronic circuit diagram meeting the requirements after testing into a photomask image. Firstly, the pattern on the mask plate needs to be transferred to the photoresist layer, after the mask plate and the photoresist layer are aligned, the photoresist changes the self property and structure after exposure, namely, the original soluble substance is changed into the insoluble substance, or vice versa, then the soluble part is removed by a chemical solvent or a developer, a hole is left under the photoresist layer, and the hole corresponds to the lightproof part of the mask plate. Next, it is necessary to transfer the pattern from the photoresist pattern to a wafer (wafer refers to a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a wafer because it has a circular shape, and various circuit device structures can be manufactured on the silicon wafer to become an IC product having a specific electric function). In the step, through different etching methods, the protective layer or the film layer of the part of the wafer which is not protected by the photoresist is removed, and finally the photoresist layer is removed, so that the pattern on the mask is transferred to the wafer finally.
Specifically, in order to facilitate the positioning of the subsequent photolithography process, a positioning mark is generally designed at the edge of the mask, and after a photomask process is performed on the semiconductor device once, a positioning mark corresponding to the positioning mark of the mask is formed on the surface of the metal layer of the semiconductor device, that is, the first positioning mark in this embodiment may include two parallel sides. Fig. 2a is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, as shown in fig. 2a, 10 is a metal layer, 20 is a circuit substrate, when a photomask process is performed on the semiconductor device, first, a metal layer 10 is placed on the circuit substrate 20, a protective layer may be covered on the metal layer 10, the protective layer is used to protect a portion of the metal layer 10 that needs to be reserved from corrosion, a mask may be covered on the protective layer, the mask may include a lithography pattern (such as a circuit pattern, etc.) meeting requirements through a test, a corresponding exposure window, and a positioning mark for positioning, and generally, the positioning mark is located at an edge of the mask. When light irradiates downwards from the upper part of the mask, the substance structure of the protective layer corresponding to the exposure window of the mask changes, then the whole semiconductor device with the mask removed is put into a corrosion solvent which can corrode the protective layer with the substance structure changing, the surface of the semiconductor device at the position, corresponding to the corroded position, of the protective layer is exposed, the exposed metal layer 10 corresponding to the protective layer with the substance structure changing is removed through other corrosion solvents or corrosion modes, and after the protective layer covering the metal layer 10 is washed away, the photoetching pattern on the mask can be transferred onto the metal layer 10, and finally the metal layer shown in fig. 2 is obtained. In this embodiment, a corrosion solvent may also be selected to directly corrode the portion of the protection layer with the changed material structure and the metal layer 10 corresponding to the portion of the protection layer with the changed material structure (i.e. the corresponding metal layer located below the protection layer with the changed material structure), so as to transfer the lithographic pattern on the mask onto the metal layer 10, and transfer the positioning mark on the mask onto the metal layer 10 in the same manner. In this embodiment, after the semiconductor device completes a photomask manufacturing process, the processor corresponding to the lithography apparatus may acquire the positioning identifier on the metal layer or the mask used for the photomask manufacturing process through a microscopic apparatus, a laser apparatus, or other image acquisition apparatuses, where the positioning identifier includes two parallel side edges. Fig. 2b is a schematic structural diagram of another semiconductor device according to the first embodiment of the present invention. As shown in fig. 2b, the first positioning mark is located at the edge of the metal layer 10, the first positioning mark is in a cross shape, and the first side edge of the first positioning mark is parallel to the second side edge.
Fig. 3a is a schematic diagram of a first positioning identifier according to an embodiment of the present invention. As shown in fig. 3a, the first positioning mark is cross-shaped, the first side edge is 1, the second side edge is 2, and the first side edge and the second side edge are parallel to each other. In this embodiment, the shape of the first positioning mark may be various, as long as it is ensured that the first positioning mark is a symmetrical pattern, and there is a group of sides parallel to each other.
Step S120, a second positioning mark formed by a second photomask manufacturing process is obtained, the second positioning mark comprises a third side and a fourth side, the third side is parallel to the first side, and the intersecting angle of the fourth side and the second side is smaller than 45 degrees.
Specifically, fig. 3b is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention. 10 is a top metal layer, 20 is a bottom metal layer (i.e., a metal layer for performing a first photo-masking process), 30 is a circuit substrate, when a second photo-masking process is performed on the semiconductor device, a top metal layer covers the surface of the metal layer of the semiconductor device having performed the first photo-masking process, which is the same as the first photo-masking process, and a positioning mark (i.e., the second positioning mark of the embodiment) can also be generated at the edge of the top metal layer (i.e., 10 in fig. 3 b) having performed the second photo-masking process according to the positioning mark of the mask used in the second photo-masking process, and the second positioning mark is used for comparing with the first positioning mark to determine whether there is an error in the positioning of the bottom metal layer and the top metal layer. The processor corresponding to the lithography apparatus may acquire the second positioning identifier on the metal layer or on the mask used in the sub-photomask manufacturing process through a microscopic apparatus, a laser apparatus, or other image acquisition apparatuses. Fig. 3c is a schematic diagram of a second positioning identifier according to an embodiment of the present invention. As shown in fig. 3c, the third side is 3, the fourth side is 4, the third side 3 is parallel to the first side of the first positioning mark, the fourth side 4 intersects with the second side of the first positioning mark at an intersection, and the intersection angle between the fourth side and the second side is less than 45 degrees.
Step S130, determining a deviation between the third side and the first side according to an intersection angle and an intersection position of the fourth side and the second side.
Fig. 4a is a schematic diagram of a first positioning identifier and a second positioning identifier according to an embodiment of the present invention. As shown in fig. 4a, when the first positioning mark and the second positioning mark are completely aligned, the third side of the second positioning mark coincides with the first side of the first positioning mark, and the fourth side of the second positioning mark intersects with the third side of the first positioning mark at a fixed point. Fig. 4b is a schematic view of another first positioning identifier and a second positioning identifier according to an embodiment of the present invention, as shown in fig. 4b, when the first positioning identifier and the second positioning identifier have a positioning error, a processor of the lithographic apparatus may determine an intersection angle and an intersection position of a fourth side and a second side in a preset coordinate system, where the preset coordinate system may be a two-dimensional planar coordinate system that uses an end point of the first side as an origin, a direction parallel to the first side as a coordinate system, and a direction perpendicular to the first side as another coordinate system, and the preset coordinate system may be obtained by obtaining a size of the first positioning identifier and performing certain calculation. After the processor of the lithographic apparatus determines the intersection angle and the intersection position of the fourth side and the second side, since the first positioning identifier and the second positioning identifier are both symmetric patterns, an error between the third side and the first side, that is, a distance value between the third side and the first side (i.e., h in fig. 4 b), can be obtained according to a preset deviation algorithm.
The first embodiment of the invention has the advantages that the offset of the photoetching pattern in one direction is amplified by comparing the first positioning mark and the second positioning mark on the adjacent metal layers or the same circuit substrate and utilizing the intersection relation of the two positioning marks, so that the technical problem that a semiconductor device cannot be accurately positioned due to limitation of human eye limit and equipment alignment precision is solved, and the technical effects of intelligently improving photoetching positioning precision and improving precision and quality of a semiconductor finished product are realized.
Example two
The second embodiment of the invention is further improved on the basis of the first embodiment. Fig. 5 is a flowchart of a positioning method for a photolithography process according to a second embodiment of the present invention. As shown in fig. 5, the positioning method for photolithography process of this embodiment includes:
step S210, a first positioning mark formed by a first photomask manufacturing process is obtained, where the first positioning mark includes a first side and a second side that are parallel to each other.
Specifically, the shape of the first positioning mark in the embodiment of the present invention may be various, as long as it is ensured that the first positioning mark is a symmetrical pattern and two side edges are parallel to each other.
Step S220, a second positioning mark formed by a second photomask manufacturing process is obtained, the second positioning mark includes a third side and a fourth side, the third side is parallel to the first side, and an intersecting angle between the fourth side and the second side is smaller than 45 degrees.
Specifically, in this embodiment, the first positioning mark and the second positioning mark may also be located on the circuit substrate. Fig. 6a is a schematic diagram of a second positioning identifier according to a second embodiment of the present invention. As shown in fig. 6a, the third side 3 of the second positioning mark is parallel to the first side of the first positioning mark, the fourth side 4 of the second positioning mark intersects with the second side of the first positioning mark, and the intersection angle between the fourth side and the second side is less than 45 degrees (which can be determined by the geometric characteristics of a right triangle).
Step S230, determining an intersection angle and an intersection position of the fourth side and the second side based on a preset planar coordinate system, where the preset planar coordinate system is a two-dimensional coordinate system using the first side as a coordinate axis, using a direction perpendicular to the first side as another coordinate axis, and using an end point of the first side as an origin.
Step S240, determining a distance between the intersection position of the fourth side and the second side along a direction parallel to the first side according to the intersection angle and the intersection position of the fourth side and the second side.
And S250, determining the deviation between the third side edge and the first side edge according to the distance.
Specifically, the processor of the lithographic apparatus may determine an intersection angle and an intersection position of the fourth side and the second side in a preset coordinate system, where the preset coordinate system may be a two-dimensional planar coordinate system using an end point of the first side as an origin, a direction parallel to the first side as a coordinate system, and a direction perpendicular to the first side as another coordinate system, and the preset coordinate system may be obtained by obtaining a size identified by the first positioning and performing a certain calculation. After the processor of the lithographic apparatus determines the intersection angle and the intersection position of the fourth side and the second side, the processor further needs to determine an interval between intersection points of each group of the fourth side and the second side along the direction of the first side according to a geometric relationship, and then obtains a deviation between the third side and the first side through a preset algorithm. Fig. 6b is a schematic diagram of a first positioning identifier and a second positioning identifier according to a second embodiment of the present invention. As shown in fig. 6b, when the first positioning identifier and the second positioning identifier are not aligned, that is, the first side of the first positioning identifier and the third side of the second positioning identifier are not overlapped, because the first positioning identifier and the second positioning identifier are both symmetric graphs, the processor may determine, according to a geometric relationship, a distance between intersection points of two sets of fourth sides and second sides in a direction parallel to the first side (that is, h in fig. 6) based on a preset coordinate system, and then obtain, through a preset deviation algorithm, an error between the third side and the first side, that is, a distance between the third side and the first side (that is, a in fig. 6 b), and also determine, according to the geometric relationship, a distance between an intersection point of the second side and the fourth side when the first positioning identifier and the second positioning identifier are not aligned, and a preset intersection point, that is the first side and the second positioning identifier when the first positioning identifier and the second positioning identifier are completely aligned, and then obtain, through a preset deviation formula, an error between the third side and the first side.
In this embodiment, the first positioning identifier includes a cross positioning identification pattern or a symmetrical polygon positioning identification pattern with adjacent sides perpendicular to each other, and the second positioning identifier includes a symmetrical polygon positioning identification pattern with slopes on the sides.
Specifically, because the second positioning mark has at least one side edge intersecting with the first positioning mark, the second positioning mark may be a symmetrical polygon with a slope on a side edge in this embodiment, and the second positioning mark further needs to have a side edge parallel to the first side edge of the first positioning mark.
In this embodiment, the first positioning mark and the second positioning mark have different graphic shapes, and the length of the second side edge of the first positioning mark in the first side edge direction is less than or equal to the length of the fourth side edge of the second positioning mark in the first side edge direction.
In this embodiment, the first positioning mark may be further located on a bottom mask covering the bottom metal plate or on the bottom metal plate, and the second positioning mark may be further located on a top mask covering the bottom metal plate or on the bottom metal plate, the top mask being adjacent to the bottom mask.
Specifically, the first positioning mark can be located on a bottom metal plate of the semiconductor device or covered on a bottom mask of the bottom metal plate, the second positioning mark is similar to the first positioning mark, the second positioning mark can be located on the bottom metal plate of the semiconductor device or a top mask of the bottom metal plate, the top mask is adjacent to the bottom mask, the bottom mask can refer to a mask covered on the surface of a metal layer of the semiconductor device when the semiconductor device is subjected to a first photomask manufacturing process, and the top mask can refer to a mask used when the semiconductor device is subjected to a second photomask manufacturing process.
In this embodiment, the first positioning mark and the second positioning mark are respectively formed on the bottom mask and the top mask adjacent to each other in a photolithography, electron beam, or etching solvent manner, and the masks are used to form corresponding photolithography patterns on the surface of the metal layer covering the substrate.
In this embodiment, the lengths of the exposure windows of the bottom mask and the top mask are different.
Specifically, fig. 7 is a schematic structural diagram of a mask provided in the second embodiment of the present invention. As shown in FIG. 7, 10 is a mask, 20 is a metal layer, and s is an exposure window length. In this embodiment, the lengths of the exposure windows of the bottom mask corresponding to the first photomask process and the top mask corresponding to the second photomask process may be different, and the length of the exposure window depends on the pattern to be manufactured in the current photomask process, i.e., which portions of the metal layer are to be retained, and the portions to be retained are not opened at the corresponding positions of the masks.
In this embodiment, first location sign still includes the fifth side, and second location sign still includes the sixth side, the fifth side with the second side is parallel, the sixth side with the contained angle of a coordinate axis of predetermineeing the coordinate system with the fourth side with predetermine the coordinate system the contained angle of coordinate axis is the same, the fifth side with the sixth side is crossing, the length of fifth side is greater than the length of sixth side.
Specifically, fig. 8a is a schematic diagram of a first positioning identifier according to a second embodiment of the present invention, and fig. 8b is a schematic diagram of another first positioning identifier and another second positioning identifier according to the second embodiment of the present invention. As shown in fig. 8a and 8b, the straight line C1 is parallel to the third side 3, an intersection point exists between the sixth side 6 of the second positioning mark and the fifth side of the first positioning mark, and the sixth side 6 and the fourth side 4 are symmetrically distributed along C1 (i.e. an included angle between the sixth side and one coordinate axis of the preset coordinate system is the same as an included angle between the fourth side and one coordinate axis of the preset coordinate system). In this embodiment, the length of the fifth side may be greater than the length of the sixth side, so as to ensure that the fifth side and the sixth side can intersect.
In this embodiment, the deviation between the third side and the first side can be determined by the following formula:
h＝2a*cotθ
wherein h is the pitch, a is the deviation, and θ is the intersection angle.
Specifically, after the processor of the lithographic apparatus determines the distance h between the intersection position of the fourth side and the second side along the direction parallel to the first side according to the intersection angle (i.e., θ in the formula) and the intersection position of the fourth side and the second side, the deviation between the third side and the first side, i.e., a in the formula, can be determined according to the formula, i.e., the deviation of the first positioning mark and the second positioning mark along one of the coordinate axis directions of the preset coordinate system is amplified, so that a manufacturer can more accurately position the semiconductor device, and the manufacturing accuracy of the semiconductor device is improved.
The second embodiment of the invention has the advantages that the offset of the photoetching pattern in one direction is amplified by utilizing the intersection relation and the geometric relation of the two layers of positioning marks through comparing the first positioning mark and the second positioning mark which are different on the adjacent metal layers or on the same circuit substrate, thereby solving the technical problem that the semiconductor device cannot be accurately positioned due to the limitation of human eyes and the alignment precision of equipment, and realizing the technical effects of intelligently improving the photoetching positioning precision and the quality of a semiconductor finished product.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.

Claims (8)

1. A positioning method for a lithographic process, comprising:
acquiring a first positioning mark formed by a first photomask manufacturing process, wherein the first positioning mark comprises a first side edge and a second side edge which are parallel to each other;
obtaining a second positioning mark formed by a second photomask manufacturing process, wherein the second positioning mark comprises a third side and a fourth side, the third side is parallel to the first side, and the intersecting angle of the fourth side and the second side is less than 45 degrees;
determining the deviation between the third side edge and the first side edge according to the intersection angle and the intersection position of the fourth side edge and the second side edge;
the determining the deviation between the third side edge and the first side edge according to the intersection angle and the intersection position of the fourth side edge and the second side edge comprises:
determining the intersection angle and the intersection position of the fourth side and the second side based on a preset plane coordinate system, wherein the preset plane coordinate system is a two-dimensional coordinate system which takes the first side as one coordinate axis, takes the direction vertical to the first side as the other coordinate axis and takes the end point of the first side as the origin;
determining the distance between the intersection position of the fourth side and the second side along the direction parallel to the first side according to the intersection angle and the intersection position of the fourth side and the second side;
determining a deviation between the third side edge and the first side edge based on the spacing.
2. The positioning method for lithography process according to claim 1, wherein said first positioning mark comprises a cross positioning identification pattern or a symmetrical polygon positioning identification pattern with mutually perpendicular adjacent sides, and said second positioning mark comprises a symmetrical polygon positioning identification pattern with slopes on the sides.
3. The positioning method for lithography process according to claim 1, wherein the first positioning mark and the second positioning mark have different patterns, and a length of a second side edge of the first positioning mark in the first side edge direction is less than or equal to a length of a fourth side edge of the second positioning mark in the first side edge direction.
4. The method as claimed in claim 1, wherein the first positioning mark is located on the bottom metal plate or on a bottom mask covering the bottom metal plate, and the second positioning mark is located on the bottom metal plate or on a top mask covering the bottom metal plate and adjacent to the bottom mask.
5. The positioning method for lithography processes as claimed in claim 4, wherein the first positioning mark and the second positioning mark are formed on the bottom layer mask and the top layer mask respectively by photolithography, electron beam or corrosive solvent, and the masks are used to form corresponding lithography patterns on the surface of the metal layer covering the substrate.
6. The positioning method for lithography process according to claim 5, wherein the bottom layer mask and the top layer mask have different exposure window lengths.
7. The positioning method for lithography according to claim 2, wherein the first positioning mark further comprises a fifth side, the second positioning mark further comprises a sixth side, the fifth side is parallel to the second side, an included angle between the sixth side and one coordinate axis of the preset planar coordinate system is the same as an included angle between the fourth side and the coordinate axis of the preset planar coordinate system, the fifth side intersects with the sixth side, and the length of the fifth side is greater than the length of the sixth side.
8. The positioning method for lithography process according to claim 1, wherein the deviation between the third side and the first side is determined by the following formula:
h＝2a*cotθ
wherein h is the pitch, a is the deviation, and θ is the intersection angle.
CN202010895384.3A 2020-08-31 2020-08-31 Positioning method and positioning mark for photoetching process Active CN111965961B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010895384.3A CN111965961B (en) 2020-08-31 2020-08-31 Positioning method and positioning mark for photoetching process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010895384.3A CN111965961B (en) 2020-08-31 2020-08-31 Positioning method and positioning mark for photoetching process

Publications (2)

Publication Number Publication Date
CN111965961A CN111965961A (en) 2020-11-20
CN111965961B true CN111965961B (en) 2023-03-10

Family

ID=73400062

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010895384.3A Active CN111965961B (en) 2020-08-31 2020-08-31 Positioning method and positioning mark for photoetching process

Country Status (1)

Country Link
CN (1) CN111965961B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128070A (en) * 1999-03-26 2000-10-03 Mosel Vitelic Inc. Monitor method and apparatus for overlay alignment of a stepper
CN105467747A (en) * 2016-01-09 2016-04-06 北京工业大学 Alignment mark and mask
CN109830508A (en) * 2019-01-09 2019-05-31 昆山国显光电有限公司 The method of image element array substrates and verifying mask plate
CN110750038A (en) * 2019-11-25 2020-02-04 上海华力微电子有限公司 Mask plate, standard plate and alignment pattern error compensation method
CN111198478A (en) * 2018-11-20 2020-05-26 长鑫存储技术有限公司 Mask assembly and registration measuring method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128070A (en) * 1999-03-26 2000-10-03 Mosel Vitelic Inc. Monitor method and apparatus for overlay alignment of a stepper
CN105467747A (en) * 2016-01-09 2016-04-06 北京工业大学 Alignment mark and mask
CN111198478A (en) * 2018-11-20 2020-05-26 长鑫存储技术有限公司 Mask assembly and registration measuring method
CN109830508A (en) * 2019-01-09 2019-05-31 昆山国显光电有限公司 The method of image element array substrates and verifying mask plate
CN110750038A (en) * 2019-11-25 2020-02-04 上海华力微电子有限公司 Mask plate, standard plate and alignment pattern error compensation method

Also Published As

Publication number Publication date
CN111965961A (en) 2020-11-20

Similar Documents

Publication Publication Date Title
US5017514A (en) Method of manufacturing a semiconductor device using a main vernier pattern formed at a right angle to a subsidiary vernier pattern
EP0061536B1 (en) Method of manufacturing a semiconductor device having improved alignment marks and alignment marks for said method
US7933015B2 (en) Mark for alignment and overlay, mask having the same, and method of using the same
US8497997B2 (en) Semiconductor device and method of manufacturing the same
US20210296392A1 (en) Flat Panel Array with the Alignment Marks in Active Area
CN111524836B (en) Marking for locating patterns in semiconductor manufacturing
US7288848B2 (en) Overlay mark for measuring and correcting alignment errors
CN109884862B (en) Overlay deviation compensation device and method in three-dimensional memory exposure system
KR0168772B1 (en) Photomask and fabricating method using it
US7030506B2 (en) Mask and method for using the mask in lithographic processing
CN112882346A (en) Overlay compensation method and system
JP2009270988A (en) Calculating method for overlap misalignment and manufacturing method for semiconductor device
CN111965961B (en) Positioning method and positioning mark for photoetching process
US20050026385A1 (en) Method for manufacturing a semiconductor device and semiconductor device with overlay mark
KR100831680B1 (en) Mask of focus measuring pattern and method for measuring focus values of exposure process by using the same
US7136520B2 (en) Method of checking alignment accuracy of patterns on stacked semiconductor layers
CN108461479A (en) A kind of preparation method of alignment mark
US20160291457A1 (en) Reticle, system comprising a plurality of reticles and method for the formation thereof
CN116931389B (en) Line width measuring method
JP3196721B2 (en) Semiconductor device manufacturing method and measuring device
KR960011264B1 (en) Contact hole type confirmation method of semiconductor device
CN117111398B (en) Method and system for monitoring deviation of photomask manufacturing process
CN111508825B (en) Device offset monitoring method, semiconductor device and manufacturing method thereof
CN117970739A (en) Photomask of large-size spliced product and on-line measuring and positioning method
KR100298193B1 (en) Reticle for leveling alignement of wafer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant