CN111953304B - Front-end signal synthesis module for accelerator low-level control system - Google Patents
Front-end signal synthesis module for accelerator low-level control system Download PDFInfo
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Abstract
The invention discloses a front end signal synthesis module for an accelerator low level control system, which comprises: the device comprises a reference working signal generating unit, an intermediate frequency signal generating unit, a local oscillator signal generating unit and a clock signal generating unit; the output ends of the reference working signal generating unit and the intermediate frequency signal generating unit are connected with the input end of the local oscillation signal generating unit; the output end of the intermediate frequency signal generating unit is connected with the input end of the clock signal generating unit; the invention adopts a frequency multiplication and frequency division parallel structure, wherein the primary structure is a parallel reference working signal generating unit and an intermediate frequency signal generating unit, and the secondary structure is a parallel local oscillator signal generating unit with the internal function of frequency mixing and a clock signal generating unit with the internal function of 4 frequency multiplication. The structure not only can ensure the coherence among the local oscillation signal, the clock signal and the reference working signal, but also can obtain a larger frequency range while overcoming the problem of cascading noise.
Description
Technical Field
The invention belongs to the field of accelerator low-level control, and particularly relates to a front-end signal synthesis module for an accelerator low-level control system.
Background
An accelerator is a device that obtains a large amount of energy by continuously accelerating charged particles through the action of an electromagnetic field. Generally consists of an ion source or an electron gun, an accelerating focusing system and a control system. The microwave power fed into the electron gun and the accelerating tube has a direct influence on the quality parameters of the particle beam, such as energy divergence, beam cluster length, repeatability, etc., so that it is necessary to ensure the amplitude and phase stability of the microwave power source, i.e., the output power of the high frequency RF signal.
In order to achieve the stability of the acceleration field in the acceleration cavity, a Low Level Radio Frequency (LLRF) control system is often introduced. The LLRF control system ensures the stabilization of the acceleration field in the acceleration cavity through feedback or feedforward control, including the generation of control signals, timing and synchronization, signal acquisition and digital signal processing. The stability of the amplitude and the phase of the high-frequency RF signal is two major functional requirements of a low-level control system, and the control of the amplitude and the phase is realized by IQ modulation and demodulation. Digital Low Level RF (DLLRF) control systems have been increasingly used in recent years due to their great flexibility compared to analog techniques. A DLLRF control system front-end signal synthesis module serves as a front-end terminal system and is integrated to generate a reference working signal REF, a local oscillator signal LO and a clock signal CLK. The reference working signal REF is used as a reference for power control of a microwave high-frequency RF signal, the frequency is consistent with the high-frequency RF, a local oscillator signal LO with the frequency close to that of the reference working signal REF is used for up-conversion and down-conversion of a system, and a clock signal CLK is used for a digital signal processing platform. Since the post-stage structure of the front-end signal synthesis module of the DLLRF control system needs to monitor and control the amplitude and phase stability of the high-frequency RF signal through the interaction of the three signals, it is required that the initial phases between the three signal pulses have certainty, that is, coherence. The coherence of these three signals will directly affect the accuracy of the DLLRF control system.
Currently, the existing front-end modules are generally classified into direct synthesis modules and indirect synthesis modules. The indirect synthesis module carries out indirect synthesis on the frequency, uses a high-performance crystal oscillator as a reference frequency, realizes frequency multiplication or frequency division by using phase locking, generates a required signal, has the advantages of small volume and multi-frequency signal output, but has longer time and slower speed in the phase locking process. Most direct synthesis modules adopt a plurality of cascaded frequency dividers to perform frequency division processing on high-frequency signals, and the required signals are obtained through down-conversion. In addition, noise interference can be caused by cascade connection of multiple stages of frequency dividers, the stability of the amplitude phase of the obtained signal is low, and the stray is large; in order to avoid noise interference, if the number of cascaded frequency dividers is reduced, the frequency range of the obtained signal is also reduced correspondingly.
Disclosure of Invention
In view of the above defects or improvement requirements of the prior art, the present invention provides a front-end signal synthesis module for an accelerator low-level control system, which aims to solve the technical problem that in the prior art, due to the adoption of multi-stage frequency divider cascade, coherence between a local oscillator signal and a clock signal and between a local oscillator signal and a reference working signal cannot be ensured.
In order to achieve the above object, the present invention provides a front end signal synthesis module for an accelerator low level control system, comprising: the device comprises a reference working signal generating unit, an intermediate frequency signal generating unit, a local oscillator signal generating unit and a clock signal generating unit;
the output ends of the reference working signal generating unit and the intermediate frequency signal generating unit are connected with the input end of the local oscillation signal generating unit; the output end of the intermediate frequency signal generating unit is connected with the input end of the clock signal generating unit;
the reference working signal generating unit is used for carrying out N frequency multiplication on the INPUT source signal INPUT to obtain a required reference working signal REF and outputting the required reference working signal REF to the local oscillator signal generating unit;
the intermediate frequency signal generating unit is used for carrying out M frequency division on the INPUT source signal INPUT to obtain an intermediate frequency signal IF and outputting the intermediate frequency signal IF to the local oscillator signal generating unit and the clock signal generating unit;
the local oscillation signal generating unit is used for mixing the intermediate frequency signal IF and the reference working signal REF to obtain a required local oscillation signal LO;
the clock signal generating unit is used for carrying out 4-time multiplication on the intermediate frequency signal IF to obtain a required clock signal CLK.
Further preferably, the reference operating signal generating unit includes: the first frequency multiplier and the first filter are connected in series;
after the source signal INPUT is frequency-multiplied by a first frequency multiplier, a signal REF carrying a harmonic signal is obtainedraw，REFrawAfter filtering by the first filter, a reference working signal REF is obtained.
Further preferably, the intermediate frequency signal generating unit includes: a frequency divider and a second filter connected in series;
after the frequency of the source signal INPUT is divided by the frequency divider, a signal IF carrying a harmonic signal is obtainedraw，IFrawAnd filtering the intermediate frequency signal IF through a second filter to obtain an intermediate frequency signal IF.
Further preferably, the local oscillator signal generating unit includes a mixer and a third filter connected in series;
after the reference working signal REF and the intermediate frequency signal IF are mixed by a mixer, a signal LO carrying an intermodulation component is obtainedrawAnd the local oscillation signal is input to a third filter for filtering to obtain a local oscillation signal LO; the frequency of the local oscillator signal LO is the difference between the reference operating signal REF and the frequency of the intermediate frequency signal IF.
Further preferably, the clock signal generating unit includes a second frequency multiplier and a fourth filter connected in series;
the intermediate frequency signal IF is subjected to 4 frequency doubling by a second frequency multiplier to obtain a signal CLK carrying a harmonic signalraw，CLKrawAnd filtering the clock signal CLK by a fourth filter to obtain the clock signal CLK.
Further preferably, the first filter, the third filter and the fourth filter are all band-pass filters, and the second filter is a low-pass filter.
Further preferably, the mixer is a passive mixer.
Further preferably, the connecting lines in the front-end signal synthesis module are all transmission lines with working frequency in the range of 0-3GHz and shielding efficiency of 80 dB.
Further preferably, the front-end signal synthesis module is disposed in a constant temperature box with an electromagnetic shielding function, and an INPUT end of a source signal INPUT, an output end of a reference working signal REF, an output end of a local oscillator signal LO, and an output end of a clock signal CLK are SMA interfaces.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
1. the invention provides a front-end signal synthesis module for an accelerator low-level control system, which is used for multiplying and dividing the frequency of a same source signal INPUT to obtain three paths of signals of a reference working signal REF, a local oscillator signal LO and a clock signal CLK for outputting, wherein the local oscillator signal LO is obtained by mixing an intermediate frequency signal and the reference working signal REF, so that the coherence between the reference working signal and the local oscillator signal is ensured; the local oscillator signal LO and the clock signal CLK are obtained by mixing and multiplying the intermediate frequency signal IF, respectively, and are both generated by the same signal and have coherence.
2. The front-end signal synthesis module for the accelerator low-level control system provided by the invention abandons the method of obtaining other signals by a reference working signal REF down-conversion mode adopted in the traditional direct frequency synthesis mode, the source signal INPUT of the intermediate frequency point directly enters the reference signal generating unit and the intermediate frequency signal generating unit to carry out frequency multiplication and frequency division respectively to obtain a reference working signal REF and an intermediate frequency signal IF, then the local oscillator signal LO and the clock signal CLK are output in parallel in the local oscillator signal generating unit and the clock signal generating unit, the local oscillator signal generating unit and the clock signal generating unit in the invention are second-stage units, because the frequency conversion times in the unit are smaller, multistage frequency conversion devices are not required to be connected in series, the problem of cascade noise is solved, and the stability of the amplitude phase of the obtained signal is higher and the stray is small; and the serial structure of the traditional multistage frequency divider is optimized into a frequency division multiple parallel structure, a larger frequency range is obtained without depending on the cascade depth, and the larger frequency range can be obtained while the problem of noise is solved.
3. The front-end signal synthesis module for the accelerator low-level control system provided by the invention adopts a direct synthesis method, can realize signal synthesis output by using the frequency mixer, the frequency multiplier and the frequency divider, has high speed, and overcomes the problem that indirect synthesis needs longer phase-locking time.
4. According to the front-end signal synthesis module for the low-level control system of the accelerator, the filter is adopted at the rear end inside each signal generation unit, harmonic waves and intermodulation components generated by a frequency conversion device cannot pass through the filter, and the purity and the stability of signals are guaranteed. And the device connection adopts a connecting wire with high shielding efficiency and the whole device structure is arranged in the constant temperature box with the electromagnetic shielding function, so that the work of the whole structure is ensured not to be interfered by the electromagnetic interference.
Drawings
FIG. 1 is a schematic structural diagram of a front-end signal synthesis module for an accelerator low-level control system according to the present invention;
FIG. 2 is a schematic diagram of a specific structure of a front-end signal synthesis module for an accelerator low-level control system according to the present invention;
fig. 3 is a schematic structural diagram of a front-end signal synthesis module for an accelerator low-level control system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In order to achieve the above object, the present invention provides a front end signal synthesis module for an accelerator low level control system, as shown in fig. 1, comprising: a reference working signal generating unit 1, an intermediate frequency signal generating unit 2, a local oscillator signal generating unit 3 and a clock signal generating unit 4;
the output ends of the reference working signal generating unit 1 and the intermediate frequency signal generating unit 2 are connected with the input end of the local oscillation signal generating unit 3; the output of the intermediate frequency signal generation unit 3 is connected to the input of the clock signal generation unit 4. Specifically, the reference working signal generating unit 1 is configured to perform N-frequency multiplication on an INPUT source signal INPUT to obtain a required reference working signal REF, and output the required reference working signal REF to the local oscillator signal generating unit; where N is the ratio of the frequency of the desired reference operating signal REF to the frequency of the source signal INPUT. The intermediate frequency signal generating unit 2 is configured to perform M frequency division on the INPUT source signal INPUT to obtain an intermediate frequency signal IF, and output the intermediate frequency signal IF to the local oscillator signal generating unit and the clock signal generating unit. The local oscillation signal generating unit 3 is configured to mix the intermediate frequency signal IF with the reference working signal REF to obtain a desired local oscillation signal LO. The clock signal generating unit 4 is configured to multiply the intermediate frequency signal IF by 4 to obtain the required clock signal CLK. It should be noted that, the DLLRF post-stage system measures and controls the amplitude and phase of the microwave field high-frequency RF signal by using a digital IQ method, the method requires the frequency of the clock signal CLK to be 4 times of the sampling frequency, the frequency of the intermediate frequency signal IF in the present invention is the sampling frequency in the digital IQ method, and therefore the required clock signal CLK is obtained by multiplying the frequency of the intermediate frequency signal IF by 4.
It should be noted that, in order to avoid cascade connection of multiple stages of frequency dividers, the present invention uses a source signal INPUT at an intermediate frequency point to implement frequency conversion from the middle up and down, a local oscillator signal LO is obtained from a reference working signal REF and an intermediate frequency signal IF difference frequency, and a clock signal CLK is obtained from an intermediate frequency signal IF by 4-fold frequency; the front-end signal synthesis module is a frequency multiplication and division parallel structure, wherein the primary structure is a parallel reference working signal generation unit and an intermediate frequency signal generation unit, and the secondary structure is a parallel local oscillator signal generation unit with the internal function of frequency mixing and a clock signal generation unit with the internal function of 4-frequency multiplication. The structure not only can ensure the coherence among the local oscillation signal, the clock signal and the reference working signal, but also avoids using a deeper cascade structure, and can obtain a larger frequency range while overcoming the problem of cascade noise.
Preferably, the reference operating signal generating unit includes: the first frequency multiplier and the first filter are connected in series; the intermediate frequency signal generating unit includes: a frequency divider and a second filter connected in series; the local oscillation signal generating unit comprises a mixer and a third filter which are connected in series; the clock signal generating unit comprises a second frequency multiplier and a fourth filter which are connected in series. Referring to fig. 2, the reference working signal generation process is as follows, as shown in fig. 2: the source signal INPUT passes through the first frequency multiplier 11 to realize N frequency multiplication to obtain a signal REFrawThe main component of which is a signal having a frequency corresponding to the desired reference operating signal REFNumber, containing a small number of harmonics, is passed through a first filter 12 to signal REFrawThe signal without harmonic, that is, the required reference working signal REF, is obtained by filtering, and is output to the local oscillator signal generating unit 3 while being output by the front end signal synthesizing module. The intermediate frequency signal generation process is as follows: the signal INPUT is passed through a frequency divider 21 to implement M frequency division to obtain a signal IFrawWhose main component is a signal having a frequency corresponding to the intermediate frequency signal IF and containing a small amount of high frequency harmonics, the signal IF is passed through the second filter 22rawThe signal without harmonic, that is, the intermediate frequency signal IF, is obtained by filtering, and is input to the local oscillator signal generating unit 3 and the clock signal generating unit 4, respectively. The local oscillation signal generation process is as follows: the intermediate frequency signal IF and the reference operating signal REF are input to a mixer 31 to obtain a signal LOrawWhose main component is a signal whose frequency is identical to that of the local oscillator signal LO and which contains a small amount of intermodulation components generated by the mixer, the signal LO is filtered by a third filter 32rawFiltering to obtain a signal without intermodulation component, namely the required local oscillator signal LO; the frequency of the local oscillator signal LO is the difference between the reference operating signal REF and the frequency of the intermediate frequency signal IF. The clock signal generation process is as follows: the IF signal is passed through a second frequency multiplier 41 to realize 4 frequency multiplication to obtain a CLK signalrawThe main component is a signal having a frequency identical to the clock signal CLK and containing a small amount of harmonics, and the signal is filtered by the fourth filter 42 to obtain a signal without harmonics, that is, the desired clock signal CLK.
Further, REF is based on the frequency distribution of harmonic and intermodulation componentsraw、LOrawAnd CLKrawThe main harmonics in the signal are distributed on both sides of the main frequency, and the IFrawSince signal harmonics are mainly distributed at a high frequency of the main frequency, it is preferable that the first filter, the third filter, and the fourth filter are all band-pass filters, and the second filter is a low-pass filter. The passive mixer does not need external power supply, so that the influence of noise introduced by the active mixer into an active circuit can be avoided, and the upper mixer is preferably a passive mixer.
To further illustrate the front-end signal synthesis module provided by the present invention, details will be described below with reference to a specific embodiment, in this embodiment, the INPUT signal is a source signal INPUT with a frequency of 357MHz, and the output signals are a reference working signal REF with a frequency of 2856MHz, a local oscillator LO with a frequency of 2830.5MHz, and a clock signal CLK with a frequency of 102 MHz.
Specifically, as shown in fig. 3, a reference working signal REF with a frequency of 2856MHz is obtained by sequentially passing a source signal INPUT through a first frequency multiplier 11 and a first filter 12; the first frequency multiplier 11 is an 8-frequency multiplier, and the first filter 12 is a band-pass filter with a center frequency of 2856MHz and a bandwidth of 50 MHz. An intermediate frequency signal IF with the frequency of 25.5MHz is obtained by sequentially passing a source signal INPUT through a frequency divider 21 and a second filter 22; the frequency divider 21 is a 14-frequency divider, and the second filter 22 is a low-pass filter with a passband frequency of 30MHz and a stopband frequency of 50 MHz. A local oscillation signal LO with the frequency of 2830.5MHz is obtained by filtering through a third filter 32 after frequency mixing of an intermediate frequency signal IF and a reference working signal REF through a mixer 31; the third filter is a band-pass filter with a center frequency of 2830.5MHz and a bandwidth of 18MHz, and is used for filtering the intermodulation component generated by the mixer 31. A clock signal CLK with a frequency of 102MHz is obtained by sequentially passing an intermediate frequency signal IF through the second frequency multiplier 41 and the fourth filter 42; the second frequency multiplier 41 is a 4-frequency multiplier, and the fourth filter 42 is a band-pass filter with a center frequency of 102MHz and a bandwidth of 50 MHz.
It should be noted that, since the overall structure operating frequency of the front-end signal synthesis module is 0-3GHz, all the connection lines have an operating frequency of 0-3GHz, and in order to avoid environmental noise and mutual interference between the modules, a transmission line with a frequency efficiency of 80dB is used.
Furthermore, in order to avoid the influence of environmental noise interference and temperature change, the front-end signal synthesis module is placed in a constant temperature box body with an electromagnetic shielding function; in order to conveniently interconnect the DLLRF system in an integral structure, the INPUT end of a source signal INPUT, the output end of a reference working signal REF, the output end of a local oscillator signal LO and the output end of a clock signal CLK are SMA interfaces.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A front end signal synthesis module for an accelerator low level control system, comprising: the device comprises a reference working signal generating unit, an intermediate frequency signal generating unit, a local oscillator signal generating unit and a clock signal generating unit;
the output ends of the reference working signal generating unit and the intermediate frequency signal generating unit are connected with the input end of the local oscillation signal generating unit; the output end of the intermediate frequency signal generating unit is connected with the input end of the clock signal generating unit;
the reference working signal generating unit is used for carrying out N frequency multiplication on the INPUT source signal INPUT to obtain a required reference working signal REF and outputting the required reference working signal REF to the local oscillator signal generating unit;
the intermediate frequency signal generating unit is used for performing M frequency division on an INPUT source signal INPUT to obtain an intermediate frequency signal IF and outputting the intermediate frequency signal IF to the local oscillator signal generating unit and the clock signal generating unit;
the local oscillation signal generating unit is used for mixing the intermediate frequency signal IF and the reference working signal REF to obtain a required local oscillation signal LO;
the clock signal generating unit is used for carrying out 4-frequency multiplication on the intermediate frequency signal IF to obtain a required clock signal CLK.
2. The front-end signal synthesis module of claim 1, wherein the reference working signal generation unit comprises: the first frequency multiplier and the first filter are connected in series; the first filter is a band-pass filter;
after the source signal INPUT is subjected to frequency multiplication by the first frequency multiplier, a signal REF carrying a harmonic signal is obtainedraw，REFrawAnd filtering by the first filter to obtain a required reference working signal REF.
3. The front-end signal synthesis module of claim 1, wherein the intermediate frequency signal generation unit comprises: a frequency divider and a second filter connected in series; the second filter is a low-pass filter;
after the frequency of the source signal INPUT is divided by the frequency divider, a signal IF carrying a harmonic signal is obtainedraw，IFrawAnd filtering the intermediate frequency signal by the second filter to obtain an intermediate frequency signal IF.
4. The front-end signal synthesis module of claim 1, wherein the local oscillator signal generation unit comprises a mixer and a third filter connected in series; the third filter is a band-pass filter;
after the reference working signal REF and the intermediate frequency signal IF are mixed by the mixer, a signal LO carrying an intermodulation component is obtainedrawAnd the local oscillation signal is input to the third filter for filtering to obtain a required local oscillation signal LO; the frequency of the local oscillator signal LO is the difference between the reference operating signal REF and the frequency of the intermediate frequency signal IF.
5. The front-end signal synthesis module of claim 4, wherein the mixer is a passive mixer.
6. The front-end signal synthesis module of claim 1, wherein the clock signal generation unit comprises a second frequency multiplier and a fourth filter connected in series; the fourth filter is a band-pass filter;
the intermediate frequency signal IF passes through the second frequency multiplier to realize 4 times of frequency multiplication to obtain a signal CLK carrying a harmonic signalraw，CLKrawAnd filtering by the fourth filter to obtain the required clock signal CLK.
7. The front-end signal synthesis module of claim 1, wherein the connection lines are transmission lines having an operating frequency in the range of 0-3GHz and a shielding efficiency of 80 dB.
8. The front-end signal synthesis module of any one of claims 1 to 7, wherein the INPUT terminal of the source signal INPUT, the output terminal of the reference working signal REF, the output terminal of the local oscillator signal LO, and the output terminal of the clock signal CLK are SMA interfaces when placed in a thermostatic box with electromagnetic shielding function.
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