CN111952938A - Input protection circuit and method of power supply - Google Patents
Input protection circuit and method of power supply Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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Abstract
The embodiment of the application provides an input protection circuit and a method of a power supply, which comprises the following steps: the device comprises a detection circuit, a protection circuit, a bootstrap circuit and a control switch circuit; the detection circuit is used for providing the detected input electric signal to the protection circuit; the protection circuit is used for providing a first logic level for the control circuit under the condition that the input electric signal is determined not to meet a first preset condition; the bootstrap circuit is used for providing a conducting logic level for the control circuit; the control circuit is used for controlling the first switching tube to be switched off according to the first logic level and the conducting logic level.
Description
Technical Field
The present disclosure relates to power management protection technologies, and in particular, to an input protection circuit and method for a power supply.
Background
In the related art, a dedicated power management protection chip is generally adopted, the cost of the dedicated power management protection chip is relatively high, other types of devices are generally included in a power supply, and the compatibility between different types of devices is also poor.
Disclosure of Invention
Embodiments of the present application are intended to provide an input protection circuit and method for a power supply.
In a first aspect, an embodiment of the present application provides an input protection circuit for a power supply, including: the circuit comprises a detection circuit, a protection circuit, a bootstrap circuit and a control switch circuit, wherein the control switch circuit comprises a first switching tube circuit and a control circuit; the first switching tube circuit comprises a first switching tube; the detection circuit is used for providing the detected input electric signal to the protection circuit; the input electrical signal comprises a current signal and/or a voltage signal; the protection circuit is used for providing a first logic level for the control circuit under the condition that the input electric signal is determined not to meet a first preset condition; the bootstrap circuit is used for providing a conducting logic level for the control circuit; the control circuit is used for controlling the first switching tube to be switched off according to the first logic level and the conducting logic level.
In a second aspect, an embodiment of the present application provides an input protection method for a power supply, which is applied to an input protection circuit, where the input protection circuit includes: the circuit comprises a detection circuit, a protection circuit, a bootstrap circuit and a control switch circuit, wherein the control switch circuit comprises a first switching tube circuit and a control circuit; the first switching tube circuit comprises a first switching tube; the method comprises the following steps: the detection circuit provides the detected input electrical signal to the protection circuit; the input electrical signal comprises a current signal and/or a voltage signal; the protection circuit provides a first logic level to the control circuit under the condition that the input electric signal is determined not to meet a first preset condition; the bootstrap circuit provides a turn-on logic level to the control circuit; the control circuit controls the first switch tube to be switched off according to the first logic level and the conducting logic level.
In the embodiment of the application, the detection circuit, the protection circuit, the bootstrap circuit and the control switch circuit which form the input protection circuit of the power supply are all formed by universal discrete components, so that the cost is relatively low and the compatibility is good.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic diagram of a power management protection chip in the related art according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an input protection circuit of a power supply according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a detecting circuit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another exemplary embodiment of a detection circuit;
fig. 5A is a schematic structural diagram of a current protection circuit according to an embodiment of the present application;
fig. 5B is a schematic diagram of a structure of the voltage protection circuit according to the embodiment of the present disclosure;
fig. 6A is a schematic diagram illustrating a structure of a bootstrap circuit according to an embodiment of the present application;
FIG. 6B is a schematic diagram of another bootstrap circuit according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a second switching tube circuit according to an embodiment of the present disclosure;
fig. 8 is a schematic flow chart illustrating an implementation of a power input protection method according to an embodiment of the present application;
fig. 9 is a functional block diagram of an overall circuit according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the examples provided herein are merely illustrative of the present application and are not intended to limit the present application. In addition, the following examples are provided as partial examples for implementing the present application, not all examples for implementing the present application, and the technical solutions described in the examples of the present application may be implemented in any combination without conflict.
It should be noted that in the embodiments of the present application, the terms "comprises", "comprising" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a method or apparatus including a series of elements includes not only the explicitly recited elements but also other elements not explicitly listed or inherent to the method or apparatus. Without further limitation, the use of the phrase "including a. -. said." does not exclude the presence of other elements (e.g., steps in a method or elements in a device, such as portions of circuitry, processors, programs, software, etc.) in the method or device in which the element is included.
The term "and/or" herein is merely an association relationship describing an associated object, and means that there may be three relationships, e.g., U and/or W, which may mean: u exists alone, U and W exist simultaneously, and W exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of U, W, V, and may mean including any one or more elements selected from the group consisting of U, W and V.
Fig. 1 is a schematic diagram of a power management protection chip in the related art according to an embodiment of the present application, and as shown in fig. 1, the chip needs to be specifically configured or converted according to actual needs during a use process, so that compatibility is not very high, and cost is relatively high.
In view of the above-mentioned technical problems, the present application provides an input protection circuit for a power supply.
Fig. 2 is a schematic diagram of a structure of an input protection circuit of a power supply according to an embodiment of the present application, and as shown in fig. 2, the input protection circuit of the power supply may include: the circuit comprises a detection circuit 201, a protection circuit 202, a bootstrap circuit 203 and a control switch circuit 204, wherein the control switch circuit 204 comprises a first switching tube circuit 2041 and a control circuit 2042; the first switching tube circuit 2041 comprises a first switching tube 20411;
the detection circuit 201 is used for providing the detected input electric signal to the protection circuit 202; the input electrical signal comprises a current signal and/or a voltage signal;
the protection circuit 202 is configured to provide a first logic level to the control circuit 2042 when it is determined that the input electrical signal does not meet a first preset condition;
the bootstrap circuit 203 is configured to provide a conducting logic level to the control circuit 2042;
the control circuit 204 is configured to control the first switching tube 20411 to turn off according to the first logic level and the conducting logic level.
Here, the on logic level is a driving voltage range determined according to the model of the selected first switching tube. In one example, the corresponding driving voltage range may be looked up from the data sheet of the first switching tube to obtain the turn-on logic level.
For example, in the case that the driving voltage range corresponding to the first switch tube of the model a is 2V to 4V, the determined on logic level is 2V to 4V or a voltage range including 2V to 4V, for example, the determined on logic level may be 2V to 5V.
In one example, a logic low level may refer to a voltage having a voltage value of less than 0.5V, for example, a voltage having a voltage value of 0V; a logic high level may refer to a voltage having a voltage value greater than 3.3V or 5V, for example, a voltage having a voltage value of 6V.
In one example, the first switch tube may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), or the like, and is not particularly limited herein.
In one embodiment, the first logic level protection circuit 202 may provide a logic low level to the control circuit 2042 if it is determined that the input electrical signal meets a first preset condition; in the case where it is determined that the input electrical signal meets the second preset condition, a logic high level is provided to the control circuit 2042.
Here, the first preset condition and the second preset condition may be opposite, the first preset condition may include a first voltage preset condition and a first current preset condition, and the second preset condition may also include a second voltage preset condition and a second current preset condition. For example, the first preset condition may be that the voltage is greater than 10V and the current is greater than 5A, and the corresponding second preset condition may be that the voltage is less than 8V and the current is less than 4A; the first preset condition is that the voltage is less than 5V and the current is greater than 6A, and the corresponding second preset condition may be that the voltage is greater than 6V and the current is less than 5A. The first preset condition and the second preset condition may be voltage and/or current ranges determined according to actual requirements, and are not particularly limited herein.
For the implementation manner of controlling the first switch tube 20411 to turn off according to the first logic level and the conducting logic level, a first control signal may be determined according to the first logic level, and the first switch tube 20411 may be controlled to turn off according to the first control signal and the conducting logic level. Here, the implementation manner of determining the first control signal according to the first logic level may be that, when the first logic level is a logic low level, the first control signal of the first switching tube is determined to be a low-level control signal; and determining that the second control signal of the first switching tube is a high-level control signal under the condition that the first logic level is a logic high level.
It can be seen that the detection circuit, the protection circuit, the bootstrap circuit and the control switch circuit which constitute the input protection circuit of the power supply are all formed by common separate elements, so that the cost is relatively low and the compatibility is good.
In some possible embodiments, the protection circuit 202 may include: a current protection circuit 2021, configured to provide a first logic level to the control circuit 204 when it is determined that the current signal does not meet a preset first current preset condition; and/or, the voltage protection circuit 2022 is configured to provide the first logic level to the control circuit 204 when it is determined that the voltage signal does not meet a preset first voltage preset condition.
In one example, the first current preset condition may be that a current value of the current signal is greater than a first current threshold; the first voltage preset condition may be that the voltage value of the voltage signal is greater than a first voltage threshold or less than a second voltage threshold.
In one embodiment, the current protection circuit 2021 may provide a logic low level to the control circuit 204 when the current signal is determined not to meet a preset first current preset condition, and provide a logic high level to the control circuit 204 when the current signal is determined to meet a second current preset condition.
In one example, the second current preset condition may be that a current value of the current signal is less than a second current threshold; the second voltage preset condition may be that the voltage value of the voltage signal is less than the third voltage threshold or greater than the fourth voltage threshold. For example, the first current threshold may be 10A, the second current threshold may be 8A, the first voltage threshold may be 12V, the second voltage threshold may be 4V, the third voltage threshold may be 10V, and the fourth voltage threshold may be 5V, that is, a logic low level may be provided to the control circuit 204 in a case where a current value of the current signal is greater than 10A, a voltage value of the voltage signal is greater than 12V, or a voltage of the voltage signal is less than 4V, and a logic high level may be provided to the control circuit 204 in a case where a current value of the current signal is less than 8A, a voltage value of the voltage signal is less than 10V, or a voltage of the voltage signal is greater than 5V.
In one embodiment, the detection circuit includes a sampling resistor, a differential amplifier, and a voltage follower; one end of the sampling resistor is connected to the power supply input end, and the other end of the sampling resistor is connected to the power supply output end; the first input end of the differential amplifier is connected to a common node of the sampling resistor and the power supply input end, and the second input end of the differential amplifier is connected to a common node of the sampling resistor and the power supply output end; the input end of the voltage follower is connected to the output end of the differential amplifier.
The sampling resistor can sense the current flowing through the sampling resistor to obtain a voltage signal on the sampling resistor, and the differential amplifier can amplify the voltage signal acquired by the sampling resistor; the voltage follower can follow the voltage signal amplified by the differential amplifier, so that the buffering and the isolation of the signal are realized.
In one example, the amplifying differential amplifier may be a precision, rail-to-rail or Over-the-TOP (i.e., an input other than the power rail) input capability operational amplifier, or a precision, rail-to-rail or Over-the-TOP input capability operational amplifier and a resistor comprising a classical differential amplifier.
FIG. 3 is a schematic diagram of a detecting circuit according to an embodiment of the present disclosure; as shown in fig. 3, the detection circuit includes a sampling resistor Rsen1, an operational amplifier OPA1, a first resistor R1, a second resistor R2, a third resistor R3, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Q1, an operational amplifier OPA2, a first diode D1, an input terminal Vin1 of a power supply, and an output terminal Vout1 of the power supply, wherein Rsen1 is connected between Vin1 and Vout1, one end of R1 is connected to a negative input terminal of OPA1, the other end of R1 is connected to a common node of Rsen1 and Vin1, and a positive input terminal of OPA1 is connected to a common node of Rsen1 and Vout 1; the output of OPA1 is connected to the gate of Q1, the source of Q1 is connected to the negative input of OPA1 and the common node of R1, and R2 is connected between the drain of Q1 and the common ground node; the common point of the drains of R2 and Q1 is connected to the positive input of OPA 2; the output end of the OPA2 is connected to the positive electrode of the D1, the negative electrode of the D1 is connected to the negative input end of the OPA2, negative feedback is formed, and a voltage follower is obtained; r3 is connected between the negative terminal of D1 and the common ground node. The common node of D1 and R3 is the output of the detection circuit 201.
When the input current passes through the sampling resistor Rsen1, the input current is connected to the second end of the sampling resistor Rsen1 according to the ampere theorem.
When the input current flows through Rsen1, a voltage drop Vsen is generated across Rsen1, see formula (1);
Vsen＝I1*Rsen1 (1)；
wherein, I1 represents the current value of the current passing through Rsen1, and Rsen1 represents the resistance value of the sampling resistor; a negative feedback amplifier composed of OPA, R1, R2 and Q1 can obtain the voltage Vo1 generated on R2 according to the virtual short and virtual break principles of the operational amplifier, and the formula (2) is shown;
Vo1＝R2*(Vsen/R1)＝R2*I1*Rsen1/R1, (2)；
wherein, R2 represents the resistance of the second resistor, and the current I2 on the line can be obtained according to the voltage output on R2, see formula (3);
I2＝Vo1*R1/(R2*Rsen1) (3)；
FIG. 4 is a schematic diagram of another exemplary embodiment of a detection circuit; as shown in fig. 4, the differential amplifier includes: the power supply comprises a sampling resistor Rsen2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an operational amplifier OPA3, a reference given voltage Vref1, an input end Vin2 of the power supply and an output end Vout2 of the power supply. Wherein Rsen2 is connected between Vin2 and Vout 2; one end of R4 is connected to the positive input of OPA3, and the other end of R4 is connected to the common node of Rsen2 and Vin 2; one end of R5 is connected to the negative input terminal of OPA3, and the other end of R5 is connected to the common node of Rsen2 and Vout 2; one end of R6 is connected to the common node of R4 and the positive input of OPA3, the other end of R6 is connected to Vref 1; one end of the R7 is connected to the common node of the negative inputs of the R5 and OPA3, and the other end of the R7 is connected to the output of the OPA 3. The output of OPA3 is the detection circuit 201 output.
Here, R4 ═ R5 and R6 ═ R7 are required, and the output voltage V02 of the operational amplifier OPA3 can be obtained according to the principle of virtual short and virtual break of the operational amplifier, see formula (4);
Vo2＝Vref1+Vsen2*R6/R4＝Vref1+I*Rsen2*R6/R4 (4)；
further, the current Isen2 flowing through Rsen2 can be obtained, see formula (5)
Isen2＝(Vo2-Vref1)*R4/(Rsen2*R6) (5)；
Here, the reference given voltage Vref1 may be GND, but may be influenced by the output capability of the operational amplifier Vo2, even if the low level output capability of the rail-to-rail operational amplifier cannot completely reach the negative rail voltage, and a certain Vref1 voltage is generally applied to avoid such influence. The same consideration is given to the fact that the output of the voltage follower in fig. 3 is connected in series with a diode (single power supply).
In one example, the output accuracy of the detection circuit 201 is also affected by the accuracy of the resistances of the peripheral resistors R4, R5, R6 and R7, and it is contemplated to use a differential operational amplifier integrated with the peripheral resistors, such as the INA21x series of TI, to reduce the effect of the resistance accuracy.
In one embodiment, the current protection circuit 2021 may include a first hysteretic comparator with power supply input current over-current hysteretic protection.
In one embodiment, the voltage protection circuit 2022 may include: a second hysteresis comparator with power supply input voltage over-voltage hysteresis protection and a third hysteresis comparator with power supply input voltage under-voltage hysteresis protection.
It is to be understood that the first hysteresis comparator and the second hysteresis comparator may be implemented by inverting inputs and the third hysteresis comparator may be implemented by non-inverting inputs.
Fig. 5A is a schematic diagram of a structure of a current protection circuit according to an embodiment of the present disclosure, and as shown in fig. 5A, the current protection circuit 2021 includes: the operational amplifier OPA4, the eighth resistor R8, the ninth resistor R9 and the reference given voltage Vref2, wherein R8 is connected between Vref2 and the positive input end of OPA4, one end of R9 is connected to the common node of the positive input ends of R8 and OPA4, and the other end of R9 is connected to the output end of OPA 4. The negative input of OPA4 is connected to the output of detection circuit 201. The output end of the OPA4 is the output end UO1 of the current protection circuit 2021
Fig. 5B is a schematic diagram of a structure of the voltage protection circuit according to the embodiment of the present application, and as shown in fig. 5B, the voltage protection circuit 2022 includes: an operational amplifier OPA5, an operational amplifier OPA6, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an input end Vin3 of a power supply, a reference given voltage URH and a reference given voltage URL, wherein the R10 and the R11 are connected in series to form a first series branch, and the first series branch is connected between the Vin3 and a common ground node; connecting the common node of R10 and R11 to the negative input of OPA 5; r14 is connected between URH and the positive input of OPA 5; one end of R15 is connected to the common point of R14 and the positive input of OPA5, the other end of R15 is connected to the output of OPA 5; the output end of the OPA5 is the output end UO2 of the voltage protection circuit 2022; r12 and R13 are connected in series to form a second series branch, which is connected between Vin3 and the common ground node, one end of R16 is connected to the common node of R12 and R13, and the other end of R16 is connected to the positive input of OPA 6; one end of R17 is connected to the common node of the positive inputs of R16 and OPA6, and the other end of R17 is connected to the output of OPA 6; the negative input of OPA6 is connected to the URL; the output terminal of the OPA6 is the output terminal UO3 of the voltage protection circuit 2022.
In one example, the current protection circuit shown in fig. 5A is an overcurrent protection circuit, the output logic high level of the current protection circuit 2021 may be Voh, the output logic low level of the current protection circuit 2021 may be 0, the corresponding preset high threshold may be Uth +, and the corresponding hysteresis threshold may be Uth —, see formula (6) and formula (7);
Uth+＝(Voh-Vref2)*R8/(R8+R9)+Vref2 (6)；
Uth-＝Vref2*R9/(R8+R9) (7)；
when the voltage value of the output end of the detection circuit 201 is greater than the preset high threshold Uth +, the current protection circuit 2021 converts the output logic high level Voh to the output logic low level 0; when the voltage value at the output of the detection circuit 201 is smaller than the hysteresis threshold Uth-, the current protection circuit 2021 will switch from an output logic low level 0 to an output logic high level Voh.
In an example, the current protection circuit 2021 may be a power input current overcurrent hysteresis protection circuit, that is, the protection circuit is triggered after the power input current exceeds a preset high threshold current, and the protection circuit is not immediately released after the current drops to the preset high threshold current, and the protection circuit needs to be released after the current drops to a certain value lower than the high threshold, for example, the preset high threshold current value is 38A, the protection circuit is triggered immediately after the power input current value exceeds 38A, and the protection circuit needs to be released after the power input current value drops to below 26A, so as to recover power supply.
Similarly, 501 in the voltage protection circuit 2022 shown in fig. 5B may be an over-voltage hysteresis protection circuit, the voltage at the input terminal of the over-voltage hysteresis protection circuit is Vin3, and when the voltage value of Vin3 exceeds the preset high threshold URH1, the output terminal UO1 will change from the logic high level Voh to the output logic low level 0; when the voltage value of Vin3 is less than the hysteresis threshold URL1, the output UO1 will transition from a logic low level of 0 to an output logic high level Voh. The difference between the preset high threshold URH1 and the hysteresis threshold URL1 may constitute the hysteresis width. Here, URH1, URL1 may be determined from the URL and the corresponding resistances R10, R11, R14, and R15.
In one example, the input voltage over-voltage hysteresis protection circuit, that is, the input voltage over-voltage protection circuit triggers the open-circuit protection after exceeding URH1, the protection is not immediately released when the voltage drops to URH1, and the protection is not released until the voltage drops to below URL1, for example, URH1 is 15V, URL1 is 14V, the open-circuit protection is immediately triggered when the input voltage over-voltage 15V, and the protection needs to drop below 14V to release the protection, so that the power supply is recovered.
502 of the voltage protection circuit 2022 shown in fig. 5B may be an under-voltage hysteresis protection circuit, the voltage at the input terminal of the under-voltage hysteresis protection circuit is Vin3, and when the voltage value of Vin3 is lower than the preset low threshold URL2, the output terminal Uo2 may transform from a logic high level Voh to an output logic low level 0; when the voltage value of Vin3 is greater than the preset high threshold URH2, the output Uo2 may transition from a logic low level of 0 to an output logic high level of Voh. Here, URH2, URL2 may be determined from the URL and the corresponding resistances R12, R13, R16, and R17.
In one example, the power input voltage under-voltage hysteresis protection circuit triggers the open-circuit protection when the power input voltage is lower than URL2, and does not immediately release the protection when the voltage rises to URL2, and needs to rise to URH2 to release the protection, for example, URL2 is 9V and URH2 is 10V, the open-circuit protection is triggered immediately when the power input voltage is lower than 9V, and needs to rise back to above 10V to release the protection and restore the power supply.
In an example, the output ends of the current protection circuit 2021 and the voltage protection circuit 2022 may be subjected to a logical and operation, a control signal of the first switch tube is obtained according to a result of the logical and operation, and then the first switch tube is controlled to be turned off according to the control signal and the on logic level of the first switch tube, where the first switch tube may be an N-type Metal Oxide Semiconductor (NMOS). The current carrier of a P-type Metal Oxide Semiconductor (pmos) switch is only one third of the NMOSE, and the nmos switch is generally used in a high-current scene on a power supply, and has few pmos types and high price.
In one example, in the under-voltage hysteresis protection circuit, R16 and R17 form a positive feedback loop, the hysteresis width of the under-voltage hysteresis protection circuit is related to URL and Uo3, and series divider resistors R12 and R13 also have influence, so in order to reduce the influence, it is necessary to take R16 and R17 resistance values to be far greater than R12 and R13, and at this time, the influence can be ignored.
In one embodiment, the bootstrap circuit includes: a pulse generator and an N voltage doubling circuit; the output end of the pulse generator is connected to the input end of the N voltage doubling circuit, wherein the pulse generator is used for generating square waves with specific frequency; the N voltage doubling circuit is used for performing voltage doubling rectification on the square waves generated by the pulse generator to obtain the conducting logic level.
Here, the pulse generator may be a general timer.
In one example, for a high-current scenario, since the control voltage of the first switching tube (NMOS switch) needs to be higher than the input voltage on the line, a bootstrap circuit is needed to provide a conducting logic level to the gate of the first switching tube (NMOS switch), so that the first switching tube (NMOS switch) can be normally saturated and conducted.
In a possible implementation manner, since the grid electrode of the first switching tube (NMOSE switch) has a large impedance, the requirement of the boost circuit on the current output capability is low, and therefore, a general timer and a voltage-doubling rectifying circuit can be adopted to form the bootstrap circuit. The oscillating pulse which can be generated by the general timer is rectified by the diode rectifying circuit and then is charged to the capacitor, so that the capacitor is charged to the input power supply voltage, and the rectifying-charging circuit is connected step by step, so that the booster circuit which is 2 times, 3 times, 4 times or even more times of the input power supply voltage can be obtained.
The following provides a bootstrap circuit, which generally includes a pulse generator and an N-fold voltage circuit. The embodiment of the application provides a bootstrap circuit, which includes a pulse generator and a 2-time voltage doubling circuit, as shown in fig. 6A, the pulse generator includes a timer and a peripheral circuit, the timer includes pins 1 to 8, the peripheral circuit includes an eighteenth resistor R18, a nineteenth resistor R19, a first capacitor C1, a second capacitor C2, a third capacitor C3 and an input terminal Vin4 of a power supply. Wherein R18, R19 and C2 are connected in series to form a third series branch, a branch formed by connecting the third series branch in parallel with C1 is connected between Vin4 and a common ground node, pin 4 and pin 8 are connected to common nodes of Vin4, C1 and R18, pin 7 is connected to a common node of R18 and R19, pin 2 is connected to pin 6, a common node of pin 2 and pin 6 is connected to a common node of R19 and C2, pin 1 is connected to the common ground node, and C3 is connected between pin 5 and the common ground node; pin 3 is the output Vout3 of the pulse generator.
The 2-time voltage circuit may include: a first diode VD1, a second diode VD2, a fourth capacitor C4, and a fifth capacitor C5;
a fourth series branch formed by connecting the cathode of the VD1 with the anode of the C4 is connected between the Vin4 and the pin 3, the anode of the VD1 is connected to the Vin4, and the cathode of the C4 is connected to the pin 3; a fifth serial branch formed by connecting the anode of the C5 with the cathode of the VD2 is connected with the VD1 in parallel, the anode of the VD2 is connected with the common node of the VD1 and the C4, and the cathode of the C5 is connected with the common node of the VD1 and the Vin 4; the common node of the C5 and the VD2 is the output terminal Vout4 of the 2-fold circuit.
An embodiment of the present application further provides a bootstrap circuit, which includes a pulse generator and a3 × voltage circuit, as shown in fig. 6B, the pulse generator in fig. 6B is the same as the pulse generator in fig. 6A, and the 3 × voltage circuit in fig. 6B may include: a third diode VD3, a fourth diode VD4, a fifth diode VD5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8;
a sixth series branch formed by connecting the anode of the C6 and the cathode of the VD3 in series is connected between the Vin4 and the pin 3, and the cathode of the C6 is connected to a common node of the Vin4, the R18, the pin 4 and the pin 8; the anode of VD3 is connected to pin 3; a seventh serial branch formed by connecting the cathode of the VD4 with the anode of the C7 is connected with the VD3 in parallel, the anode of the VD4 is connected with the common node of the VD3 and the C6, and the cathode of the C7 is connected with the common node of the VD3 and the pin 3; an eighth series branch formed by connecting the anode of the C8 with the cathode of the VD5 is connected with the VD4 in parallel, the cathode of the C8 is connected with a common node of the C6, the VD3 and the VD4, the anode of the VD5 is connected with a common node of the VD4 and the C7, and the common node of the C8 and the VD5 is the output end Vout5 of the 3-time circuit.
In one embodiment, the apparatus may further include a soft start circuit connected to an input of the bootstrap circuit.
Here, the slow start circuit can include slow start resistance and slow start electric capacity, will slowly start resistance and slowly start electric capacity and establish ties and form resistance capacitance RC charging circuit to obtain the slow start circuit, and then, can realize the hot plug protection.
In one embodiment, the apparatus may further include: the second switching tube circuit is used for preventing the reverse connection of the power supply; the second switching tube circuit comprises a second switching tube, a grid resistor and a voltage stabilizer, wherein the grid resistor is connected between the anode of the input power supply and the grid of the second switching tube, the source electrode of the second switching tube is connected to the cathode of the input power supply, and the drain electrode of the second switching tube is connected to the power supply ground; one end of the voltage stabilizer is connected to a common node of the grid electrode of the second switching tube and the grid electrode resistor, and the other end of the voltage stabilizer is connected to a common node of the source electrode of the second switching tube and the power ground.
Fig. 7 is a schematic diagram illustrating a structure of a second switching tube circuit according to an embodiment of the present application, and as shown in fig. 7, when the input terminal Vin + of the power supply is a normal voltage, a body diode in the second switching tube (low side NMOSE switch) is turned on, so that Ugs is increased and the second switching tube is turned on; when the input end Vin + of the power supply is reverse voltage, Ugs is 0, the second switch tube is cut off and cannot be conducted. Therefore, the back-end circuit is not affected by this reverse voltage at all. Therefore, the power source reverse connection prevention protection is carried out through the second switch tube, the power source reverse connection prevention protection can be used in a heavy current scene, a front end fuse does not need to be burnt, and normal power supply can be carried out after the reverse connection of the power source is removed. Here, Vin + may be Vin 1.
In one embodiment, the control circuit includes wired and logic circuitry.
For an implementation of the wired-and-logic circuit, the wired-and-logic circuit may include, for example, a first transistor T1, a second transistor T2, a third transistor T3, a twentieth resistor R20, a twenty-first resistor R21, and a twenty-second resistor R22, wherein: the base of T1 is connected to the output of the first hysteretic comparator, the base of T2 is connected to the output of the second hysteretic comparator, the base of T3 is connected to the output of the third hysteretic comparator, and the emitters of T1, T2 and T3 are all connected to a common ground node; collectors of T1, T2, and T3 are connected to one ends of R20, R21, and R22, respectively, and the other ends of R20, R21, and R22 are connected to a power supply positive node of the logic circuit. Here, the power positive node of the logic circuit may be Vin3, Vin4, or the like, and is not particularly limited herein.
For another implementation of the wired-and-logic circuit, illustratively, the wired-and-logic includes a first general comparator COMP1, a second general comparator COMP2, a third general comparator COMP3, a twenty-third resistor R23, a twenty-fourth resistor R24, and a twenty-fifth resistor R25, and wherein: positive input ends of COMP1, COMP2 and COMP3 are connected to a power supply positive node of the logic circuit; negative input terminals of COMP1, COMP2 and COMP3 are connected to an output terminal of the first hysteresis comparator, an output terminal of the second hysteresis comparator and an output terminal of the third hysteresis comparator, respectively; output terminals of COMP1, COMP2 and COMP3 are respectively connected to one ends of R23, R24 and R25, and the other ends of R23, R24 and R25 are respectively connected to a power supply positive node of the logic circuit.
In one embodiment, the apparatus further comprises: a power supply monitoring chip; the detection circuit is further configured to provide the detected input electrical signal to the power supply monitoring chip, and the power supply monitoring chip performs Analog-to-Digital Converter (ADC) conversion on the input electrical signal to obtain a Digital input electrical signal; obtaining current input power according to the input digital electric signal, determining a second logic level according to the input power and preset power, and providing the second logic level for the control circuit; the control circuit is used for controlling the first switch tube to be switched off according to the first logic level, the second logic level and the conducting logic level.
Here, the power supply monitoring chip may be a general-purpose chip, for example, a Digital Signal Processing (DSP) chip or the like. According to the technical scheme provided by the embodiment of the application, the function of a special power management protection chip can be realized by combining a general chip with the circuit provided by the embodiment, so that the compatibility is improved.
In one example, the preset power may be a maximum power threshold set according to demand; the implementation manner of determining the second logic level according to the input power and the preset power may be that the input power is compared with a maximum power threshold, and the logic low level is determined as the second logic level when the input power is determined to be greater than the maximum power threshold; and determining the logic high level as a second logic level under the condition that the input power is determined to be less than or equal to the maximum power threshold value.
In one example, the first switching tube is controlled to be turned off according to the first logic level, the second logic level and the on logic level, which may be determining a second control signal of the first switching tube according to the first logic level and the second logic level, and controlling the first switching tube to be turned off according to the second control signal and the on logic level. And determining an implementation manner of the second control signal of the first switching tube according to the first logic level and the second logic level, which may be performing a logic and operation on the logic level output by the protection circuit and the logic level output by the power supply monitoring chip, and determining the logic level after the logic and operation as the second control signal.
The embodiment of the present application further provides an input protection method for a power supply, which is applied to the input protection circuit, where the input protection circuit includes: the circuit comprises a detection circuit, a protection circuit, a bootstrap circuit and a control switch circuit, wherein the control switch circuit comprises a first switching tube circuit and a control circuit; the first switching tube circuit comprises a first switching tube;
fig. 8 is a schematic diagram of an implementation flow of an input protection method for a power supply according to an embodiment of the present application, and as shown in fig. 8, the flow may include:
and step 804, the control circuit controls the first switch tube to be turned off according to the first logic level and the conducting logic level.
The specific implementation of the input protection method of the power supply has been described in the foregoing embodiments, and is not described herein again.
Fig. 9 is a functional block diagram of an overall circuit according to an embodiment of the present application, as shown in fig. 9, a sampling resistor Rsen and a first switching tube (power NMOS) are connected in series in a positive input terminal Vin + of an input power supply and an output terminal Vout + of the power supply, an input current can be determined by Rsen, an operational amplifier can amplify a voltage corresponding to the input current determined by Rsen, so as to facilitate overcurrent protection and power supply monitoring at a subsequent stage, a logic and operation is performed on a management control logic level determined by the power supply monitoring, a protection output logic level determined by overcurrent protection, undervoltage protection and overvoltage protection, a control signal of the first switching tube can be determined, and the turn-off of the first switching tube is controlled according to the control signal of the first switching tube and a turn-on logic level obtained after bootstrap boosting. Here, the hot plug protection of the input power supply can be realized through the RC slow start circuit; the negative input end Vin-of the input power supply is connected with a second switching tube in series, and the grid electrode of the second switching tube is connected to Vin + so as to realize the reverse connection protection of the input power supply.
While the present embodiments have been described with reference to the accompanying drawings, the present embodiments are not limited to the above-described embodiments, which are merely illustrative and not restrictive, and it will be apparent to those of ordinary skill in the art that many more modifications and variations can be made in the present embodiments without departing from the spirit of the disclosure and the scope of the appended claims.
Claims (10)
1. An input protection circuit for a power supply, comprising: the circuit comprises a detection circuit, a protection circuit, a bootstrap circuit and a control switch circuit, wherein the control switch circuit comprises a first switching tube circuit and a control circuit; the first switching tube circuit comprises a first switching tube;
the detection circuit is used for providing the detected input electric signal to the protection circuit; the input electrical signal comprises a current signal and/or a voltage signal;
the protection circuit is used for providing a first logic level for the control circuit under the condition that the input electric signal is determined not to meet a first preset condition;
the bootstrap circuit is used for providing a conducting logic level for the control circuit;
the control circuit is used for controlling the first switching tube to be switched off according to the first logic level and the conducting logic level.
2. The input protection circuit of claim 1, wherein the protection circuit comprises:
the current protection circuit is used for providing a first logic level for the control circuit under the condition that the current signal is determined not to accord with a preset first current preset condition; and/or the presence of a gas in the gas,
and the voltage protection circuit is used for providing a first logic level for the control circuit under the condition that the voltage signal is determined not to accord with a preset first voltage preset condition.
3. The input protection circuit of claim 1, wherein the detection circuit comprises a sampling resistor, a differential amplifier, and a voltage follower; wherein the content of the first and second substances,
one end of the sampling resistor is connected to the power supply input end, and the other end of the sampling resistor is connected to the power supply output end;
the first input end of the differential amplifier is connected to a common node of the sampling resistor and the power supply input end, and the second input end of the differential amplifier is connected to a common node of the sampling resistor and the power supply output end;
the input end of the voltage follower is connected to the output end of the differential amplifier.
4. The input protection circuit of claim 2, wherein the current protection circuit comprises: a first hysteresis comparator with power supply input current over-current hysteresis protection;
the voltage protection device includes: a second hysteresis comparator with power supply input voltage over-voltage hysteresis protection and a third hysteresis comparator with power supply input voltage under-voltage hysteresis protection.
5. The input protection circuit of claim 1, wherein the bootstrap circuit comprises: a pulse generator and an N voltage doubling circuit;
the output end of the pulse generator is connected to the input end of the N voltage doubling circuit, wherein the pulse generator is used for generating square waves with specific frequency; the N voltage doubling circuit is used for performing voltage doubling rectification on the square waves generated by the pulse generator to obtain the conducting logic level.
6. The input protection circuit of claim 5, further comprising: and the slow start circuit is connected to the input end of the bootstrap circuit.
7. The input protection circuit of claim 1, further comprising:
the second switching tube circuit is used for preventing the reverse connection of the power supply;
the second switching tube circuit comprises a second switching tube, a grid resistor and a voltage stabilizer, wherein the grid resistor is connected between the anode of the input power supply and the grid of the second switching tube, the source electrode of the second switching tube is connected to the cathode of the input power supply, and the drain electrode of the second switching tube is connected to the power supply ground; one end of the voltage stabilizer is connected to a common node of the grid electrode of the second switch tube and the grid electrode resistor, and the other end of the voltage stabilizer is connected to a common node of the source electrode of the second switch tube and the power ground.
8. The input protection circuit of claim 1, wherein the control circuit comprises a wired-and logic circuit.
9. The input protection circuit of claim 1, further comprising: a power supply monitoring chip;
the detection circuit is also used for providing the detected input electric signal to the power supply monitoring chip, and the power supply monitoring chip performs analog-digital ADC (analog-to-digital converter) conversion on the input electric signal to obtain a digital input electric signal; obtaining current input power according to the input digital electric signal, determining a second logic level according to the input power and preset power, and providing the second logic level for the control circuit;
the control circuit is used for controlling the first switch tube to be switched off according to the first logic level, the second logic level and the conducting logic level.
10. An input protection method of a power supply, which is applied to an input protection circuit, the input protection circuit comprising: the circuit comprises a detection circuit, a protection circuit, a bootstrap circuit and a control switch circuit, wherein the control switch circuit comprises a first switching tube circuit and a control circuit; the first switching tube circuit comprises a first switching tube;
the method comprises the following steps:
the detection circuit provides the detected input electrical signal to the protection circuit; the input electrical signal comprises a current signal and/or a voltage signal;
the protection circuit provides a first logic level to the control circuit under the condition that the input electric signal is determined not to meet a first preset condition;
the bootstrap circuit provides a turn-on logic level to the control circuit;
the control circuit controls the first switch tube to be switched off according to the first logic level and the conducting logic level.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112881787A (en) * | 2021-01-13 | 2021-06-01 | 常州同惠电子股份有限公司 | Low-input-impedance high-voltage circuit for voltage test and implementation method |
| CN113437736A (en) * | 2021-05-31 | 2021-09-24 | 济南浪潮数据技术有限公司 | Hot plug protection circuit and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101056047A (en) * | 2006-04-13 | 2007-10-17 | 中国科学院半导体研究所 | A power MOSFET driving circuit |
| JP2011222789A (en) * | 2010-04-12 | 2011-11-04 | Nec Corp | Input protection circuit and semiconductor integrated circuit |
| CN103368143A (en) * | 2013-08-02 | 2013-10-23 | 成都启臣微电子有限公司 | Overpower protection circuit for current-type switching power supply |
| CN204615366U (en) * | 2015-05-19 | 2015-09-02 | 成都欧安电气有限公司 | A kind of double-current defencive function power supply |
| CA2965212A1 (en) * | 2016-04-26 | 2017-10-26 | RAB Lighting Inc. | Bi-level low voltage dimming controller for lighting drivers |
| CN209692351U (en) * | 2019-04-10 | 2019-11-26 | 湖北亿咖通科技有限公司 | A kind of car networking equipment reverse-connection preventing circuit and vehicle electronic device |
-
2020
- 2020-07-31 CN CN202010757066.0A patent/CN111952938A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101056047A (en) * | 2006-04-13 | 2007-10-17 | 中国科学院半导体研究所 | A power MOSFET driving circuit |
| JP2011222789A (en) * | 2010-04-12 | 2011-11-04 | Nec Corp | Input protection circuit and semiconductor integrated circuit |
| CN103368143A (en) * | 2013-08-02 | 2013-10-23 | 成都启臣微电子有限公司 | Overpower protection circuit for current-type switching power supply |
| CN204615366U (en) * | 2015-05-19 | 2015-09-02 | 成都欧安电气有限公司 | A kind of double-current defencive function power supply |
| CA2965212A1 (en) * | 2016-04-26 | 2017-10-26 | RAB Lighting Inc. | Bi-level low voltage dimming controller for lighting drivers |
| CN209692351U (en) * | 2019-04-10 | 2019-11-26 | 湖北亿咖通科技有限公司 | A kind of car networking equipment reverse-connection preventing circuit and vehicle electronic device |
Non-Patent Citations (2)
| Title |
|---|
| 孙立群: "《彩色电视机开关电源维修技术》", 31 July 2004, 高等教育出版社 * |
| 李曼等: "《工程测试技术》", 28 February 2017, 煤炭工业出版社 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112881787A (en) * | 2021-01-13 | 2021-06-01 | 常州同惠电子股份有限公司 | Low-input-impedance high-voltage circuit for voltage test and implementation method |
| CN112881787B (en) * | 2021-01-13 | 2023-03-14 | 常州同惠电子股份有限公司 | Low-input-impedance high-voltage circuit for voltage test and implementation method |
| CN113437736A (en) * | 2021-05-31 | 2021-09-24 | 济南浪潮数据技术有限公司 | Hot plug protection circuit and method |
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Application publication date: 20201117 |