CN111949598B - System-on-chip pin multiplexing self-adaptive synchronous circuit - Google Patents
System-on-chip pin multiplexing self-adaptive synchronous circuit Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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Abstract
The system-on-chip pin multiplexing clock self-adaptive synchronous circuit comprises automatic test equipment and a clock module, wherein the automatic test equipment is connected to a chip MCU to be tested through a single bus, an edge picking circuit and a self-adaptive synchronous circuit are arranged in the chip MCU to be tested, and the edge picking circuit is used for receiving a START START pulse transmitted by the automatic test equipment, detecting and determining the pulse width and the baud rate of the pulse and transmitting the pulse to the self-adaptive synchronous circuit; the self-adaptive synchronous circuit receives the pulse width transmitted by the sampling edge circuit and determines the sampling interval of the subsequent bus; the pulse signals acquired by the edge picking circuit are processed by the self-adaptive synchronous circuit and used for assisting the chip MCU to be tested to enter a test mode, the invention avoids the use of an external clock and corresponding PAD pins, can ensure the communication between test equipment or an upper computer and the chip MCU to be tested under the condition of no calibration, and can avoid communication faults caused by clock precision deviation when used for a digital-analog hybrid chip.
Description
Technical field:
the invention relates to the technical field of chip design, in particular to a system-on-chip pin multiplexing self-adaptive synchronous circuit.
The background technology is as follows:
the MCU, also called as a single-chip microcomputer or a single-chip microcomputer, properly reduces the frequency and specification of a CPU, integrates peripheral interfaces such as a memory (memory), a counter (Timer), USB, A/D conversion, UART, PLC, DMA and the like, and even LCD driving circuits on a single chip to form a chip-level computer, and performs different combination control for different application occasions. A Central Processing Unit (CPU) in a microcomputer is called a Microprocessor (MPU), and is a core component constituting the microcomputer, and may be referred to as a heart of the microcomputer. The MPU and MCU are different in application positioning essentially, the MPU focuses on executing complex and diverse large programs through stronger operation/processing capacity, the MCU usually runs a single task, and usually does not need stronger operation/processing capacity, and the current mainstream general MCU/MPU can enter different test modes through a plurality of groups of pin combination input vector modes due to relatively abundant pin resources, as shown in figure 6, such as SCAN scanning inspection, total power supply current in IDDQ static state, BIST built-in self-test technology, analog circuit test, functional test and the like. For a power chip containing MCU core-digital-analog mixture, the pin resources are deficient, different test modes can be gated only through a sequence mode by individual pins, and because the clock circuit of the chip is not calibrated at the moment, communication faults with certain fixed baud rate can occur, so that part of chips are difficult to enter corresponding test modes, and stable clocks are required to be provided through an additional clock or an additional power supply mode. Resulting in increased test costs. There is a need for a system-on-chip pin multiplexing adaptive synchronization circuit that addresses the above-described issues.
The invention comprises the following steps:
the invention aims to provide a system-on-chip pin multiplexing self-adaptive synchronous circuit to solve the problems in the prior art.
In order to achieve the above purpose, the invention provides a system-on-chip pin multiplexing clock self-adaptive synchronous circuit, which comprises automatic test equipment and a clock module, wherein the automatic test equipment is connected to a chip MCU to be tested through a single bus, and an edge picking circuit and a self-adaptive synchronous circuit are arranged in the chip MCU to be tested;
the edge picking circuit is used for receiving a START pulse transmitted by the automatic test equipment, detecting and determining the pulse width and the baud rate of the pulse, and transmitting the pulse to the self-adaptive synchronous circuit;
the self-adaptive synchronous circuit receives the pulse width transmitted by the sampling edge circuit and determines the sampling interval of the subsequent bus;
the pulse signals acquired by the edge acquisition circuit are processed by the self-adaptive synchronous circuit and used for assisting the chip MCU to be tested to enter a test mode, the edge acquisition circuit transmits the pulse signals to the self-adaptive synchronous circuit after acquiring and determining the pulse width and the baud rate of the pulse, and the self-adaptive synchronous circuit sets sampling points again so as to assist the chip MCU to be tested to enter and exit the corresponding test mode.
As a further improvement of the technical scheme, the edge picking circuit comprises an edge picking circuit and a lower edge picking circuit, and the edge picking circuit and the lower edge picking circuit are used for carrying out edge picking on the pulse. The edge acquisition can accurately judge the START pulse window position, and provides a reference for the following baud rate determination and acquisition point position location.
As a further improvement of the above technical solution, the adaptive synchronization circuit is connected to a sampling number register, and the register can adjust the setting sampling number.
The self-adaptive synchronous circuit is internally provided with a counting unit which is used for receiving pulse signals acquired by the edge acquisition circuit and processing the signals;
the counting unit is connected with a judging unit for judging which test mode the pulse signal enters.
As a further improvement of the above technical solution, the rising edge circuit includes a first flip-flop D and a second flip-flop, the first flip-flop D is terminated with a single bus signal, the first flip-flop CP is terminated with a clock module signal, the first flip-flop Q is connected to the second flip-flop D and a first and gate, the second flip-flop CP is terminated with a clock module signal, the second flip-flop Q is terminated with a first not gate, and the first not gate is connected to the first and gate.
As a further improvement of the above technical solution, the trailing edge circuit includes a third flip-flop D and a fourth flip-flop, the third flip-flop D is terminated with a single bus signal, the third flip-flop CP is terminated with a clock module signal, the third flip-flop Q is connected to the fourth flip-flop D and to a second and gate, the fourth flip-flop CP is terminated with a clock module signal, the fourth flip-flop Q is terminated with a second not gate, and the second not gate is connected to the second and gate.
As a further improvement of the above technical solution, the adaptive synchronization circuit is provided with a fifth flip-flop, the fifth flip-flop is connected with a sixth flip-flop, a seventh flip-flop and an eighth flip-flop in series, the single bus signal is connected to the D end of the fifth flip-flop, the clock module signal is connected to the CP ends of the fifth flip-flop, the sixth flip-flop and the eighth flip-flop, the first and second and gates are connected to the adaptive synchronization circuit, and the rising edge circuit and the falling edge circuit are connected to the adaptive synchronization circuit through the first and second and gates, so that pulse width and baud rate data can be transmitted to the adaptive synchronization circuit.
A system-on-chip pin multiplexing clock self-adaptive synchronous circuit, entering a test mode comprises the following steps:
s1: the automatic test equipment is connected with a power supply, and a START pulse is sent to a circuit to be tested, wherein the pulse range is 100-500 us;
s2: detecting the pulse by adopting an edge circuit, counting and storing the pulse by a counting unit 13 of the self-adaptive synchronous circuit, and determining the pulse width and the baud rate of the pulse;
s3: the automatic test equipment continues to send a START pulse to the circuit to be tested, and the edge picking circuit acquires bus data on a single bus through the baud rate established by the first pulse;
s4: the self-adaptive synchronous circuit determines the sampling interval of a subsequent bus through the acquired pulse width, and each pulse width range generates 1-3 sampling points;
s5: when the bit value of the step S3 is 1 or 0 after 2 times of sampling, judging that the bit is a corresponding value of the test mode, entering the step S6, otherwise, re-executing the step S3;
s6: and entering a test mode.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention avoids the use of an external clock and a corresponding PAD pin, and can ensure that test equipment or an upper computer communicates with a chip MCU to be tested in a serial mode even under the condition of no calibration, the baud rate dynamically follows the upper computer, the test establishment and switching time is reduced, and the time sequence of the upper computer is prevented from being manually adjusted;
2. when the method is applied to the digital-analog hybrid chip, the test communication fault caused by the deviation of clock precision can be avoided, and by adopting the method, a large amount of debugging work of an upper computer or a testing machine can be avoided, the online on-line test is realized, the efficiency is improved, and the test cost is reduced.
Description of the drawings:
FIG. 1 is a schematic diagram of the connection of a sampling edge circuit and an adaptive synchronous circuit;
FIG. 2 is a schematic diagram of a START pulse transmission and processing structure;
FIG. 3 is a block diagram of a connection test structure of an automatic test device and a chip MCU to be tested;
FIG. 4 is a sequence chart of a START pulse corresponding to a clock pulse SCLK;
FIG. 5 is a flow chart of a chip under test entering a test mode;
fig. 6 is a schematic diagram of the corresponding function of the chip to be tested.
In the figure: 1. a first trigger; 2. a second trigger; 3. a third trigger; 4. a fourth trigger; 5. a fifth trigger; 6. a sixth trigger; 7. a seventh flip-flop; 8. an eighth flip-flop; 9. a first NOT gate; 10. a second NOT gate; 11. a first AND gate; 12. a second AND gate 13, a counting unit; 14. and a judging unit.
The specific embodiment is as follows:
in order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below. The specific conditions are not noted in the examples and are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
Examples: as shown in fig. 3, a system-on-chip pin multiplexing clock self-adaptive synchronous circuit comprises automatic test equipment and a clock module, wherein the automatic test equipment is connected to a chip to be tested MCU through a single bus, and an edge picking circuit and the self-adaptive synchronous circuit are arranged in the chip to be tested MCU;
as shown in fig. 2, the edge picking circuit is used for receiving a START pulse transmitted by the automatic test equipment, detecting and determining the pulse width and the baud rate of the pulse, and transmitting the pulse to the adaptive synchronous circuit; the self-adaptive synchronous circuit receives the pulse width transmitted by the sampling edge circuit and determines the sampling interval of the subsequent bus; the pulse signals acquired by the edge acquisition circuit are processed by the self-adaptive synchronous circuit and used for assisting the chip MCU to be tested to enter a test mode, and the pulse width and the baud rate of the pulses acquired by the edge acquisition circuit are transmitted to the self-adaptive synchronous circuit.
The edge picking circuit comprises an edge picking circuit and a lower edge picking circuit, and the edge picking circuit and the lower edge picking circuit are used for carrying out sectional acquisition on the pulse.
The self-adaptive synchronous circuit is connected to a sampling frequency register, and the frequency preset value of the sampling frequency register can be adjusted by means of automatic test equipment and an MCU chip.
The self-adaptive synchronous circuit is provided with a counting unit 13 which is used for receiving pulse signals acquired by the edge acquisition circuit and processing the signals, the counting unit is connected with a judging unit 14 which is used for judging a test mode of the pulse signals, the counting unit 13 takes the edge pulse signals acquired by the edge acquisition circuit as the START and end signals of the technology, and establishes the window time of START pulse of the START and the subsequent positioning reference calculation of the sequence sampling points.
As shown in fig. 1, the rising edge circuit includes a first flip-flop 1 and a second flip-flop 2, the first flip-flop 1D is terminated with a single bus signal, the first flip-flop 1CP is terminated with a clock module signal, the first flip-flop 1Q terminal is connected to the second flip-flop 2D terminal and the first and gate 11, the second flip-flop 2CP is terminated with the clock module signal, the second flip-flop 2Q is terminated with the first not gate 9, and the first not gate 9 is connected to the first and gate 11.
The sampling edge circuit comprises a third trigger 3 and a fourth trigger 4, wherein the third trigger 3D is connected with a single bus signal, the third trigger 3CP is connected with a clock module signal, the end of the third trigger 3Q is connected with the end of the fourth trigger 4D and a second AND gate 12, the fourth trigger 4CP is connected with the clock module signal, the fourth trigger 4Q is connected with a second NOT gate 10, and the second NOT gate 10 is connected with the second AND gate 12.
The self-adaptive synchronous circuit is provided with a fifth trigger 5, the fifth trigger 5 is connected with a sixth trigger 6, a seventh trigger 7 and an eighth trigger 8 in series, a single bus signal is connected to the end of the fifth trigger 5D, a clock module signal is connected to the ends of the fifth trigger 5, the sixth trigger 6 and the eighth trigger 8CP, a first AND gate 11 and a second AND gate 12 are connected to the self-adaptive synchronous circuit, and after the self-adaptive synchronous circuit receives collected pulse width and baud rate data through the output ends of the first AND gate 11 and the second AND gate 12, sampling points are adjusted and selected.
As shown in fig. 5, entering the test mode includes the steps of:
s1: the automatic test equipment is connected with a power supply, and a START pulse is sent to a circuit to be tested, wherein the pulse range is 100-500 us;
s2: detecting the pulse by adopting an edge circuit, counting and storing the pulse by a counting unit 13 of the self-adaptive synchronous circuit, and determining the pulse width and the baud rate of the pulse;
s3: the self-adaptive synchronous circuit determines the sampling interval of a subsequent bus through the acquired pulse width, and each pulse width range generates 1-3 sampling points;
s4: the automatic test equipment continues to send a START pulse to the circuit to be tested, and the chip MCU to be tested collects bus data on a single bus through the baud rate established by the first pulse;
s5: when the bit value of the step S3 is 1 or 0 after 2 times of sampling, judging that the bit is a corresponding value of the test mode, entering the step S6, otherwise, re-executing the step S3; the purpose of sampling 1-3 times is to reduce glitch, and when the criterion of sampling 2 times or more for 3 times is 1 or 0, the bit is judged to be the corresponding value of the test mode. The sampling points can be added according to the actual working conditions or a hamming distance judging mode can be used;
s6: and entering a test mode.
As shown in fig. 4, when the automatic test equipment sends START pulses to the chip MCU to be tested, in the START pulse SEQ timing diagram, CHKP is a check point, point a is a sampling point of the sampling edge circuit, point b is a sampling point of the sampling edge circuit, after the collected narrow pulse signals of the rising edge of the RISE and the falling edge of the FALL of the RISE are transmitted to the self-adaptive synchronous circuit, the counting unit 13 in the self-adaptive synchronous circuit establishes how many SCLK clock signal pulses the START pulses occupy, for example, the number of the START pulses is 4 corresponding to SCLK clock signal pulses in section a-b in the diagram, in practice, the START pulse signals in the machine test are very wide, according to the different pulse frequencies of the SCLK clock signal pulses, the count of the SCLK clock signal pulses can reach several tens to hundreds, so that the 4 SCLK clock signal pulses in the diagram are only intuitively illustrated, the counting unit 13 in the self-adaptive synchronous circuit calculates the sampling position of SAMP through the number of the SCLK clock signal pulses, the sampling edge circuit again acquires START pulse signals, the sampling times is adjusted according to the preset value of the SAMP register, and the number of sampling times can be adjusted according to the preset value of the self-adaptive synchronous circuit, and the sampling sequence can be matched with the corresponding value of the sampling units 14, and the data can be judged when the corresponding to the data sequence is completely matched with the corresponding to the sampling sequence, and the data is sampled by the corresponding to the data sequence, and the data in the test sequence can be judged when the corresponding to the data sequence is sampled by the corresponding to the sampling unit 14.
In summary, the invention avoids the use of an external clock and a corresponding PAD pin, and can ensure that the test equipment or the upper computer communicates with the chip MCU to be tested in a serial mode even under the condition of no calibration, the baud rate dynamically follows the upper computer, the test establishment and switching time is reduced, and the manual adjustment of the upper computer time sequence is avoided.
In addition, when the invention is applied to a digital-analog hybrid chip, the test communication fault caused by the deviation of clock precision can be avoided, and by adopting the method, a large amount of debugging work of an upper computer or a testing machine can be avoided, the online just-tested is realized, the efficiency is improved, and the test cost is reduced.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (3)
1. The system-on-chip pin multiplexing clock self-adaptive synchronous circuit comprises automatic test equipment and a clock module, wherein the automatic test equipment is connected to a chip MCU to be tested through a single bus;
the edge picking circuit is used for receiving a START pulse transmitted by the automatic test equipment, detecting and determining the pulse width and the baud rate of the pulse, and transmitting the pulse to the self-adaptive synchronous circuit;
the self-adaptive synchronous circuit receives the pulse width transmitted by the sampling edge circuit and determines the sampling interval of the subsequent bus;
the pulse signals acquired by the edge acquisition circuit are processed by the self-adaptive synchronous circuit and used for assisting the chip MCU to be tested to enter a test mode;
the edge picking circuit comprises an edge picking circuit and a lower edge picking circuit and is used for carrying out sectional acquisition on the pulse; the sampling up edge circuit comprises a first trigger (1) and a second trigger (2), wherein a D end of the first trigger (1) is connected with a single bus signal, a CP end of the first trigger (1) is connected with a clock module signal, a Q end of the first trigger (1) is connected with a D end of the second trigger (2) and a first AND gate (11), a CP end of the second trigger (2) is connected with the clock module signal, a Q end of the second trigger (2) is connected with a first NOT gate (9), and the first NOT gate (9) is connected with the first AND gate (11); the sampling edge circuit comprises a third trigger (3) and a fourth trigger (4), wherein the third trigger (3) D is connected with a single bus signal, the third trigger (3) CP is connected with a clock module signal, the Q end of the third trigger (3) is connected with the D end of the fourth trigger (4) and a second AND gate (12), the CP of the fourth trigger (4) is connected with the clock module signal, the Q end of the fourth trigger (4) is connected with a second NOT gate (10), and the second NOT gate (10) is connected with the second AND gate (12);
the self-adaptive synchronous circuit is internally provided with a counting unit (13) which is used for receiving pulse signals acquired by the edge acquisition circuit and processing the signals; the counting unit (13) is connected with a judging unit (14) for judging which test mode the pulse signal enters; the self-adaptive synchronous circuit is provided with a fifth trigger (5), the fifth trigger (5) is connected with a sixth trigger (6), a seventh trigger (7) and an eighth trigger (8) in series, the single bus signal is connected to the D end of the fifth trigger (5), the clock module signal is connected to the CP ends of the fifth trigger (5), the sixth trigger (6) and the eighth trigger (8), and the first AND gate (11) and the second AND gate (12) are connected to a counting unit (13) in the self-adaptive synchronous circuit.
2. The system-on-chip pin multiplexing clock adaptive synchronization circuit of claim 1, wherein the adaptive synchronization circuit is coupled to a sample times register.
3. The system-on-chip pin multiplexing clock adaptive synchronization circuit of claim 1, wherein entering the test mode comprises the steps of:
s1: the automatic test equipment is connected with a power supply, and a START pulse is sent to a circuit to be tested, wherein the pulse range is 100-500 us;
s2: detecting the pulse by adopting an edge circuit, counting and storing the pulse by a counting unit 13 of the self-adaptive synchronous circuit, and determining the pulse width and the baud rate of the pulse;
s3: the automatic test equipment continues to send a START pulse to the circuit to be tested, and the edge picking circuit acquires bus data on a single bus through the baud rate established by the first pulse;
s4: the self-adaptive synchronous circuit determines the sampling interval of a subsequent bus through the acquired pulse width, and each pulse width range generates 1-3 sampling points;
s5: when the bit value of the step S3 is 1 or 0 after 2 times of sampling, judging that the bit is a corresponding value of the test mode, entering the step S6, otherwise, re-executing the step S3;
s6: and entering a test mode.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6661266B1 (en) * | 2000-11-08 | 2003-12-09 | Texas Instruments Incorporated | All digital built-in self-test circuit for phase-locked loops |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| CN106443184A (en) * | 2016-11-23 | 2017-02-22 | 优利德科技(中国)有限公司 | Phase detection device and phase detection method |
| CN106528478A (en) * | 2016-12-06 | 2017-03-22 | 天津北芯微科技有限公司 | Single-bus asynchronous serial port communication system and communication method thereof |
| CN109412582A (en) * | 2018-12-10 | 2019-03-01 | 珠海市微半导体有限公司 | A kind of pwm signal sample detecting circuit, processing circuit and chip |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6661266B1 (en) * | 2000-11-08 | 2003-12-09 | Texas Instruments Incorporated | All digital built-in self-test circuit for phase-locked loops |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| CN106443184A (en) * | 2016-11-23 | 2017-02-22 | 优利德科技(中国)有限公司 | Phase detection device and phase detection method |
| CN106528478A (en) * | 2016-12-06 | 2017-03-22 | 天津北芯微科技有限公司 | Single-bus asynchronous serial port communication system and communication method thereof |
| CN109412582A (en) * | 2018-12-10 | 2019-03-01 | 珠海市微半导体有限公司 | A kind of pwm signal sample detecting circuit, processing circuit and chip |
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