CN111936949A

CN111936949A - Driving circuit and related chip

Info

Publication number: CN111936949A
Application number: CN202080001681.7A
Authority: CN
Inventors: 李宗隆; 范铨奇; 徐建昌
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2020-03-25
Filing date: 2020-03-25
Publication date: 2020-11-13
Also published as: WO2021189282A1

Abstract

The application discloses a driving circuit (200) and a related chip. The driving circuit comprises a logic circuit (110), a push-pull circuit (120) and a control circuit (210), wherein the logic circuit is used for generating a data signal; the push-pull circuit includes: a first transistor (M1) for, when the data signal transitions from a first logic state to a second logic state, transitioning the potential of the output terminal of the driving circuit from a first potential corresponding to the first logic state to a second potential corresponding to the second logic state during the first transition; the control circuit is coupled to the push-pull circuit and used for controlling the current flowing through the first transistor to be a first constant current (ics1) before the potential of the output end reaches the second potential during the first transition state.

Description

Driving circuit and related chip

Technical Field

The present disclosure relates to circuits, and particularly to a driving circuit and a related chip.

Background

An interface of an integrated circuit generally needs to comply with some design specifications of an electronic component, for example, a general-purpose input/output (i/o) interface needs to comply with an electromagnetic interference (EMI) design specification. Therefore, an innovative design is needed to reduce EMI of existing interfaces.

Disclosure of Invention

An objective of the present application is to disclose a circuit, and more particularly, to a driving circuit and a related chip to solve the above problems.

An embodiment of the present application discloses a driving circuit: the circuit comprises a logic circuit, a push-pull circuit and a control circuit, wherein the logic circuit is used for generating a data signal; the push-pull circuit includes: a first transistor for switching a potential of an output terminal of the driving circuit from a first potential corresponding to a first logic state to a second potential corresponding to a second logic state during a first transition when the data signal transitions from the first logic state to the second logic state; the control circuit is coupled to the push-pull circuit and used for controlling the current flowing through the first transistor to be a first constant current before the potential of the output end reaches the second potential during the first transition state.

An embodiment of the present application discloses a chip, including the foregoing driving circuit.

The driving circuit disclosed by the application can control the current flowing through the conductive pull-up transistor or the conductive pull-down transistor to be constant current. Accordingly, the slew rate of the pull-up transistor and the pull-down transistor can be controlled during each conduction period to improve the EMI problem.

Drawings

The circuit diagram of fig. 1A illustrates the charging operation of the drive circuit.

The voltage waveform diagram of fig. 1B illustrates the voltage versus time variation of the output of the driver circuit under the charging operation of the equivalent capacitor.

The circuit diagram of fig. 1C illustrates the discharge operation of the drive circuit.

The voltage waveform diagram of fig. 1D illustrates the voltage versus time variation of the output of the driver circuit under discharge operation to the equivalent capacitor.

The circuit diagram of fig. 2A illustrates the charging operation of the drive circuit of the present application.

The voltage waveform diagram of fig. 2B illustrates the voltage versus time variation of the output of the driver circuit of fig. 2A under the charging operation of the equivalent capacitor.

The circuit diagram of fig. 2C illustrates the discharging operation of the driving circuit of the present application.

The voltage waveform diagram of fig. 2D illustrates the voltage versus time variation of the output of the driver circuit of fig. 2C under discharge operation to the equivalent capacitor.

Fig. 3 is a circuit diagram of yet another embodiment of a driving circuit of the present application.

Fig. 4 is a circuit diagram of still another embodiment of a driving circuit of the present application.

Fig. 5 is a circuit diagram of a further embodiment of the driving circuit of the present application.

Detailed Description

The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "the same" generally means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "the same" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are "the same" unless otherwise specifically indicated or indicated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.

Generally, an input/output interface, such as a general-purpose input/output (GPIO) interface, is generally formed by transistors. When the input/output interface is operated, the equivalent capacitor seen from the output end of the input/output interface is charged or discharged through the transistor, so that the input/output interface outputs high potential or low potential. For example, the circuit diagrams of fig. 1A and 1C illustrate the charging operation and the discharging operation of the driving circuit 100, respectively.

Referring to fig. 1A, the driving circuit 100 includes a logic circuit 110 and a push-pull circuit 120. The push-pull circuit 120 includes a P-type transistor M1 and an N-type transistor M2 connected in series between the specific voltages VDD and VSS. Specifically, the source and the drain of the transistor M1 are coupled to the specific voltage VDD and the drain of the transistor M2, respectively, and the source of the transistor M2 is coupled to the specific voltage VSS. In some embodiments, the specific voltages VDD and VSS are the same magnitude and opposite polarity. In some embodiments, the specific voltage VSS is a reference ground.

The logic circuit 110 is coupled to the transistors M1 and M2, and configured to turn on only one of the transistors M1 and M2 at any time (i.e., the transistors M1 and M2 are not turned on at the same time) according to the enable signal EN and the data signal D. For example, the logic circuit 110 includes a not gate 112, a nand gate 114, and a nor gate 116. The data signal D is transmitted to the gates of the transistors M1 and M2 via the nand gate 114 and the nor gate 116, respectively. In detail, the nand gate 114 inverts the logic state of the received data signal D based on the enable signal EN of logic 1, and outputs the inverted data signal D to the gate of the transistor M1. Based on the enable signal EN of logic 1, the nor gate 116 inverts the logic state of the received data signal D and outputs the inverted data signal D to the gate of the transistor M2.

The drains of the transistors M1 and M2 form the output terminal OUT, and in fig. 1A, the transistor M2 is not conductive and the transistor M1 is conductive, and the transistor M1 charges the equivalent capacitor CL seen by the output terminal OUT with a specific voltage VDD to transition the potential of the output terminal OUT from the first potential (about VSS, corresponding to logic 0) to the second potential (about VDD, corresponding to logic 1) during the rising transition. The rising transition period is a period in which the potential continues to rise, and does not include a period in which the potential reaches the second potential, is maintained at the second potential, and does not continue to rise again. In fig. 1C, when the transistor M1 is turned off and the transistor M2 is turned on, the transistor M2 discharges the equivalent capacitor CL with a specific voltage VSS to change the potential of the output terminal OUT from the second potential (about VDD) to the first potential (about VSS) during the falling transition. The falling transition period is a period in which the potential is continuously falling, and does not include a period in which the potential reaches the first potential, is maintained at the first potential, and does not continue to fall any more.

The voltage waveform diagrams of fig. 1B and 1D illustrate the voltage versus time variation of the output terminal OUT of the driver circuit 100 in the charging operation and the discharging operation of the equivalent capacitor CL, respectively. In fig. 1B and 1D, the voltage on the vertical axis represents the potential of the output terminal OUT of the drive circuit 100, and the horizontal axis represents time. Referring to fig. 1B, observing the curve change of the waveform 130, the potential of the output terminal OUT quickly climbs to Vr with a steep slope in the initial charging period (period dTr), which causes the drain-source voltage of the transistor M1 to change greatly for a short time, i.e., the slew rate (slew rate) is too large; similarly, when the waveform 135 shown in fig. 1D is observed to change, the voltage level at the output terminal OUT decreases rapidly to Vf with a steep slope in the early stage of discharge (period dTf), which also causes the slew rate of the transistor M2 to be too high. Since the larger the slew rate, the larger the EMI, subsequent embodiments will ameliorate the EMI problem by controlling the slew rate of transistors M1 and M2 of the push-pull circuit 120.

< example one >

The circuit diagrams of fig. 2A and 2C illustrate the charging operation and the discharging operation of the driving circuit 200, respectively. Referring to fig. 2A, the driving circuit 200 is similar to the driving circuit 100 of fig. 1A, except that the driving circuit 200 further includes a control circuit 210, and the control circuit 210 is coupled to the push-pull circuit 120. In the present embodiment, the control circuit 210 includes a current source Ir and a current sink Ik.

The current source Ir receives a specific voltage VDD and is coupled to the source of the transistor M1. In fig. 2A, the transistor M2 is not turned on and the transistor M1 is turned on, and the current source Ir is used to continuously provide a constant current ics1 to the output terminal OUT via the transistor M1 to charge the equivalent capacitor CL during the on period of the transistor M1. In short, the current source Ir controls the current flowing through the transistor M1 to be a constant current ics 1. In the present embodiment, the constant current means that the magnitude of the current does not change with time.

In some embodiments, the current source Ir can be implemented as a single P-type transistor, wherein the source of the P-type transistor receives the specific voltage VDD, the gate is controlled by the control voltage, and the drain is coupled to the source of the transistor M1.

The current sink Ik receives a specific voltage VSS and is coupled to the source of the transistor M2. In fig. 2C, the transistor M1 is not conducting and the transistor M2 is conducting, and the current sink Ik is used to continuously draw a constant current ics2 from the output terminal OUT via the transistor M2 to discharge the equivalent capacitor CL during the conduction period of the transistor M2. In short, the current sink Ik controls the current flowing through the transistor M2 to be a constant current ics 2.

In some embodiments, the current sink Ik can be implemented as a single N-type transistor, wherein the source of the N-type transistor receives a specific voltage VSS, the gate is controlled by another control voltage, and the drain is coupled to the source of the transistor M2.

The voltage waveform diagrams of fig. 2B and 2D illustrate the voltage-to-time variation of the output terminal OUT of the driving circuit 200 in the charging operation and the discharging operation of the equivalent capacitor CL, respectively. In fig. 2B and 2D, the voltage on the vertical axis represents the potential of the output terminal OUT of the drive circuit 200, and the horizontal axis represents time.

For comparison, in fig. 2B, the waveform 130 of fig. 1B is shown. Comparing the

waveforms

230 and 130, it can be observed that the potential of the output terminal OUT indicated by the waveform 230 climbs to Vr with a relatively small and substantially fixed slope in the initial charging period (period dTr) compared to the waveform 130 of fig. 1B. This means that, in the initial stage of charging, the transistor M1 of fig. 2A is smaller in the slew rate of the drain-source voltage than the transistor M1 of fig. 1A.

Similarly, for comparison, in fig. 2D, the waveform 135 of fig. 1D is shown. Comparing the

waveforms

235 and 135, it can be observed that the voltage level at the output terminal OUT indicated by the waveform 235 is reduced to Vr with a relatively small and substantially constant slope in the initial discharge period (period dTf) compared to the waveform C135 in fig. 1D. This means that, in the initial stage of discharge, the transistor M2 of fig. 2C is smaller in the slew rate of the drain-source voltage than the transistor M2 of fig. 1C.

Since the slew rate of each of the transistors M1 and M2 can be controlled, the EMI problem at the initial stage of discharge and the initial stage of charge can be improved, and the EMI can be made to meet the specification.

< example two >

Fig. 3 is a circuit diagram of an embodiment of a driving circuit 300 of the present application. Referring to fig. 3, the driving circuit 300 is similar to the driving circuit 200 of fig. 2A, with the difference that the control circuit 310 of the driving circuit 300 further includes: a reference current source Iref and transistors M3, M4, M5, M6, and M7.

Transistors M3 and M4 form a current mirror. Since this current mirror receives a constant current Iref (which may be referred to as a reference constant current where appropriate) from a reference current source Iref, this current mirror may be referred to as a source current mirror where appropriate, and transistors M3 and M4 may be referred to as reference transistors where appropriate. In detail, the gate of the transistor M3 is short-circuited to the drain, and is short-circuited to the gate of the transistor M4. The source current mirror copies the constant current iref received by transistor M3 and outputs a constant current icof (which may be referred to as a copied constant current where appropriate) through transistor M4. In addition to the source current mirror, the driver circuit 300 includes other current mirrors, as described in detail below.

Transistor M3 also forms a current mirror with transistor M7, which may be referred to as a first current mirror where appropriate. In detail, the gate of the transistor M3 is further short-circuited to the gate of the transistor M7. The first current mirror copies the constant current iref received by transistor M3 and outputs a constant current ic1 through transistor M7. Since transistor M7 provides the function of a current sink, it may also be referred to as a current sink transistor where appropriate.

Transistors M5 and M6 form a current mirror, which may be referred to as a second current mirror where appropriate. In detail, the gate of the transistor M5 is short-circuited to the drain, and is short-circuited to the gate of the transistor M6. The second current mirror copies the constant current icof received by transistor M5 and outputs a constant current ic2 through transistor M6. Since transistor M6 provides the function of a current source, it may also be referred to as a current source transistor where appropriate.

In the charging operation, since the transistors M1 and M6 are connected in series, the transistor M6 continuously provides the constant current ic2 to the output terminal OUT via the transistor M1 when the transistor M1 is turned on.

In the discharging operation, since the transistors M2 and M7 are connected in series, the transistor M7 continuously draws a constant current ic1 from the output terminal OUT through the transistor M2 when the transistor M2 is turned on.

For the same reason as described in the first embodiment, since the slew rates of the transistors M1 and M2 can be controlled, the driving circuit 300 of the present application can improve the EMI problem in the initial discharge stage and the initial charge stage, and make the EMI meet the specification.

< example three >

Fig. 4 is a circuit diagram of an embodiment of a driving circuit 400 of the present application. Referring to fig. 4, a driving circuit 400 is similar to the driving circuit 300 of fig. 3, with the difference that the control circuit 410 of the driving circuit 400 further includes, compared to the control circuit 310 of fig. 3: the connection modes of the transistors M8, M9 and M10, and the transistors M3 and M5 are different from the connection modes of the transistors M3 and M5 of the control circuit 310. In the present embodiment, the transistors M8, M9, and M10 can be used as resistors, which are described in detail below.

The circuit operator can change the current gear of the reference current source Iref as required to adjust the magnitude of the constant current Iref, so that the charging and discharging time of the parasitic capacitor CL can meet the specification requirement. In order to accurately adjust the charging/discharging time of the parasitic capacitor CL, it is necessary to accurately adjust the magnitudes of the constant currents ic1 and ic 2.

In order to achieve the above object, it is possible to make the amounts of change of the constant currents iref and ic1 as equal as possible and to make the amounts of change of the constant currents iref and ic2 as equal as possible. Incidentally, since the constant current ic2 is directly copied from the constant current icof and is indirectly copied from the constant current iref, the amounts of change among the constant currents iref, icof, and ic2 are also made equal.

One possible way to achieve this is to (1) make the equivalent circuits through which constant currents iref and ic1 flow as equal as possible; and (2) equivalent circuits through which constant currents iref, icof, and ic2 flow are as equal as possible.

With respect to the above (1), the equivalent circuit through which the constant current ic1 flows is constituted by the transistors M2 and M7 connected in series, and the transistor M2 receives a voltage equivalent to the specific voltage VDD. Accordingly, the transistor M8 is added, and the transistors M8 and M3 are connected in series. In order to make the transistor M8 follow the behavior of the transistor M2 when turned on, the gate of the transistor M8 receives the specific voltage VDD. In this way, the equivalent circuits through which the constant currents ic1 and iref flow are as equal as possible.

With regard to the above (2), the equivalent circuit through which the constant current ic2 flows is constituted by the transistors M1 and M6 connected in series, and the transistor M1 receives a voltage equivalent to the specific voltage VSS. Accordingly, the transistor M10 is added, and the transistors M10 and M5 are connected in series. In order to make the transistor M10 follow the behavior of the transistor M1 when turned on, the gate of the transistor M10 receives the specific voltage VSS. In this way, the equivalent circuits through which the constant currents ic2 and icof flow are as equal as possible. In addition, an equivalent circuit through which the constant current iref flows is constituted by transistors M3 and M8 connected in series, and the transistor M8 receives the specific voltage VDD. Accordingly, the transistor M9 is added, and the transistors M9 and M4 are connected in series. In order to make the transistor M9 follow the behavior of the transistor M8 when turned on, the gate of the transistor M9 also receives the specific voltage VDD. In this way, the equivalent circuits through which the constant currents icof and iref flow are as equal as possible to each other. In summary, equivalent circuits through which constant currents iref, icof, and ic2 flow are as equal as possible.

In addition to from the viewpoint of the equivalent circuit, it may also be from the viewpoint of the equivalent impedance. In short, the resistance value of the drain of the transistor M3 is as same as the resistance value of the drain of the transistor M7. Therefore, the transistor M8 is added in series with the transistor M3 stack. Accordingly, the transistor M8 may be referred to as a stacked transistor where appropriate. Further, the resistance value with respect to the drain of the transistor M3 relates to the on-resistance of the transistor M8, and the resistance value with respect to the drain of the transistor M7 relates to the on-resistance of the transistor M2. That is, the transistor M8 may be used as a resistor.

Similarly, the impedance value of the drain of the transistor M5 is made as same as the impedance value of the drain of the transistor M6. Therefore, transistor M10 is added in series with the stack of transistor M5. Accordingly, the transistor M10 may be referred to as a stacked transistor where appropriate. Further, the resistance value with respect to the drain of the transistor M5 relates to the on-resistance of the transistor M10, and the resistance value with respect to the drain of the transistor M6 relates to the on-resistance of the transistor M1. That is, the transistor M10 may be used as a resistor.

In addition, the impedance value of the drain of the transistor M4 is made as same as the impedance value of the drain of the transistor M3 as possible. Therefore, transistor M9 is added in series with the stack of transistor M4. Accordingly, the transistor M9 may be referred to as a stacked transistor where appropriate. Further, the resistance value with respect to the drain of the transistor M4 relates to the on-resistance of the transistor M9, and the resistance value with respect to the drain of the transistor M3 relates to the on-resistance of the transistor M8. That is, the transistor M9 may be used as a resistor.

As described above, the driving circuit 400 of the present application can not only improve the EMI problem in the initial discharge stage and the initial charge stage, but also accurately adjust the magnitudes of the constant currents ic1 and ic 2.

< example four >

Fig. 5 is a circuit diagram of an embodiment of a driving circuit 500 of the present application. Referring to fig. 5, the driving circuit 500 is similar to the driving circuit 400 of fig. 4, and the main difference is that the transistor M1 of the push-pull circuit 120 and the transistor M6 of the control circuit 510 are stacked in a manner opposite to the stacking manner of fig. 4 in the up-down direction, and the transistor M2 of the push-pull circuit 120 and the transistor M7 of the control circuit 510 are stacked in a manner opposite to the stacking manner of fig. 4 in the up-down direction.

In detail, the transistor M1 becomes stacked above the transistor M6, i.e., the transistor M1 is coupled between the source of the transistor M6 and the specific voltage VDD. The transistor M2 becomes stacked under the transistor M7, i.e., coupled between the source of the transistor M7 and the specific voltage VSS.

In order to accurately adjust the magnitudes of the constant currents ic1 and ic2, the transistor M10 becomes stacked above the transistor M5 coupled between the source of the transistor M5 and the specific voltage VDD in response to the stack variation of the transistors M1 and M6 for the same reason as in the embodiment of fig. 4. In order to make the transistor M10 follow the behavior of the transistor M1 when turned on, the gate of the transistor M10 receives the specific voltage VSS. Further, in order to form a current mirror, the drain and the gate of the transistor M5 are short-circuited to each other, and the drain of the transistor M5 is also short-circuited to the gate of the transistor M6. Collectively, transistors M5, M6, and M10 form the aforementioned second current mirror.

Similarly, in response to the stack variation of the transistors M2 and M7, the transistor M3 becomes stacked above the transistor M8, coupled between the reference current source Iref and the drain of the transistor M8. In order to make the transistor M8 follow the behavior of the transistor M2 when turned on, the gate of the transistor M8 receives the specific voltage VDD. To form a current mirror, the drain and gate of the transistor M3 are short-circuited to each other, and the drain of the transistor M3 is also short-circuited to the gate of the transistor M7. Collectively, transistors M3, M7, and M8 form the first current mirror described above.

Similarly, in response to the stack change of the transistors M3 and M8, the transistor M4 becomes stacked above the transistor M9, coupled between the drain of the transistor M9 and the drain of the transistor M5. In order to make the transistor M9 follow the behavior of the transistor M8 when turned on, the gate of the transistor M9 receives the specific voltage VDD. To form a current mirror, the gate of transistor M4 is coupled to the gate of transistor M3. Collectively, transistors M3, M4, M8, and M9 form the aforementioned source current mirror.

As described above, the driving circuit 500 of the present application can not only improve the EMI problem in the initial discharge stage and the initial charge stage, but also accurately adjust the magnitudes of the constant currents ic1 and ic 2.

The present application also provides a chip including the driving

circuit

200, 300, 400 or 500, for example, the chip may be a semiconductor chip implemented by different processes.

The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A drive circuit comprises a logic circuit, a push-pull circuit and a control circuit, wherein

The logic circuit is used for generating a data signal;

the push-pull circuit includes: a first transistor for switching a potential of an output terminal of the driving circuit from a first potential corresponding to a first logic state to a second potential corresponding to a second logic state during a first transition when the data signal transitions from the first logic state to the second logic state;

the control circuit is coupled to the push-pull circuit and used for controlling the current flowing through the first transistor to be a first constant current before the potential of the output end reaches the second potential during the first transition state.

2. The drive circuit of claim 1, wherein the push-pull circuit further comprises:

a second transistor for switching a potential of the output terminal from the second potential to the first potential during a second transition when turned on,

wherein the first transistor and the second transistor are not turned on at the same time.

3. The driving circuit as claimed in claim 2, wherein the control circuit is configured to control the current flowing through the second transistor to be a second constant current during the second transition.

4. The drive circuit of claim 3, wherein the first constant current is the same as the second constant current.

5. The drive circuit of claim 3, wherein the control circuit comprises:

a current source for continuously providing the first constant current to the output terminal via the first transistor during a conduction period of the first transistor.

6. The drive circuit of claim 5, wherein the control circuit further comprises:

a current sink for continuously drawing the second constant current from the output terminal through the second transistor during a turn-on period of the second transistor.

7. The drive circuit of claim 6, wherein the control circuit further comprises:

a source current mirror for receiving a reference constant current and outputting a replica constant current by replicating the reference constant current; and

a second reference transistor coupled to the source current mirror to receive the replica constant current, wherein the second reference transistor and the current source form a second current mirror.

8. The drive circuit of claim 7, wherein the source current mirror comprises: a first reference transistor, wherein the first reference transistor and the current sink form a first current mirror, the first reference transistor receiving the reference constant current, wherein a gate and a drain of the first reference transistor are short-circuited.

9. The driving circuit of claim 8, wherein the gate and drain of the second reference transistor are short-circuited.

10. The drive circuit of claim 7, wherein the source current mirror comprises: a first reference transistor, wherein the first reference transistor and the current sink form a first current mirror, wherein the current sink comprises:

a current sink transistor connected in series with the second transistor and having a gate short-circuited to a gate of the first reference transistor,

wherein the equivalent impedance to the current sink transistor is the same as the equivalent impedance to the first reference transistor.

11. The drive circuit of claim 10, wherein the source current mirror further comprises:

a first stacked transistor connected in series with the first reference transistor,

wherein the equivalent impedance with respect to the first reference transistor is related to the on-resistance of the first stacked transistor.

12. The drive circuit of claim 11, wherein the current source comprises:

a current source transistor connected in series with the first transistor and having a gate short-circuited to a gate of the second reference transistor,

wherein the equivalent impedance with respect to the current source transistor is the same as the equivalent impedance with respect to the second reference transistor.

13. The drive circuit of claim 12, wherein the second current mirror further comprises:

a second stacked transistor connected in series with the second reference transistor,

wherein the equivalent impedance with respect to the second reference transistor is related to the on-resistance of the second stacked transistor.

14. The drive circuit of claim 13, wherein the source current mirror further comprises:

a third reference transistor having a gate short-circuited to the gate of the first reference transistor; and

and the third stacked transistor is connected with the third reference transistor in series, and the grid electrode of the third stacked transistor is in short circuit connection with the grid electrode of the first stacked transistor.

15. The driving circuit as claimed in claim 14, wherein the gate of the first stacked transistor is for receiving a first supply voltage.

16. The driver circuit of claim 15, wherein the gate of the second stacked transistor is to receive a second supply voltage, different from the first supply voltage.

17. The drive circuit of claim 16, wherein the drain of the first stack transistor, the gate of the first reference transistor, and the gate of the current sink transistor are short-circuited to each other.

18. The driving circuit as claimed in claim 17, wherein the drain of the second stacked transistor, the gate of the second reference transistor, and the gate of the current source transistor are short-circuited to each other.

19. The drive circuit of claim 16, wherein the drain and gate of the first reference transistor are shorted with the gate of the current sink transistor.

20. The driving circuit as claimed in claim 19, wherein the drain and gate of the second reference transistor and the gate of the current source transistor are short-circuited to each other.

21. The driving circuit according to claim 2, wherein the first transistor and the second transistor have different polarities, and the digital signals received by the gates of the respective transistors have the same logic state.

22. A chip, wherein the chip comprises:

a driver circuit as claimed in any one of claims 1 to 21.