CN111934537B - Anti-interference method for driving signals of cascade converter - Google Patents
Anti-interference method for driving signals of cascade converter Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Inverter Devices (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention belongs to the technical field of multilevel converter, and discloses an anti-interference method for driving signals of a cascade converter.A Pulse Width Modulation (PWM) driving signal generated by internal carrier modulation is encoded by an Field Programmable Gate Array (FPGA) according to a specific form, a start code and a stop code are added in the encoding, and the signals are continuously transmitted according to a certain baud rate; the CPLD receives the coding signals and decodes the coding signals one by one, and when the received start code, PWM signal coding and stop code are all correct, the PWM driving signal output by the CPLD is updated to the current received logic level; otherwise, the output PWM drive signal level state remains unchanged. The invention avoids the influence of high-frequency electromagnetic interference generated in the switching process of the power device due to the direct long-line transmission of the PWM driving signal, and improves the anti-interference capability of the long-line transmission of the PWM driving signal; meanwhile, PWM narrow pulse signals generated by high-frequency modulation can be automatically filtered, and the switching loss of a high-power switching device is reduced.
Description
Technical Field
The invention belongs to the technical field of multilevel converter, and particularly relates to an anti-interference method for driving signals of a cascade converter.
Background
At present, the multi-level converter has the characteristics of high output level number, good voltage/current harmonic characteristic, small voltage stress of a switching device, small electromagnetic interference, capability of realizing high-voltage output by adopting a low-voltage device and the like, so that the multi-level converter is widely applied to high-power occasions with medium and high voltages.
The cascade multilevel circuit is of a typical multilevel topology, each phase is formed by overlapping a plurality of single-phase full-bridge circuits in series, compared with clamp type and flying capacitor type multilevel circuits, the clamp type and flying capacitor type multilevel circuit has the advantages that complicated capacitor voltage balance is not needed to be considered, a large number of clamp diodes and flying capacitors are omitted, meanwhile, the cascade multilevel circuit has the advantages of being high in equivalent switching frequency, easy to expand in modularization and the like, and therefore the cascade multilevel circuit is widely applied to high-voltage motor driving, photovoltaic new energy grid-connected power generation/battery energy storage systems and static synchronous compensators. When the circuit topology is practically applied, four paths of driving signals are required to be provided for each H bridge arm, and as a plurality of H bridges are arranged in each phase, more PWM driving signals are required for the whole circuit. Therefore, the multi-path PWM driving signal of the cascade multi-level circuit is required to meet the requirement of the multi-path PWM driving signal of the cascade multi-level circuit, and the purposes of modularized control and management of the power unit are achieved.
In real-world conditions where it is difficult for a single digital signal processor (digital signal processor, DSP) to provide multiple drive signals, the multiple PWM drive signals required are typically generated by way of a combination of multiple processors, while achieving modular control and management of the power cells.
Through the above analysis, the problems and defects existing in the prior art are as follows: (1) The prior art multiprocessor combination also results in PWM drive signals that are transmitted over longer lines to act on the target switching device. In the middle-high voltage high-power industrial application occasion, the power device switching process can generate stronger high-frequency electromagnetic interference, so that PWM driving signals transmitted through a long line are easily influenced by the high-frequency electromagnetic interference, abnormal pulses appear in the driving signals, and the abnormal pulses can cause misoperation of the power switch device, further the control effect of the system is poor, even the system cannot work normally, and finally the reliable, safe and stable operation of a power electronic system is threatened.
(2) In the high-voltage high-power application occasion, because the response time of the switching process of the power device is relatively long, the phenomenon that the switching device is turned off immediately after being turned on in a very short time or is turned off immediately after being not turned on completely can occur when the narrow driving pulse acts on the switching device, so that the ratio of the switching process time to the actual on time is very large, the switching loss is obviously increased, and further, the higher requirements are provided for the heat dissipation system of the power electronic device, the heat dissipation mode can be replaced, the natural cooling is changed into forced air cooling, and even the forced air cooling is changed into water cooling to meet the requirements, the higher requirements are provided for the whole heat dissipation system, and the system structure is more complex.
The meaning of solving the problems and defects is as follows: abnormal pulses caused by high-frequency electromagnetic interference are eliminated, so that the power electronic system can be ensured to run more reliably, safely and stably; narrow pulses in the PWM signals are automatically filtered, so that the switching loss of the high-power switching device is reduced, and further, the requirement on a heat dissipation system of the power electronic device is reduced.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides an anti-interference method for driving signals of a cascade converter.
According to the anti-interference method for the PWM driving signals of the cascade converter, the FPGA sends the PWM driving signals in a specific coding mode, and the CPLD receives and decodes the coding signals to obtain the PWM driving signals, so that the direct long-line transmission of the driving signals is prevented from being easily influenced by high-frequency electromagnetic interference, the anti-interference capability of the PWM driving signals is improved, and the reliable, safe and stable operation of a power electronic system is ensured; meanwhile, the method can automatically filter PWM narrow pulse signals generated by high-frequency modulation, and reduce the switching loss of a high-power switching device.
Further, fig. 2 is a system block diagram, and in order to improve the anti-interference capability in the PWM driving signal transmission process, the encoding method of fig. 3 and the decoding method corresponding to fig. 4 are adopted.
Further, the anti-interference encoding method for the PWM driving signal in fig. 3 specifically comprises the following steps:
s1, an FPGA in a main controller transmits an initial code v of a PWM coding signal bit by bit according to a set baud rate 1 v 2 v 3 “011”；
Step S2, immediately reading the level value of the PWM signal generated by the internal carrier modulation of the FPGA after the start code is sent, and if the level value is 1, encoding the signal v 4 v 5 v 6 Taking "101", if the level value is "0", signal encodingv 4 v 5 v 6 Taking "010" while adding stop code v at the end of encoding 7 Constant "1";
step S3, continuously transmitting the code v generated in step S2 bit by bit according to the baud rate of step S1 4 v 5 v 6 v 7 ；
Further, the anti-interference decoding method for the PWM driving signal in fig. 4 specifically comprises the following steps:
step S1, CPLD in IGBT driver samples the input PWM coding signal according to the baud rate of step S1 of claim 3, CPLD receives and compares the initial coding v bit by bit 1 v 2 v 3 If the bit-by-bit comparison is identical, continuing to receive the subsequent codes; otherwise, immediately ending the sampling of the current round, and keeping the level of the driving signal currently output by the CPLD unchanged;
step S2, if the initial code is identical in bit-by-bit comparison, continuing to receive the subsequent four-bit code v 4 v 5 v 6 v 7 The specific logic level value of the four-bit code is not needed to be considered in the process;
step S3, immediately after the subsequent four-bit code is received, the last code v is immediately coded 7 Comparing with '1', if the same, decoding the driving signal; otherwise, immediately ending the sampling of the round, and keeping the level of the driving signal output by the CPLD unchanged;
step S4, if the stop codes are the same, then the code v is coded 4 v 5 v 6 Judging that if the value is '101', the CPLD output driving signal is high level '1', if the value is '010', the CPLD output driving signal is low level '0', otherwise, the level of the driving signal output by the CPLD is kept unchanged.
Further, the influence of high-frequency electromagnetic interference generated by the power switch device on the PWM driving signal due to long-line transmission can be avoided, the anti-interference capability of the PWM driving signal is improved, and therefore reliable, safe and stable operation of a power electronic system is ensured.
Furthermore, as long as the PWM narrow pulse signal generated by high-frequency modulation does not appear at the moment of reading the level value of the PWM signal after the start code is sent, the anti-interference encoding method for the PWM driving signal in fig. 3 can automatically filter the narrow pulse in the PWM signal, so as to reduce the switching loss of the high-power switching device.
It is a further object of the invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of:
the FPGA encodes the PWM driving signal generated by the internal carrier wave, adds a start code and a stop code to the encoding, and sends the encoding according to a certain baud rate;
CPLD receives the coded signal and decodes the coded signal one by one;
when the received start code, PWM signal code and stop code are all correct, the PWM driving signal output by CPLD is updated to the logic level currently received; otherwise, the output PWM drive signal level remains unchanged.
Another object of the present invention is to provide a computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
the FPGA encodes the PWM driving signal generated by the internal carrier wave, adds a start code and a stop code to the encoding, and sends the encoding according to a certain baud rate;
CPLD receives the coded signal and decodes the coded signal one by one;
when the received start code, PWM signal code and stop code are all correct, the PWM driving signal output by CPLD is updated to the logic level currently received; otherwise, the output PWM drive signal level remains unchanged.
The method has wider applicability, is not only suitable for cascading multi-level power electronic systems, but also suitable for other types of multi-level variable current control systems, such as: diode clamps five-level, seven-level or higher level circuits, and MMCs.
By combining all the technical schemes, the invention has the advantages and positive effects that:
in the invention, the PWM driving signal generated by the internal carrier is encoded through the FPGA, and in order to ensure the reliability of transmission encoding, a start code and a stop code are added in the encoding and are transmitted according to a certain baud rate; the CPLD receives the coding signals and compares and decodes the coding signals one by one, and only when the received start code, PWM signal coding and stop code are correct, the PWM driving signal output by the CPLD is updated to the current received logic level; otherwise, the output PWM drive signal level remains unchanged. The method can avoid the influence of high-frequency electromagnetic interference generated in the switching process of the power device when the PWM driving signal is directly transmitted by the long circuit, and improve the anti-interference capability of the PWM driving signal for the long circuit transmission; meanwhile, the method can automatically filter PWM narrow pulse signals generated by high-frequency modulation, and reduce the switching loss of a high-power switching device.
The FPGA does not directly output the PWM driving signal, but sends the PWM driving signal in a specific coding mode, and the CPLD receives and decodes the coding signal to obtain the PWM driving signal, so that the direct long-line transmission of the PWM driving signal is prevented from being easily influenced by high-frequency electromagnetic interference, the anti-interference capability of the PWM driving signal is improved, and the reliable, safe and stable operation of a power electronic system is ensured; meanwhile, the method can automatically filter PWM narrow pulse signals generated by high-frequency modulation, and reduce the switching loss of a high-power switching device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly explain the drawings needed in the embodiments of the present application, and it is obvious that the drawings described below are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of an anti-interference method for driving signals of a cascaded converter according to an embodiment of the present invention.
Fig. 2 is a block diagram of a control system of a cascaded five-level converter according to an embodiment of the present invention;
fig. 3 is a flowchart of an anti-interference encoding method for a PWM driving signal of a cascaded converter according to embodiment 1 of the present invention.
Fig. 4 is a flowchart of an anti-interference decoding method for a PWM driving signal of a cascaded converter according to embodiment 1 of the present invention.
Fig. 5 (a) - (e) are schematic diagrams of the anti-interference method for PWM driving signals of the cascaded converter according to embodiment 1 of the present invention during normal operation;
FIGS. 6 (a) - (e) are schematic diagrams illustrating the processing of the PWM-encoded signal start-up code according to embodiment 2 of the present invention when it is disturbed;
fig. 7 (a) - (e) are schematic diagrams illustrating the PWM signal encoding process of the PWM encoded signal according to embodiment 3 of the present invention when the PWM signal encoding process is disturbed.
Fig. 8 (a) - (e) are schematic views illustrating the processing of the PWM encoded signal according to embodiment 4 of the present invention when the stop code is interfered.
Fig. 9 (a) - (d) are experimental waveforms of the PWM driving signal anti-interference method for a cascaded converter according to embodiment 1 of the present invention during normal operation.
Fig. 10 is an experimental waveform of the anti-interference method for the PWM driving signal of the cascaded converter according to embodiment 1 of the present invention for automatically filtering the PWM narrow pulse signal.
Detailed Description
The present invention will be described in detail with reference to examples below in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Aiming at the problems existing in the prior art, the invention provides an anti-interference method for driving signals of a cascading converter, and the invention is described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides an anti-interference method for driving signals of a cascaded converter, which includes:
s101, encoding a PWM driving signal generated by FPGA carrier modulation, adding a start code and a stop code to the encoding, and transmitting according to a certain baud rate.
S102, the CPLD receives the coded signals and decodes the coded signals one by one.
S103, when the received start code, PWM signal code and stop code are all correct, the PWM driving signal output by the CPLD is updated to the current received logic level; otherwise, the output PWM drive signal level state remains unchanged.
One of ordinary skill in the art may implement the method for anti-interference of driving signals of a cascaded converter according to the present invention by using other steps, and fig. 1 is merely provided as an embodiment.
The invention is further described below in connection with specific embodiments.
Example 1
The embodiment of the invention provides an anti-interference method for PWM driving signals of a cascade converter. Specifically taking a cascaded five-level converter as an example, the system structure of the cascaded five-level converter is schematically shown in fig. 2, and the system mainly comprises a main controller, an interface and sampling circuit, an IGBT driver and an H-bridge power unit, wherein the power unit has A, B and C three phases. Each phase is formed by connecting two H bridges in series, and the total of twenty-four IGBTs are arranged in the cascade five-level converter, so twenty-four paths of PWM driving signals are needed; in order to meet the multi-path PWM driving signals required by the system and simultaneously meet the modular design requirement of the cascaded five-level converter, a scheme of three processors of the DSP, the FPGA and the CPLD in FIG. 2 is adopted, and signal conditioning in FIG. 2 indicates that sampled current and voltage signals are processed to meet the input requirement of the DSP. Note that, since the methods for generating PWM driving signals for the A, B and C three-phase circuits are identical, only the a phase is taken as an example in fig. 2.
The DSP generates an A-phase reference voltage signal according to the control instruction, the current and voltage signals obtained by sampling and the controlled object model, the signal is transmitted to the FPGA to complete modulation, and two groups of four-way phase-shifting PWM signals of 0 degree, 180 degrees, 90 degrees and 270 degrees are generated, wherein the groups of 0 degree and 180 degrees are transmitted to the A-phase H bridge 1, the 0 degree PWM signal is a left bridge arm driving signal, and the 180 degree PWM signal is a right bridge arm driving signal; the 90-degree and 270-degree groups are sent to an A-phase H bridge 2, a 90-degree PWM signal is a left bridge arm driving signal, and a 270-degree PWM signal is a right bridge arm driving signal;
in order to provide four-path PWM signals required by each H bridge, CPLD in IGBT driver generates upper and lower bridge arms according to two input PWM driving signals (0 degree and 180 degree or 90 degree and 270 degree)Complementary four-way driving signals containing dead zones, namely CPLD generates two-way PWM signals containing certain dead zone time by using 0 degree (or 90 degree) PWM signals to respectively drive T of A-phase H bridge 1 (or 2) 1 And T 2 The method comprises the steps of carrying out a first treatment on the surface of the 180 degrees (or 270 degrees) PWM signals generate two paths of PWM signals with certain dead time to respectively drive T of A-phase H bridge 1 (or 2) 3 And T 4 。
Fig. 3 is a flowchart of an anti-interference encoding method of the PWM driving signal of the cascaded converter, and fig. 4 is a flowchart of an anti-interference decoding method of the PWM driving signal of the cascaded converter.
The method specifically comprises the following steps:
s1, an FPGA in a main controller transmits an initial code v of a PWM coding signal bit by bit according to a set baud rate 1 v 2 v 3 “011”；
Step S2, immediately reading the level value of the PWM signal generated by the internal carrier modulation of the FPGA after the start code is sent, and if the level value is 1, encoding the signal v 4 v 5 v 6 Taking "101", if the level value is "0", the signal codes v 4 v 5 v 6 Taking "010" while adding stop code v at the end of encoding 7 Constant "1";
step S3, continuing to transmit the code v generated in step S2 bit by bit according to the baud rate of step S1 4 v 5 v 6 v 7 ；
Step S4, the CPLD in the IGBT driver samples the input PWM coding signal in real time according to the baud rate of the step S1, and the CPLD receives and compares the initial coding v bit by bit 1 v 2 v 3 If the bit-by-bit comparison is identical, the subsequent encoding is continuously received, otherwise, the sampling of the round is immediately finished, and meanwhile, the level state of the driving signal currently output by the CPLD is kept unchanged;
step S5, if the initial code is identical in bit-by-bit comparison, continuing to receive the subsequent four-bit codes v 4 v 5 v 6 v 7 The specific logic level value of the four-bit code is not needed to be considered in the process;
step S6, immediately after the subsequent four-bit code is received, the last code v is coded 7 With "1Comparing, if the driving signals are the same, decoding the driving signals; otherwise, immediately ending the sampling of the round, and keeping the level state of the driving signal output by the CPLD unchanged;
step S7, if the stop codes are the same, then the code v is coded 4 v 5 v 6 Judging that if the value is '101', the CPLD output driving signal is high level '1', and if the value is '010', the CPLD output driving signal is low level '0'; otherwise, the level state of the driving signal output by the CPLD is kept unchanged;
5 (a) - (e) are waveform diagrams of the cascade converter PWM driving signal during normal operation of the anti-interference encoding and decoding method. Fig. 5 (c) shows the PWM encoded signal output by the FPGA, and fig. 5 (d) shows the PWM encoded signal received by the CPLD. Since the start code, PWM signal encoding, and stop code are all correct, the signal is decoded to fig. 5 (e), t 1 V before the moment 4 v 5 v 6 Encoding "101", so t in FIG. 5 (e) 1 Outputting a high level at a moment; t is t 2 V before the moment 4 v 5 v 6 Code "010", so t in FIG. 5 (e) 2 The low level is output at the moment.
Example 2
The embodiment of the invention is a processing mechanism when the initial code of a PWM code signal is interfered, and takes a cascaded five-level converter as an example. Fig. 6 (a) - (e) are schematic waveforms of the PWM encoded signals when the initial encoding is disturbed, and the PWM encoded signals output by the FPGA of fig. 6 (c) become waveforms shown in fig. 6 (d) due to high-frequency electromagnetic interference, that is, the initial encoding received by the CPLD is wrong. T in FIG. 6 (e) 1 Start code v sampled by CPLD before moment 1 Error, so t 1 The moment output PWM driving signal is kept at a high level, and the current wheel sampling is immediately ended; t in FIG. 6 (e) 2 Start code v sampled by CPLD before moment 2 Error, so t 2 The time-of-day output PWM drive signal remains low and the current wheel sampling immediately ends.
Example 3
The embodiment of the invention is a processing mechanism when PWM signal coding is interfered in PWM coding signals, and takes a cascaded five-level converter as an example. FIG. 7 (a)(e) For the waveform diagram of the PWM signal code in the PWM code signal when the PWM signal code is interfered, the PWM code signal output by the FPGA of fig. 7 (c) becomes the waveform shown in fig. 7 (d) due to the high-frequency electromagnetic interference, that is, the signal code v received by the CPLD 4 v 5 v 6 Error. T in FIG. 7 (e) 1 Signal code v sampled by CPLD before moment 6 Error, so t 1 The moment output PWM driving signal is kept at a high level, and the current wheel sampling is finished; t in FIG. 7 (e) 2 Signal code v sampled by CPLD before moment 5 Error, so t 2 The moment output PWM drive signal remains low and the current wheel sampling ends.
Example 4
The embodiment of the invention is a processing mechanism when a stop code in a PWM coding signal is interfered, and takes a cascaded five-level converter as an example. FIGS. 8 (a) - (e) are schematic waveforms of the PWM encoded signal when the stop code is disturbed, and the stop code outputted from the FPGA of FIG. 8 (c) is changed into the waveform of FIG. 8 (d), i.e. the stop code v received by the CPLD due to high frequency electromagnetic interference 7 Becomes "0". T in FIG. 8 (e) 1 Stop code v sampled by CPLD before moment 7 Error, so t 1 The moment output PWM drive signal remains high and immediately ends the current wheel sample.
The invention is further described in connection with the effects.
The invention discloses an anti-interference method for PWM driving signals of a cascade converter. The FPGA does not directly output a PWM driving signal generated by internal carrier modulation, but codes the driving signal in a specific form, wherein the codes comprise a start code, a PWM signal code and a stop code, and then the FPGA sends the signals according to a set baud rate, and the CPLD receives and decodes the coded signals. Only when the received start code, PWM signal code and stop code are correct, the PWM driving signal output by CPLD is updated to the current received logic level; otherwise, the output PWM drive signal level state remains unchanged.
The technical scheme of the invention adopts an encoding mode to transmit the PWM driving signal, thereby avoiding that the direct long-line transmission of the PWM driving signal is easily affected by high-frequency electromagnetic interference, improving the anti-interference capability of the PWM driving signal and ensuring the reliable, safe and stable operation of a power electronic system; meanwhile, the technical scheme of the invention can also automatically filter PWM narrow pulse signals generated by high-frequency modulation, and reduce the switching loss of the high-power switching device. The scheme is simple, and is realized by software only, so that the hardware cost of the system is not increased additionally; the invention is not only suitable for cascading multi-level power electronic systems, but also suitable for other types of multi-level variable current control systems, such as: diode clamps five-level, seven-level or higher level circuits, and MMCs.
The invention is further described in connection with specific experiments.
Fig. 9 (a) - (d) are experimental waveforms of the PWM drive signal anti-interference encoding and decoding method of the cascaded converter when operating normally; wherein, the channel 3 is a PWM signal modulated and output by the FPGA carrier wave, and the channel 1 is a corresponding encoded signal of the PWM signal output by the FPGA; channel 2 is the encoded signal received by the CPLD, and channel 4 is the PWM signal decoded and output by the CPLD.
In fig. 9 (a), the PWM signal output by the carrier modulation of the FPGA is low, and the encoded signal received by the CPLD is identical to the encoded signal output by the FPGA, so the PWM signal decoded and output by the CPLD is correspondingly low. Similarly, in fig. 9 (b), when the PWM signal output by the FPGA carrier modulation is at the high level, the conclusion is the same as that in fig. 9 (a).
In fig. 9 (c), the PWM signal output by the carrier modulation of the FPGA is changed from low level to high level, and the encoded signal received by the CPLD is always the same as the encoded signal output by the FPGA in the whole process, and because the encoding causes a certain delay, the PWM signal output by the CPLD in decoding is also changed from low level to high level after a small delay. Similarly, in fig. 9 (d), when the PWM signal outputted from the FPGA carrier modulation is changed from the high level to the low level, the conclusion is the same as that in fig. 9 (c).
Fig. 10 is an experimental waveform of the anti-interference method for the PWM driving signal of the cascaded converter according to embodiment 1 of the present invention for automatically filtering the PWM narrow pulse signal; wherein, the channel 3 is a PWM signal modulated and output by the FPGA carrier wave, and the channel 1 is a corresponding encoded signal of the PWM signal output by the FPGA; channel 2 is the encoded signal received by the CPLD, and channel 4 is the PWM signal decoded and output by the CPLD. When the PWM signal generated by the high-frequency carrier modulation in the FPGA is a narrow pulse, as shown in fig. 10, the very narrow pulse is 320ns, and the narrow pulse generated by the high-frequency modulation does not occur at the time of reading the level value of the PWM signal after the start code is sent, so that the PWM narrow pulse signal cannot be encoded, and the encoded signal output by the FPGA and the encoded signal received by the CPLD are always kept as the encoding of the low-level signal, so that the PWM signal decoded and output by the CPLD is low-level, and the function of automatically filtering the PWM narrow pulse signal is realized.
In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more; the terms "upper," "lower," "left," "right," "inner," "outer," "front," "rear," "head," "tail," and the like are used as an orientation or positional relationship based on that shown in the drawings, merely to facilitate description of the invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
It should be noted that the embodiments of the present invention can be realized in hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or special purpose design hardware. Those of ordinary skill in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such as provided on a carrier medium such as a magnetic disk, CD or DVD-ROM, a programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The device of the present invention and its modules may be implemented by hardware circuitry, such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., as well as software executed by various types of processors, or by a combination of the above hardware circuitry and software, such as firmware.
The foregoing is merely illustrative of specific embodiments of the present invention, and the scope of the invention is not limited thereto, but any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention will be apparent to those skilled in the art within the scope of the present invention.
Claims (6)
1. The anti-interference method for the driving signals of the cascaded converters is characterized by comprising the following steps of:
the FPGA encodes a PWM driving signal generated by internal carrier modulation, adds a start code and a stop code to the encoding, and continuously transmits the encoding according to a certain baud rate;
CPLD receives the coded signal and decodes the coded signal one by one;
when the received start code, PWM signal code and stop code are all correct, the PWM driving signal output by CPLD is updated to the logic level currently received; otherwise, the level state of the output PWM driving signal is kept unchanged;
the CPLD receives the coded signals and decodes the coded signals one by one, and the method comprises the following steps:
step 1, in an IGBT driver, CPLD samples an input PWM coding signal in real time according to the baud rate of step S1, and the CPLD receives and compares initial codes bit by bitv 1 v 2 v 3 If the bit-by-bit comparison is identical, the subsequent encoding is continuously received, otherwise, the sampling of the round is immediately finished, and meanwhile, the level of the driving signal currently output by the CPLD is kept unchanged;
step 2, if the start code is identical in bit-by-bit comparison, continuing to receive the subsequent four-bit codesv 4 v 5 v 6 v 7 ；
Step 3, after the subsequent four-bit code is received, the last code is codedv 7 Comparing with "1", and if the same, performing drive signalDecoding; otherwise, immediately ending the sampling of the round, and keeping the level of the driving signal output by the CPLD unchanged;
step 4, if the stop codes are the same, then encodingv 4 v 5 v 6 Judging that if the value is '101', the CPLD output driving signal is high level '1', and if the value is '010', the CPLD output driving signal is low level '0'; otherwise, the level of the driving signal output by the CPLD remains unchanged.
2. The method for anti-interference of driving signals of cascaded converters according to claim 1, wherein the method for encoding PWM driving signals generated by internal carrier modulation by the FPGA comprises:
s1, an FPGA in a main controller transmits an initial code of a PWM code signal bit by bit according to a set baud ratev 1 v 2 v 3 “011”；
S2, immediately reading a PWM signal level value generated by carrier modulation in the FPGA after the start code is sent, and if the level value is 1, encoding the signalv 4 v 5 v 6 Taking "101", if the level value is "0", signal encodingv 4 v 5 v 6 Taking "010" while adding stop code at the end of encodingv 7 Constant "1";
s3, continuously transmitting the codes generated in the step S2 bit by bit according to the baud rate of the step S1v 4 v 5 v 6 v 7 。
3. A computer device, characterized in that the computer device comprises a memory and a processor, the memory stores a computer program, and the computer program when executed by the processor causes the processor to execute the cascaded converter drive signal anti-interference method according to any one of claims 1-2.
4. A computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the cascaded converter drive signal anti-interference method of any one of claims 1-2.
5. A cascaded converter implementing the method for anti-interference of driving signals of the cascaded converter according to any one of claims 1-2.
6. A diode-clamped five-level, seven-level or higher level circuit and an MMC multilevel converter control system implementing the anti-jamming method of the driving signal of the cascaded converter of any one of claims 1-2.
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