CN111931251B

CN111931251B - Trusted computing chip based on blockchain

Info

Publication number: CN111931251B
Application number: CN202010627750.7A
Authority: CN
Inventors: 陈子祺; 田甲
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-07-01
Filing date: 2020-07-01
Publication date: 2024-01-12
Anticipated expiration: 2040-07-01
Also published as: CN111931251A; CN117688623A; CN117688622A

Abstract

The application relates to a trusted computing chip based on a blockchain, which comprises an enclaspe protection module, an intelligent contract execution device and an encryption module, wherein the enclaspe protection module is used for constructing a trusted computing environment on the chip, ensuring the reliability of all data and execution actions on the chip, including, but not limited to, execution of intelligent contracts, signature of data, collection of sensor data and the like; the decoding conversion unit receives the binary code input from the outside, and utilizes the decoding device to reversely analyze the binary code into a contract primitive sequence, and converts the reversely analyzed primitive sequence into an instruction code required by the instruction execution unit according to the pre-embedded primitive meaning function in the decoding device, and the processing result of the instruction execution unit is transmitted to the encryption coprocessor to carry out signature encryption on the calculation result. The trusted computing chip can effectively ensure the credibility of the chip in the computing process, and meanwhile, the execution efficiency of intelligent contracts with complete graphics can be effectively improved for the server to call.

Description

Trusted computing chip based on blockchain

Technical Field

The application relates to a trusted computing chip based on a blockchain, which is applicable to the technical field of blockchains.

Background

In recent years, blockchain technology has been continuously developed in application and exploration. The bit coin is used as the original blockchain currency, adopts a distributed trusted ledger storage mode, can conduct currency transaction without a central server, and has natural advantages in the aspect of financial currency. The representative project immediately behind is the ethernet, which develops a complete virtual engine for the eidolon based on a blockchain distributed storage system, on which intelligent contracts can be compiled and run, i.e. computable programs can be executed on the decentralised trusted system. The trusted computing unit may be a trusted computing enclosure (Enclave) that provides an application running environment that is executed in isolation.

On the other hand, with the vigorous development of embedded systems, more and more embedded chips are applied to the fields of multimedia, network communication, video monitoring and the like. The wider use means that the more likely it is to be the target to be subject to eavesdropping and attack. Embedded systems, particularly for blockchain applications, are designed to take into account various security factors of the operating state, and are not easily compromised by the system when it is typically running. The upgrading process of the system is often accompanied by a plurality of links such as running interruption, system file replacement, restarting and the like, so that the system is very likely to provide opportunities for an attacker.

At present, no security chip designed for intelligent contract virtual engines with complete graphics is available on the market, and cannot collect data on edge devices and change the state of intelligent contracts on blockchain accordingly. Meanwhile, the chip is not a complete blockchain node environment, and the integrated node cannot be realized because of the large memory and high power consumption.

Disclosure of Invention

The purpose of the application is to provide a trusted computing chip based on a blockchain, which can quickly execute or verify an intelligent contract state under a trusted computing environment on edge equipment, can be trusted and invoked by a server, ensures the credibility of chip data calculation and transmission, facilitates the application of blockchain encryption and credibility technology on the edge equipment, and can greatly expand the application scene of the blockchain.

The application relates to a trusted computing chip based on a blockchain, which comprises an enclaspe protection module, an intelligent contract execution device and an encryption module, wherein the enclaspe protection module is used for constructing a trusted computing environment on the chip and protecting all data states and execution actions on the chip;

the intelligent contract executing device comprises a decoding and converting unit of contract primitives and an instruction executing unit;

the decoding conversion unit receives binary codes input from the outside, and utilizes a decoding device to reversely analyze the binary codes into contract primitive sequences, and converts the reversely analyzed primitive sequences into instruction codes required by the instruction execution unit according to a pre-embedded primitive meaning function in the decoding device;

the encryption module comprises an encryption coprocessor, and the processing result of the instruction execution unit is transmitted to the encryption coprocessor to carry out signature encryption on the calculation result.

Preferably, the instruction execution unit includes a register file and an execution assembly, and the execution assembly is connected with the register file and an external memory.

The execution assembly comprises an instruction reading unit, an instruction decoding unit, an arithmetic logic operation unit, a memory reading and writing unit and a register reading and writing unit; the instruction reading unit receives an output instruction code from the decoding and converting unit of the contract primitive as a bottom instruction to be executed, the instruction decoding unit analyzes the category of the instruction according to the structural code of the instruction, the arithmetic logic operation unit performs operation according to the input instruction code, and performs shaping arithmetic logic operation by operating at least one register, the memory reading and writing unit operates the memory to read or modify data in the memory, and the register reading and writing unit operates the register file to read or modify data of each register in the register file.

Wherein the register file includes a PC instruction counter that directs the index of a read instruction or the modified settings by a jump instruction. The register file also includes control and status registers and compute reservation registers.

The encryption coprocessor provides an asymmetric encryption method, performs asymmetric encryption on an execution result according to a unique identity of a hardware key written in the encryption coprocessor, generates a signature and outputs the signature. The key is randomly written on the trusted computing chip during the manufacturing process for identification of the trusted computing chip, the key comprising an inaccessible private key and a public key that can be read for server authentication.

The trusted computing chip is divided into a trusted area and an untrusted area; when the trusted computing chip executes multi-user intelligent contracts, the chip configures respective software and hardware resources for a plurality of intelligent contract execution programs in a machine mode, and the intelligent contract execution programs in a trusted area are isolated from each other; when a multi-user trusted intelligent contract exists, one application program in a plurality of intelligent contract executing programs running on the trusted computing chip accesses protected resources of other trusted intelligent contract programs, a corresponding private key or an access instruction signed by the private key is required to be provided, and verification and arbitration are carried out by a security monitor to determine the access authority of the security monitor to other trusted application programs and resources.

When the trusted computing chip executes the intelligent contracts, each trusted intelligent contract executing program uses software and hardware resources allocated by the security monitor, places application program codes in a trusted area, accesses a protected physical memory, calls processor kernel resources allocated by the security monitor, writes the execution results of the intelligent contracts into the protected physical memory, and is responsible for subsequent processing of the execution results of the intelligent contracts by the security supervisor.

The protection mechanism of the trusted computing chip comprises physical memory protection, wherein the physical memory of the chip is protected through a direct physical address or a virtual memory system by setting a trusted area and an untrusted area; or alternatively

The protection mechanism of the trusted computing chip comprises processor kernel protection, software and hardware resource protection and trust base protection, wherein the processor kernel resource, the software and hardware resource and the trust base which can be accessed by each user program are configured in a machine mode, and when abnormality occurs, the control right is transferred to the machine mode to carry out identification and authorization of the access right.

By introducing an instruction set on hardware and hardware acceleration, the execution efficiency of the intelligent contract can be greatly improved, and the power consumption is effectively reduced; through a random private key hardware writing method, the identification of each chip is unique and cannot be falsified; through the designed memory protection instruction and the enclaspe memory protection method, the calculation process on the chip is ensured to be credible. In the trusted computing environment, the signature output of the execution result of the contract is realized through the built-in encryption function, so that the falsification of data by a third party in the network transmission process can be prevented, and the server side can acquire the collected data in the real edge equipment or the execution state of the contract through the preset chip white list.

The method and the device have the advantages that the solution of trusted computing is designed completely from the steps of data generation, computing and memory change to network transmission, and the reliability of chip computing can be guaranteed to the greatest extent while the blockchain technology is applied to the edge equipment. Therefore, the trusted computing chip can effectively ensure the credibility of the chip in the computing process, and can effectively improve the execution efficiency of intelligent contracts with complete graphics so as to be called by a server.

Drawings

FIG. 1 shows a model block diagram of a trusted computing chip of the present application.

FIG. 2 shows a model block diagram of an intelligent contract execution apparatus in a trusted computing chip of the present application.

FIG. 3 shows a block diagram of the model of the instruction execution unit in the trusted computing chip of the present application.

Fig. 4 shows a schematic diagram of the internal logic of the trusted computing unit of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.

The trusted computing chip based on the blockchain mainly comprises three modules, namely an enclaspe protection module, an intelligent contract execution device and an encryption module.

The enclave protection module is used for constructing a trusted computing environment on the chip, supervising and ensuring the reliability of all data and execution actions on the chip, including but not limited to the safety of data in the chip, information exchange with external software and hardware, and the like. The protection module relates to the cooperative operation of software and hardware, and mainly ensures the maintenance of memory data in the chip execution process by designing a hardware protection instruction on a chip, and does not allow the memory to be tampered in a mode of bypassing the hardware protection instruction; through the designed enclaspe software protection method, the stability of memory data in the chip instruction execution process is ensured, and other applications are not allowed to tamper with the memory data used by another application. The data storage state on the chip comprises a buffer memory and a register, which are controlled and maintained by the module, and the data access actions of the chip and an external memory, a server, a hard disk and the like are also constructed by the module to form a trusted interaction environment.

Specifically, before the chip executes the application program, a security supervisor with higher authority sets an enclave parameter of the application program, wherein a hardware instruction for setting a memory protection parameter is involved, when an illegal user accesses and falsifies data of the enclave, the access is required to access a Control and Status Register (CSR) through the instruction, and the access can cause an abnormal interrupt to be sent to a Security Monitor (SM) due to no authority, so that the access and the falsification of the memory are protected.

The intelligent contract executing device is supervised by the enclaspe protecting module, ensures that all the calculation is credible and safe, and mainly plays a role in analyzing and executing intelligent contract binary codes input by the chip. Preferably, a hot plug decoding device may be provided, on which a contract execution module bottom instruction set corresponding to an intelligent contract binary code is stored.

The intelligent contract executing device comprises two parts, a decoding and converting unit and an instruction executing unit. The decoding conversion unit reads the contract primitive corresponding code according to the decoding device which can be hot plugged and unplugged, and converts the contract primitive corresponding code into the bottom instruction code required by the execution unit. The instruction execution unit adopts a general pipeline design and RISC-V reduced instruction set, reads, analyzes and executes the bottom instruction code. Preferably, the instruction execution unit defaults to 256-bit shaped data calculation operations, which do not support floating point operations, which can greatly speed up instruction execution efficiency and simplify the parsing logic.

The encryption module includes an encryption coprocessor that provides an asymmetric encryption method that signs given input data using a built-in key. And the data can be verified at the server according to the public key of the chip. It should be noted that this process is not reversible. Under different requirements, the original data may need to be transmitted to the server together with the signature.

The key management method in the encryption module comprises the following steps: during the manufacture of the blockchain trusted computing chip, a key for identification is randomly written in a hardware level. The secret key comprises a private key and a public key, the private key is not accessed by other modules, and the public key can be read for chip white list identification or data verification of the server. Compared with the traditional method for storing the key by the hard disk, the key randomly written in the hardware level has great improvement in safety, the hard disk is isolated from the chip, a third party can steal the hard disk data without the permission of the chip, and the key built in the chip can completely prevent the problem. In addition, the secret key is stored on the chip, can access the user through rights management, is matched with the trusted computing environment constructed by the previous enclaspe, can seamlessly protect the safety of the private key on the chip, can not read the unique built-in identification on the chip by any person, and can only identify the identity of the chip through the public key. The pairing of public and private keys is asymmetric, i.e., the private key can generate a public key, which cannot be pushed against.

Examples

As shown in fig. 1-3, the trusted computing chip 100 of the present application includes a cryptographic coprocessor 200, an enclave protection module 201, and an intelligent contract execution device 202. Wherein the smart contract execution apparatus 202 expands the input binary contract primitives to the underlying instruction set logic and generates the underlying instruction execution sequence using the pluggable configured contract primitive decoding apparatus 203. Different decoding devices are configured for intelligent contracts with complete different graphics, so that the function of custom loading contract codes can be realized, and the chip is convenient to transplant or upgrade the intelligent contracts. The smart contract execution apparatus 202 includes a decode and translation unit 301 and an instruction execution unit 302 of contract primitives.

The decoding and converting unit 301 accepts a binary code input from the outside of the chip, where the binary code is a smart contract code with complete graphics, and the binary code may be compiled and deployed into a binary sequence executed in a virtual engine. The decoding and converting unit 301 parses the binary code into a contract primitive sequence, and converts the parsed primitive sequence into an instruction set expression of the chip bottom layer according to a primitive meaning function pre-embedded in the external hot-plug decoding device 203. The intelligent contracts supported by different virtual engines are designed differently, and the parameter configuration in the corresponding decoding device is also differentiated, so long as the equivalent contract primitive function can be designed according to the chip bottom instruction.

The decode conversion unit 301 can count the amount of computation (GAS) required for inputting the contract code consumed by the code in order to solve the problem of the complete language of the figure without stopping. The problem of contract code non-stop is theoretically impossible to solve, so the module will preset a GAS maximum value, for example 1000 ten thousand, beyond which the decoding translation unit will interrupt the decoding process immediately and return an error result, which can be achieved by setting the GAS overflow error register bit.

The instruction execution unit 302 employs a general purpose computing unit (CPU) design, including multi-stage pipeline processing modules, that can speed up instruction execution time and enhance parallel computing capabilities. In addition, the bottom layer of the unit is theoretically a complete computing device of the figure, and can handle most of the problems which can be handled in the general-purpose computer by realizing a RISC-V reduced instruction set. The instruction set mainly comprises a jump instruction, a shaping arithmetic operation instruction, a register read-write instruction and a memory read-write instruction.

Instruction execution unit 302 includes a register file 402 and execution components coupled to register file 402 and memory 401 for performing computations by read and write access to the data interfaces of register file 402 and memory 401.

The register file 402 includes the PC instruction counter 400, and may further include control and status registers, calculation reservation registers, and the like (not shown). The PC instruction counter 400 is used to direct the index of the read instruction or to modify the settings by the jump instruction. The control and status registers are used to record various states of instruction execution including, but not limited to, data overflows, interrupt bits, whether the sequence is empty, etc. The calculation reservation register is mainly used for an arithmetic logic operation unit to perform rapid 256-bit shaping data calculation.

The execution assembly is divided into a plurality of computing equipment units, so that the parallel operation of the pipeline is facilitated, and the computing capacity of the chip is fully utilized. The block sequence includes an instruction fetch unit 403, an instruction decode unit 404, an arithmetic logic unit 405, a memory read write unit 406, a register read write unit 407.

Instruction fetch unit 403: output is accepted from the decode translation unit of the contract primitive as the underlying instruction that needs to be executed. Preferably, the instruction reading unit is internally provided with a buffer module, so that a large number of instruction sequences can be received at one time, and the condition of instruction omission is prevented.

Instruction decode unit 404: the instruction category is resolved according to the instruction structure code, and different instruction categories may involve processing logic inconsistent with subsequent units. The jump instruction modifies the value of the PC instruction counter according to the calculation result to realize the logic judgment function of the binary program, and the calculation result can be known only in the fifth section of the pipeline, so that four cavitation bubbles can appear after the pipeline period, and no instruction is executed. In this embodiment, the invalid time consuming caused by the jump instruction is reduced as much as possible by adopting a processing method of advanced prediction, the instruction counter is increased by one (no jump) prediction logic by default, if the jump occurs, 4 instructions which are subsequently brushed in are invalidated, the input result is not processed, the instruction counter is updated, and the execution instruction sequence is updated. The shaping arithmetic operation instruction is the shaping operation addition, subtraction, multiplication and division calculation, wherein the division operation does not generate remainder and decimal, which is limited in a virtual engine in the Ethernet, and the shaping arithmetic operation data are all 256 bits. The register read-write instruction is used for operating the data in the register file, the memory read-write instruction is used for operating the memory data, and the memory state is read or the execution result is written.

An arithmetic logic operation unit 405: the unit is a core component of an instruction execution unit, and has the main functions of performing binary arithmetic and logical operations according to input, and performing shaping arithmetic and logical operations such as addition, subtraction, multiplication (including no division), inversion, bit operation and the like by operating at least one register. The unit is designed for the underlying electronic logic circuit and generally operates within one clock cycle.

Memory read/write unit 406: the unit mainly operates the external memory 401 of the chip to read or modify the memory data.

Register read-write unit 407: the unit primarily operates the register file 402 to read or modify the data of the registers in the register file. Because instruction execution may require setting data inside different registers, such as jump instructions requiring setting a PC counter, data overflow requiring setting a register overflow bit, etc.

The execution assembly sequentially calls the five modules, and reads the instructions in the instruction cache to the instruction reading unit according to the index in the PC counter in each clock period ascending section. The instruction decoding unit, the arithmetic logic operation unit, the memory read-write unit and the register read-write unit respectively read the processing results of the previous unit. In the falling period of the clock cycle, each unit outputs the execution result. The multi-stage pipeline structure is constructed, so that the chip hardware performance can be fully utilized, and excessive energy consumption loss is reduced.

Finally, the processing result of the instruction execution unit 302 is passed to the encryption coprocessor 200 to sign the calculation result. The encryption coprocessor 200 performs asymmetric encryption on the execution result according to the unique identifier of the internal hardware key, generates a signature, and outputs the signature. Preferably, the cryptographic coprocessor 302 may be configured to pass input execution results together to the output, facilitating possible metadata requirements in different application scenarios.

As shown in fig. 4, the trusted computing unit to which the present application relates is depicted by a module 600. The module is divided into 3 working modes: user mode, administrator mode, and machine mode. Where 601, 602 are user modes, 603, 604 are administrator modes, and 605 is machine mode. The trusted computing unit divides the chip into two areas, one being the untrusted areas 601, 603 and one being the trusted areas 602, 604. The trusted computing chip limits users, codes and programs in the untrusted area to access only own software and hardware resources.

Within the trusted computing chip, hardware provides security primitives and interfaces. The trusted software component (e.g., bootloader, SM) with the highest authority is assigned the smallest responsibility, i.e., is responsible for the trusted region only. Meanwhile, the rest application programs are divided into trusted applications and untrusted applications, and the trusted applications are pushed to a trusted area, and the related memory, instructions and software and hardware resources adopt a protection mechanism to prevent the untrusted applications from being illegally accessed. The trusted computing chip firstly enters a machine mode, enjoys the highest operation authority, configures the whole software and hardware system, loads the user intelligent contract execution program corresponding to the intelligent contract execution device, and distributes the physical Protected Memory (PMP) and other protected hardware resources required by the program.

Under the condition of executing multi-user intelligent contracts, the block chain intelligent contract trusted computing chip configures respective software and hardware resources for a plurality of intelligent contract executing programs in a machine mode, the intelligent contract executing programs in the trusted region 602 cannot be mutually accessed and isolated, and other untrusted application programs cannot access protected contents such as programs, memory data and the like in the trusted region.

When a multi-user trusted smart contract exists, one of the applications 0-N running on the multiple smart contract execution programs on the blockchain smart contract trusted computing chip accesses the protected resources of the other trusted smart contract programs, a corresponding private key or an access instruction signed by the private key needs to be provided, and the Security Monitor (SM) 605 performs verification and arbitration to determine the access rights of the application 0-N to the other trusted application or resources.

When the block chain intelligent contract trusted computing chip executes the intelligent contracts, each trusted intelligent contract executing program uses software and hardware resources allocated by an SM, places application program codes in a trusted area, accesses a protected physical memory, calls processor kernel resources allocated by the SM, writes the execution results of the intelligent contracts into the protected physical memory, and is responsible for further subsequent processing such as distribution and broadcasting of the intelligent contract execution results by a safety supervisor.

The protection mechanism of the trusted application program comprises physical memory protection of the trusted computing chip of the blockchain intelligent contract, and an untrusted user, code and program can only access own memory, so that a machine mode is allowed to specify the physical memory which can be accessed by the user, code and program in each user mode. Any illegal out-of-range access will be abnormal, and control is handed over to the machine mode for access rights identification and authorization. In the protection mechanism of the physical memory, the physical memory of the chip can be protected through a direct physical address by setting a trusted area and an untrusted area, and the physical memory can also be protected through a virtual memory system. When a virtual memory system is adopted, the addresses in the chip are all virtual addresses, and to access the physical memory, the virtual addresses must be converted into real physical addresses through an address conversion unit.

The trusted application protection mechanism of the smart contract trusted computing chip further includes processor kernel protection 606, software and hardware resource protection 607, and trust base protection 608, which configure processor kernel resources, software and hardware resources, and trust bases that each user program can access in machine mode. Any illegal out-of-range access will be abnormal, and control is handed over to the machine mode for access rights identification and authorization.

The smart contract execution process, the protection method and mechanism for the smart contract execution in the trusted computing chip, and the characteristics, requirements and the like of the chip design involved in the execution of the smart contract by the trusted computing chip form the main body of the present application. The method and the device can integrate the blockchain virtual engine function in the edge device, so that the intelligent contract result can be quickly and efficiently executed or verified in a real environment and uploaded into the blockchain. In addition, the trust protocol design of the chip ensures the reliability of the calculation of the data in the device, and the encryption coprocessor can ensure the effectiveness of the data in the network transmission process and prevent the third party device from stealing information or forging false data in the middle to the server.

Although the embodiments disclosed in the present application are described above, the descriptions are merely for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the patent claims of this application shall be subject to the scope of the claims that follow.

Claims

1. The block chain-based trusted computing chip is characterized by comprising an enclaspe protection module, an intelligent contract execution device and an encryption module, wherein the enclaspe protection module is used for constructing a trusted computing environment on the chip and protecting all data states and execution actions on the chip; before the trusted computing chip executes the application program, a security supervisor with higher authority sets an enclaspe parameter of the application program, wherein a hardware instruction for setting a memory protection parameter is involved, when an illegal user accesses and falsifies the data of the enclaspe, the access control and the status register are required to be accessed through the instruction, and if the access is not authorized, an abnormal interrupt signal is sent to the security monitor, so that the access and the falsification of the memory are protected;

the intelligent contract executing device is supervised by the enclaspe protection module, and comprises a decoding conversion unit and an instruction executing unit of contract primitives;

the decoding conversion unit receives binary codes input from the outside, the binary codes are intelligent contract codes with complete graphics, binary sequences which can be executed in a virtual engine after compiling can be deployed, the binary codes are utilized to reversely analyze contract primitive sequences, and the reversely analyzed primitive sequences are converted into instruction codes required by the instruction execution unit according to the pre-embedded primitive meaning functions in the decoding device; the decoding device is different decoding devices configured according to intelligent contracts of different graphic devices, and can realize the function of custom loading contract codes so as to facilitate the transplantation of chips or the upgrading of intelligent contracts;

2. The trusted computing chip of claim 1, wherein said instruction execution unit comprises a register file and an execution component, said execution component coupled to said register file and external memory.

3. The trusted computing chip of claim 2, wherein said execution component comprises an instruction fetch unit, an instruction decode unit, an arithmetic logic unit, a memory read write unit, and a register read write unit; wherein,

the instruction reading unit receives the output instruction code from the decoding and converting unit of the contract primitive as the bottom instruction to be executed,

the instruction decoding unit analyzes the category of the instruction according to the structural code of the instruction,

the arithmetic logic operation unit performs an operation according to an input instruction code, performs a shaping arithmetic logic operation by operating at least one register,

the memory read-write unit operates the memory to read or modify data in the memory,

the register read-write unit operates the register file to read or modify data of each register in the register file.

4. A trusted computing chip as claimed in claim 2 or 3, wherein said register file comprises a PC instruction counter that directs the index of a read instruction or is modified by a jump instruction.

5. The trusted computing chip of claim 4, wherein said register file further comprises control and status registers and a compute reservation register.

6. The trusted computing chip of any one of claims 1-3, 5, wherein said encryption co-processor provides an asymmetric encryption method for asymmetrically encrypting the execution result according to the unique identity of the hardware key written therein, generating a signature and outputting.

7. The trusted computing chip of claim 6, wherein said key is randomly written on said trusted computing chip during manufacturing for identification of said trusted computing chip, said key comprising an inaccessible private key and a public key that can be read for server verification.

8. The trusted computing chip of claim 7, wherein said trusted computing chip is divided into a trusted region and an untrusted region;

when the trusted computing chip executes multi-user intelligent contracts, the chip configures respective software and hardware resources for a plurality of intelligent contract execution programs in a machine mode, and the intelligent contract execution programs in a trusted area are isolated from each other;

when a multi-user trusted intelligent contract exists, one application program in a plurality of intelligent contract executing programs running on the trusted computing chip accesses protected resources of other trusted intelligent contract programs, a corresponding private key or an access instruction signed by the private key is required to be provided, and verification and arbitration are carried out by a security monitor to determine the access authority of the security monitor to other trusted application programs and resources.

9. The trusted computing chip of claim 8, wherein each trusted smart contract execution program uses software and hardware resources allocated by the security monitor to place application code in the trusted region, accesses protected physical memory, invokes processor kernel resources allocated by the security monitor, and writes the execution results of the smart contract into the protected physical memory, with subsequent processing of the execution results of the smart contract being responsible for by the security supervisor when executing the smart contract.

10. The trusted computing chip of claim 8 or 9, wherein the protection mechanism of the trusted computing chip comprises physical memory protection, by setting trusted and untrusted areas, by protecting the chip physical memory by direct physical addresses or by protecting physical memory by a virtual memory system; or alternatively