CN111929570B - State detection circuit and control detection method - Google Patents
State detection circuit and control detection method Download PDFInfo
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- CN111929570B CN111929570B CN202011081403.5A CN202011081403A CN111929570B CN 111929570 B CN111929570 B CN 111929570B CN 202011081403 A CN202011081403 A CN 202011081403A CN 111929570 B CN111929570 B CN 111929570B
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Abstract
The invention discloses a state detection circuit and a control detection method, wherein the state detection circuit comprises: an IO interface circuit, a counting circuit and a logic circuit; the IO interface circuit is mainly used for opening switches with different numbers in different counting states, closing a counter along with the increase of counting when the condition is met, and outputting the counting state at the moment; the counting circuit is mainly used for generating counts from 0 … … 00 to 1 … … 11; the logic circuit comprises a decoding circuit and a logic conversion circuit, wherein the decoding circuit outputs different switch control signals according to the counting state of the counter; the logic conversion circuit converts the counting state of the counter into different internal state control signals. According to the technical scheme, the state detection of various external connection modes is realized in a mode of combining simple time sequence control and voltage detection, the application of a comparator is omitted, and the area of a chip is reduced.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and relates to a state detection circuit and a control detection method.
Background
In electronic products, with the high development of integration, chip design hopes to realize different control modes on the same pin through some simple modes, for example, connecting resistors with different resistance values on the pin, directly grounding, floating, directly connecting a power supply, and the like. The traditional detection method has larger detection circuit area and is not more and more suitable for the development requirement of integrated circuit design.
The traditional control mode is as shown in fig. 1, the voltage division value of the internal resistance node is changed by externally connecting different resistors, the chip judges the voltage value of the node, and different voltage values correspond to different working modes.
The internal circuit is directly grounded outside the IO port, connected with different resistors to the ground in a suspension manner, connected with different resistors to a power supply, directly connected with the power supply and other different external connection modes, and can realize selection of multiple different internal modes as shown in figure 2. The detection mode has the advantages of simple design structure and no need of complex time sequence design; the disadvantage is that the IO port needs more comparators to compare voltages with different connections, which consumes a lot of area resources: each state requires a separate comparator, which is relatively large in area.
Disclosure of Invention
The invention aims to provide a state detection circuit and a control detection method, which can at least realize state detection of various external connection modes and reduce the area of a chip.
According to a first aspect of the present invention, there is provided a state detection circuit comprising:
an IO interface circuit, a counting circuit and a logic circuit;
the IO interface circuit is mainly used for opening switches with different numbers in different counting states, closing the counting circuit along with the increase of counting when the conditions are met, and outputting the counting state at the moment;
the counting circuit is mainly used for generating counts from 0 … … 00 to 1 … … 11;
the logic circuit comprises a decoding circuit and a logic conversion circuit, wherein the decoding circuit outputs different switch control signals according to the counting state of the counting circuit; the logic conversion circuit converts the counting state of the counting circuit into different internal state control signals.
Optionally, the IO interface circuit includes m switches, m current sources, a comparator and a not gate, after one switch and one current source are connected in series, each switch is connected to the IO port, a positive input end of the comparator is also connected to the IO port, a negative input end is connected to the internal reference voltage VREF, and an output end is connected to an input end of the not gate and connected to the logic circuit; along with the increase of the count, the opened current sources become more, when the external fixed resistor of the IO port is connected to the ground, the voltage of the IO end can be gradually increased, and when the voltage is greater than the internal reference voltage VREF, the counting circuit is closed, and the counting state at the moment is output.
Optionally, the IO interface circuit includes m switches, m current sources with different current values, a comparator and a not gate, after one switch and one current source are connected in series, each switch is connected to the IO port, a positive input end of the comparator is also connected to the IO port, a negative input end is connected to an internal reference voltage VREF, and an output end is connected to an input end of the not gate and connected to the logic circuit; along with the increase of the count, the switches corresponding to the sequence are sequentially opened, then the corresponding current source is switched on, other switches are closed, when the external fixed resistor of the IO port is connected to the ground, the voltage of the IO end can be gradually increased, and when the external fixed resistor is greater than the internal reference voltage VREF, the counting circuit is closed, and the counting state at the moment is output.
Optionally, the counting circuit includes n flip-flops, a first nand gate, a second nand gate and a counting detection circuit, a first input end of the first nand gate is connected to an output end of the not gate to obtain an HN signal, a second input end of the first nand gate is connected to CLK, an output end of the first nand gate is connected to a second input end of the second nand gate, a first input end of the second nand gate is connected to an output end of the counting detection circuit to obtain a CNT _ OKN signal, an output end of the second nand gate is connected to a CLK end of the first flip-flop, a Reset end of each flip-flop is connected to an enable signal PD, a D end of each flip-flop is connected to a self Q-bar end of the flip-flop and then connected to a logic circuit, a Q-bar end of an i-1 flip-flop is further connected to a CLK end of an i-th flip-flop, i =2,3,4 … … n, and a; the count detection circuit is configured to turn off the count circuit after determining 11 … … 1 the state.
Wherein m =2nAnd m and n are positive integers.
Optionally, the logic conversion circuit converts the state of the counter circuit into different internal state control signals according to the state of the counter circuit when the comparator is inverted.
According to a second aspect of the present invention, there is provided a control detection method comprising:
in the initial state, an enable signal PD is not enabled, Q < n:0> is 0 … … 00, and a default switch SW <0> is opened;
when the enable signal PD is enabled, the counting circuit starts to count, Q < n:0> starts to count from 0 … … 00, every time the counting circuit increases one bit, the switch SW < j > is opened one more bit in sequence, the current flowing to the external resistor increases one item I < j > until the IO port voltage is greater than the internal reference voltage VREF, HN becomes low, the counting circuit stops counting, and the detected state signal VM < k:0> is output through the logic conversion circuit; when the count circuit is increased to 1 … … 11 and HN is not yet inverted, the count detection circuit outputs a CNT _ OKN signal, turns off the count circuit, and outputs the current state. Wherein k = n, j is less than or equal to m.
According to a third aspect of the present invention, there is provided a control detection method comprising:
in the initial state, an enable signal PD is not enabled, Q < n:0> is 0 … … 00, and a default switch SW <0> is opened;
when the enable signal PD is enabled, the counting circuit starts to count, Q < n:0> starts to count from 0 … … 00, every time the counting circuit increases one bit, the switch SW < j > is correspondingly opened one bit in sequence, the other switches are closed, the current flowing to the external resistor gradually increases until the voltage of the IO port is greater than the internal reference voltage VREF, HN becomes low, the counting circuit stops counting, and the detected state signal VM < k:0> is output through the logic conversion circuit; when the count circuit is increased to 1 … … 11 and HN is not yet inverted, the count detection circuit outputs a CNT _ OKN signal, turns off the count circuit, and outputs the current state.
Compared with the prior art, the technical scheme of the invention realizes the state detection of various external connection modes by combining simple time sequence control and voltage comparison, saves the application of a comparator and greatly reduces the area of a chip; meanwhile, the voltage and the current adopted inside are both internal references and basically do not change along with the changes of the voltage, the temperature and the like of the power supply, and the power supply robustness design of the chip is greatly enhanced.
Drawings
Fig. 1 is a schematic diagram of a common control scheme.
Fig. 2 is a schematic diagram of a conventional internal circuit for state detection.
FIG. 3 is a diagram of a state detection circuit according to an embodiment of the invention.
FIG. 4 is a timing diagram illustrating the operation of the control detection method according to an embodiment of the present invention.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present invention. However, it will be understood by those skilled in the art that the claimed embodiments of the present invention may be practiced without these specific details and with various changes and modifications based on the following embodiments.
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example 1
The embodiment 1 provides a state detection circuit, and the embodiment described below with reference to the drawings is exemplary only for explaining the present invention and is not to be construed as limiting the present invention. The state detection circuit includes:
an IO interface circuit, a counting circuit and a logic circuit;
the IO interface circuit is mainly used for opening switches with different numbers in different counting states, closing the counting circuit along with the increase of counting when the conditions are met, and outputting the counting state at the moment;
the counting circuit is mainly used for generating counts from 0 … … 00 to 1 … … 11; it will be appreciated that this is a binary number, and the counting circuit may output n sets of signals, each set of signals being of both the "0" and "1" type, the initial state being "0 … … 00" (the n sets being 0), increasing from "0 … … 00" to "1 … … 11" in binary form.
The logic circuit comprises a decoding circuit and a logic conversion circuit, wherein the decoding circuit outputs different switch control signals SW < m:0> according to the counting state of the counting circuit; the logic conversion circuit converts the counting state of the counting circuit into different internal state control signals VM < k:0 >.
Wherein SW < m:0> represents the writing method of the switch signals SW0, SW1 and SW2 … … SWm together, and the similar writing method of other corresponding signals is also expressed in the same way.
Therefore, the state detection circuit provided by the invention provides theoretical and structural guarantee for realizing state detection of various external connection modes and reducing the chip area.
Example 2
This embodiment 2 may be further improved on the basis of embodiment 1, and the description thereof will be omitted for the same or similar parts. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. Specifically, as shown in fig. 3, the present embodiment includes:
the IO interface circuit comprises m switches, m current sources, a comparator and a NOT gate, wherein after one switch is connected with one current source in series, each switch is connected to an IO port, the positive input end of the comparator is also connected to the IO port, the negative input end of the comparator is connected with an internal reference voltage VREF, and the output end of the comparator is connected with the input end of the NOT gate and connected to a logic circuit; as the count increases, the current sources that are turned on become more, e.g., 0 … … 00 opens switches SW <0>, 0 … … 01 opens switches SW <0> and SW <1>, and so on; when the external fixed resistor of IO mouth arrives ground, the voltage of IO end can increase gradually, when being greater than inside reference voltage VREF, closes counting circuit, exports the count state this moment.
The currents of the current sources may be the same, different, or partially the same, and may be adjusted according to actual needs.
The counting circuit comprises n flip-flops, a first NAND gate, a second NAND gate and a counting detection circuit, wherein a first input end of the first NAND gate is connected with an output end of the NOT gate to obtain a HN signal, a second input end of the first NAND gate is connected with CLK, an output end of the first NAND gate is connected with a second input end of the second NAND gate, a first input end of the second NAND gate is connected with an output end of the counting detection circuit to obtain a CNT _ OKN signal, an output end of the second NAND gate is connected with a Clk end of the first flip-flop, a Reset end of each flip-flop is connected with an enable signal PD, a D end of each flip-flop is connected with a Q end of the flip-flop and then connected with a logic circuit, a Q end of an i-1 flip-flop is also connected with a Clk end of an i-th flip-flop, i =2,3,4 … … n, and; the count detection circuit is configured to turn off the count circuit after determining 11 … … 1 the state.
The logic conversion circuit corresponds to different counting states and further corresponds to different internal control states under the condition of different external resistors according to the state of the counting circuit when the comparator is reversed, and therefore, the logic conversion circuit is converted into different internal state control signals VM < k:0 >.
Example 3
This embodiment 3 can be further improved on the basis of embodiment 1 or embodiment 2, and the description of the same or similar parts is omitted. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
Specifically, in this embodiment, the current values of the SW < m:0> output signal and I < n > are changed at the same time, which can be substituted. The IO interface circuit comprises m switches, m current sources with different current values, a comparator and a NOT gate, wherein after one switch is connected with one current source in series, each switch is connected to an IO port, the positive input end of the comparator is also connected to the IO port, the negative input end of the comparator is connected with an internal reference voltage VREF, and the output end of the comparator is connected with the input end of the NOT gate and is connected to a logic circuit; along with the increase of the count, the switches corresponding to the sequence are sequentially opened, then the corresponding current source is switched on, other switches are closed, when the external fixed resistor of the IO port is connected to the ground, the voltage of the IO end can be gradually increased, and when the external fixed resistor is greater than the internal reference voltage VREF, the counting circuit is closed, and the counting state at the moment is output.
Example 4
Embodiment 4 may be further implemented in addition to embodiment 1 or embodiment 2, and may not be limited to the state detection circuit described in the present invention. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. Specifically, referring to fig. 3 and 4, the present embodiment includes:
a control detection method, comprising:
in the initial state, an enable signal PD is not enabled, Q < n:0> is 0 … … 00, and a default switch SW <0> is opened;
when the enable signal PD is enabled, the counting circuit starts to count, Q < n:0> starts to count from 0 … … 00, every time the counting circuit increases one bit, the switch SW < j > is opened one more bit in sequence, the current flowing to the external resistor increases one item I < j > until the IO port voltage is greater than the internal reference voltage VREF, HN becomes low, the counting circuit stops counting, and the detected state signal VM < k:0> is output through the logic conversion circuit; when the counter circuit is increased to 1 … … 11 and HN is not yet inverted, the count detection circuit outputs a CNT _ OKN signal (indicating the negation of the signal CNT _ OK, that is, "N" indicates "negation", and for example, the signal HN indicates the negation of the signal H and Q < N-1> N indicates the negation of the signal Q < N-1 >), and the counter circuit is turned off to output the state at that time.
The external IO is assumed to have five connection modes, namely direct grounding, connection of a 25k omega resistor to the ground, connection of a 50k omega resistor to the ground, connection of a 100k omega resistor to the ground and floating; then a two-bit counting circuit and four-bit current information are required at this time; the VREF voltage is 0.8V; the current information is I <0> =2 μ a, I <1> =6 μ a, I <2> =8 μ a, I <3> =20 μ a, respectively. Then, according to the different external connection states, the following state table can be obtained:
TABLE 1
According to the final states of H, Q <1>, Q <0>, it can easily distinguish different external modes and convert them into internal state control signals.
It can be understood that there may be more connection modes for the external IO, and the number of the counting circuit and the current etc. may be adjusted according to the actual external situation, so as to realize the judgment of different external modes.
Example 4
Embodiment 5 may be further implemented in addition to embodiment 1 or embodiment 3, and may not be limited to the state detection circuit described in the present invention. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. Specifically, referring to fig. 3 and 4, the present embodiment includes:
in the initial state, an enable signal PD is not enabled, Q < n:0> is 0 … … 00, and a default switch SW <0> is opened;
when the enable signal PD is enabled, the counting circuit starts to count, Q < n:0> starts to count from 0 … … 00, every time the counting circuit increases one bit, the switch SW < j > is correspondingly opened one bit in sequence, the other switches are closed, the current flowing to the external resistor gradually increases until the voltage of the IO port is greater than the internal reference voltage VREF, HN becomes low, the counting circuit stops counting, and the detected state signal VM < k:0> is output through the logic conversion circuit; when the count circuit is increased to 1 … … 11 and HN is not yet inverted, the count detection circuit outputs a CNT _ OKN signal, turns off the count circuit, and outputs the current state.
In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Claims (7)
1. A state detection circuit, comprising:
an IO interface circuit, a counting circuit and a logic circuit;
the IO interface circuit opens different numbers of switches in different counting states, outputs a signal HN to the counting circuit, closes the counting circuit when the conditions are met along with the increase of counting, and outputs the counting state at the moment;
the counting circuit generates a count Q < n:0> from 0 … … 00 to 1 … … 11, and further comprises a count detection circuit, wherein the count detection circuit is used for outputting a CNT _ OKN signal after judging the state of 11 … … 1 to close the counting circuit;
the logic circuit comprises a decoding circuit and a logic conversion circuit, wherein the decoding circuit outputs different switch control signals aiming at the IO interface circuit according to the real-time counting state of the counting circuit; the logic conversion circuit converts the counting state of the counting circuit into different internal state control signals according to the counting state when the counting circuit is closed.
2. The state detection circuit of claim 1, wherein: the IO interface circuit comprises m switches, m current sources, a comparator and a NOT gate, wherein after one switch is connected with one current source in series, each switch is connected to an IO port, the positive input end of the comparator is also connected to the IO port, the negative input end of the comparator is connected with an internal reference voltage VREF, and the output end of the comparator is connected with the input end of the NOT gate and connected to a logic circuit; along with the increase of the count, the opened current sources become more, when the external fixed resistor of the IO port is connected to the ground, the voltage of the IO end can be gradually increased, and when the voltage is greater than the internal reference voltage VREF, the counting circuit is closed, and the counting state at the moment is output.
3. The state detection circuit of claim 1, wherein: the IO interface circuit comprises m switches, m current sources with different current values, a comparator and a NOT gate, wherein after one switch is connected with one current source in series, each switch is connected to an IO port, the positive input end of the comparator is also connected to the IO port, the negative input end of the comparator is connected with an internal reference voltage VREF, and the output end of the comparator is connected with the input end of the NOT gate and is connected to a logic circuit; along with the increase of the count, the switches corresponding to the sequence are sequentially opened, then the corresponding current source is switched on, other switches are closed, when the external fixed resistor of the IO port is connected to the ground, the voltage of the IO end can be gradually increased, and when the external fixed resistor is greater than the internal reference voltage VREF, the counting circuit is closed, and the counting state at the moment is output.
4. The state detection circuit according to claim 2 or 3, characterized in that: the counting circuit further comprises n flip-flops, a first NAND gate and a second NAND gate, wherein a first input end of the first NAND gate is connected with an output end of the NOT gate to obtain a HN signal, a second input end of the first NAND gate is connected with CLK, an output end of the first NAND gate is connected with a second input end of the second NAND gate, a first input end of the second NAND gate is connected with an output end of the counting detection circuit to obtain a CNT _ OKN signal, an output end of the second NAND gate is connected with a Clk end of the first flip-flop, a Reset end of each flip-flop is connected with an enable signal PD, a D end of each flip-flop is connected with a self Q-NOT end of the flip-flop and then connected with a logic circuit, a Q-NOT end of an i-1 flip-flop is further connected with a Clk end of an i-th flip-flop, i =2,3, 4.
5. The state detection circuit of claim 3, wherein: the logic conversion circuit converts the state of the counter circuit into different internal state control signals according to the state of the counter circuit when the comparator is reversed.
6. A control detection method using the state detection circuit according to claim 2, comprising:
in the initial state, an enable signal PD is not enabled, Q < n:0> is 0 … … 00, and a default switch SW <0> is opened;
when the enable signal PD is enabled, the counting circuit starts to count, Q < n:0> starts to count from 0 … … 00, every time the counting circuit increases one bit, the switch SW < j > is sequentially opened for one more bit, the current flowing to the outside increases one item I < j >, until the voltage of the IO port is larger than the internal reference voltage VREF, at the moment, the HN signal at the output end of the IO interface circuit becomes low, the counting circuit stops counting, and the detected state signal VM < k:0> is output through the logic conversion circuit; when the count circuit is increased to 1 … … 11 and HN is not yet inverted, the count detection circuit outputs a CNT _ OKN signal, turns off the count circuit, and outputs the current state.
7. A control detection method using the state detection circuit according to claim 3, comprising:
in the initial state, an enable signal PD is not enabled, Q < n:0> is 0 … … 00, and a default switch SW <0> is opened;
when the enable signal PD is enabled, the counting circuit starts to count, Q < n:0> starts to count from 0 … … 00, every time the counting circuit increases one bit, the switch SW < j > is correspondingly opened one bit in sequence, the other switches are closed, the current flowing to the outside is gradually increased until the voltage of the IO port is larger than the internal reference voltage VREF, HN becomes low, the counting circuit stops counting, and the detected state signal VM < k:0> is output through the logic conversion circuit; when the count circuit is increased to 1 … … 11 and HN is not yet inverted, the count detection circuit outputs a CNT _ OKN signal, turns off the count circuit, and outputs the current state.
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| JPH0782070B2 (en) * | 1985-10-30 | 1995-09-06 | 富士通株式会社 | Test circuit |
| JPH02310483A (en) * | 1989-05-25 | 1990-12-26 | Sharp Corp | Test mode setting method for lsi |
| US7245148B2 (en) * | 2005-09-27 | 2007-07-17 | Micrel, Inc. | Power saving method in an integrated circuit programming and control circuit |
| US9000808B2 (en) * | 2010-05-28 | 2015-04-07 | Nxp B.V. | Input pin state detection circuit and method therefor |
| CN103543682B (en) * | 2013-11-06 | 2016-06-08 | 邦彦技术股份有限公司 | Method and device for identifying input state by common IO port |
| CN107748294A (en) * | 2018-01-16 | 2018-03-02 | 长沙韶光半导体有限公司 | A kind of Port detecting and state latching circuit |
| CN110334042A (en) * | 2019-06-28 | 2019-10-15 | 亚世光电股份有限公司 | The method for being identified four kinds of port status by the I/0 mouth of MCU and being distinguished peripheral hardware type |
| CN111474407B (en) * | 2020-06-29 | 2020-11-13 | 上海海栎创微电子有限公司 | Mode selection device with voltage detection priority |
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