CN111919297A - 一种半导体封装结构及其封装方法 - Google Patents

一种半导体封装结构及其封装方法 Download PDF

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Publication number
CN111919297A
CN111919297A CN201880091996.8A CN201880091996A CN111919297A CN 111919297 A CN111919297 A CN 111919297A CN 201880091996 A CN201880091996 A CN 201880091996A CN 111919297 A CN111919297 A CN 111919297A
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China
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chip
layer
substrate
metal layer
semiconductor package
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CN201880091996.8A
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English (en)
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韩梅
李晓勇
滕辉
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN111919297A publication Critical patent/CN111919297A/zh
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种半导体封装结构及其封装方法,该半导体封装结构包括:芯片(20),包括裸片,裸片的第一面上设置有信号源;裸片上与第一面相对的第二面上设置有第一金属层(26),裸片两面的结构通过过孔一一对应连接;基板(10),与芯片(20)层叠设置,且基板(10)上设置有信号管脚,其中,信号管脚通过焊接件与第一金属层(26)连接。在上述技术方案中,通过焊接的方式将芯片(20)与基板(10)电连接,提高了基板(10)与芯片(20)之间的连接强度。此外,通过采用焊接的方式,精度高,便于器件小型化后部件的连接。

Description

PCT国内申请,说明书已公开。

Claims (20)

  1. PCT国内申请,权利要求书已公开。
CN201880091996.8A 2018-03-31 2018-03-31 一种半导体封装结构及其封装方法 Pending CN111919297A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/081489 WO2019183983A1 (zh) 2018-03-31 2018-03-31 一种半导体封装结构及其封装方法

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CN111919297A true CN111919297A (zh) 2020-11-10

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CN (1) CN111919297A (zh)
WO (1) WO2019183983A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050098886A1 (en) * 2003-11-08 2005-05-12 Chippac, Inc. Flip chip interconnection pad layout
US20100072606A1 (en) * 2008-09-25 2010-03-25 Wen-Kun Yang Stacking Package Structure with Chip Embedded Inside and Die Having Through Silicon Via and Method of the same
KR20120091867A (ko) * 2011-02-10 2012-08-20 삼성전자주식회사 CoC 구조의 반도체 패키지 및 그 패키지 제조방법
CN106783765A (zh) * 2017-01-23 2017-05-31 合肥雷诚微电子有限责任公司 一种小型化高散热性的线性功率放大器结构及其制作方法
CN107644867A (zh) * 2017-09-07 2018-01-30 维沃移动通信有限公司 一种PoP封装件及其制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1178288C (zh) * 2001-07-16 2004-12-01 联测科技股份有限公司 薄型化倒装芯片半导体装置的封装方法
KR20080002491A (ko) * 2006-06-30 2008-01-04 주식회사 하이닉스반도체 플립 칩 패키지
US9515017B2 (en) * 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050098886A1 (en) * 2003-11-08 2005-05-12 Chippac, Inc. Flip chip interconnection pad layout
US20100072606A1 (en) * 2008-09-25 2010-03-25 Wen-Kun Yang Stacking Package Structure with Chip Embedded Inside and Die Having Through Silicon Via and Method of the same
KR20120091867A (ko) * 2011-02-10 2012-08-20 삼성전자주식회사 CoC 구조의 반도체 패키지 및 그 패키지 제조방법
CN106783765A (zh) * 2017-01-23 2017-05-31 合肥雷诚微电子有限责任公司 一种小型化高散热性的线性功率放大器结构及其制作方法
CN107644867A (zh) * 2017-09-07 2018-01-30 维沃移动通信有限公司 一种PoP封装件及其制作方法

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