CN111916137A

CN111916137A - OTP memory cell and OTP memory array device

Info

Publication number: CN111916137A
Application number: CN202010780644.2A
Authority: CN
Inventors: 李弦; 贾宬; 冯一飞; ***
Original assignee: Zhuhai Chuangfeixin Technology Co Ltd
Current assignee: Zhuhai Chuangfeixin Technology Co Ltd
Priority date: 2020-08-05
Filing date: 2020-08-05
Publication date: 2020-11-10

Abstract

The present invention provides an OTP memory cell, including: a substrate; the selective MOS transistor comprises a first gate oxide layer and a first gate which are sequentially formed on the substrate, and a first source region and a first drain region which are respectively formed in the substrate at two sides of the first gate; and at least one first-type storage MOS transistor formed on the substrate, wherein each first-type storage MOS transistor is structurally formed with two equivalent capacitors connected in series with the first source region, and the two equivalent capacitors are connected in parallel. Correspondingly, the invention also provides an OTP memory array device.

Description

OTP memory cell and OTP memory array device

Technical Field

The invention relates to the field of design and processing of semiconductor devices, in particular to an OTP memory cell and an OTP memory array device.

Background

In the field of embedded non-volatile memories, One Time Programmable (OTP) memories based on antifuse structures are widely used for analog circuit trimming, key and chip ID storage, SRAM/DRAM redundancy design, RFID, and the like, due to their advantages of high stability, easy programming, and the like.

OTP devices are typically fabricated using a wafer that includes a plurality of isolated minimum transistor regions, each of which includes a plurality of transistors having formed therein a base structure. Further, the minimum transistor region is used as a basis for building a single OTP memory cell, i.e. part or all of the OTP memory cells in the OTP device are built by selecting from the plurality of minimum transistor regions, and finally the OTP memory cells in the plurality of minimum transistor regions jointly form the whole OTP device. Taking a Fin-Field-Effect Transistor (FinFET) wafer implemented by a FinFET process as an example, a minimum Transistor region in the FinFET wafer includes 4 available FinFET transistors, and when an OTP memory cell is constructed, the 4 FinFET transistors are selected to form existing OTP memory cell structures such as 1T1C (1Transistor 1capacitor ), 2T, 3T, and the like.

Therefore, how to fully utilize the minimum transistor area on the wafer to construct a high-performance OTP memory cell becomes one of the research hotspots of the current OTP device.

Disclosure of Invention

It is an object of the present invention to provide an OTP memory cell that can be built with a minimum transistor area on a wafer for various common processes to reduce process complexity and processing cost.

The present invention provides an OTP memory cell, including:

a substrate;

the selective MOS transistor comprises a first gate oxide layer and a first gate which are sequentially formed on the substrate, and a first source region and a first drain region which are respectively formed in the substrate at two sides of the first gate;

and at least one first-type storage MOS transistor formed on the substrate, wherein each first-type storage MOS transistor is structurally formed with two equivalent capacitors connected in series with the first source region, and the two equivalent capacitors are connected in parallel.

According to an aspect of the invention, the OTP memory further includes: at least one second-type memory MOS transistor formed on said substrate, each said second-type memory MOS transistor being structured to form an equivalent capacitor in series with said first source region.

According to another aspect of the present invention, the first-type memory MOS transistor and the second-type memory MOS transistor in the OTP memory cell include: a second gate oxide layer and a second gate electrode sequentially formed on the substrate; and the doped region is formed in the substrate below the second gate oxide layer and is short-circuited with the first source region.

According to another aspect of the invention, the doped region and the first source region are integrated together in the substrate to form a short in the OTP memory cell; or the doped region and the first source region are connected by a contact line.

According to another aspect of the invention, the doped region in the OTP memory cell includes a second drain region formed in the substrate on a side of the second gate adjacent to the first gate.

According to another aspect of the invention, the doped region in the OTP memory cell comprises a second source region and a second drain region respectively formed in the substrate at two sides of the second gate; the second source region and the second drain region are connected by a shorting line.

According to another aspect of the present invention, the OTP memory further includes: the word line is short-circuited with the first grid electrode, the bit line is short-circuited with the first drain region, and the programming line is short-circuited with the second grid electrode.

According to another aspect of the present invention, the first gate and the second gate are arranged in parallel in the OTP memory cell.

According to another aspect of the invention, the thickness of said first gate oxide layer is greater than said second gate oxide layer in the OTP memory cell.

In addition, the present invention also provides an OTP memory array device, including: at least one vertical memory cell queue and at least one horizontal memory cell queue, wherein each of the vertical memory cell array and the horizontal memory cell array comprises a plurality of OTP memory cells as described above.

The OTP memory cell provided by the invention can be constructed by using the minimum transistor area on the wafer of various common processes, fully utilizes the existing structure of the existing wafer, and does not need to adjust the processing process flow of the wafer in a targeted manner, so that the process complexity and the processing cost required for manufacturing the OTP memory cell are obviously reduced, and the performance of the OTP memory cell is superior to that of the traditional OTP memory cells with structures of 1T1C (1 resistor 1capacitor), 2T, 3T and the like.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is a schematic diagram of the structure of the smallest transistor area of a wafer used to fabricate the OTP memory cell of the invention;

FIG. 2 is a schematic diagram of one embodiment of an OTP memory cell in accordance with the invention;

FIG. 3 is a circuit block diagram of the OTP memory cell shown in FIG. 2;

FIG. 4 is another circuit block diagram of the OTP memory cell shown in FIG. 2;

FIG. 5 is a schematic diagram of another embodiment of an OTP memory cell in accordance with the invention;

FIG. 6 is a circuit block diagram of the OTP memory cell shown in FIG. 5;

FIG. 7 is another circuit block diagram of the OTP memory cell shown in FIG. 5;

FIG. 8 is a schematic diagram of a structure of yet another embodiment of an OTP memory cell in accordance with the invention;

FIG. 9 is a circuit configuration diagram of the OTP memory cell shown in FIG. 8;

FIG. 10 is a schematic diagram of a structure of yet another embodiment of an OTP memory cell in accordance with the invention;

FIG. 11 is a circuit configuration diagram of the OTP memory cell shown in FIG. 10;

fig. 12 is a circuit configuration schematic diagram of one embodiment of an OTP memory array device according to the present invention.

The same or similar reference numbers in the drawings identify the same or similar elements.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention. Likewise, the components of the structural diagrams shown in the figures are not drawn to scale, but rather are merely schematic.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a minimum transistor area of a wafer for manufacturing an OTP memory cell of the present invention. As will be understood by those skilled in the art, a plurality of the minimum transistor regions shown in fig. 1 are generally integrated on one wafer, each of the minimum transistor regions includes a plurality of transistors having a basic structure, as shown in fig. 1, and a plurality of gates, such as the gate 10 and the gate 20 in fig. 1, are formed on the substrate 100 of the wafer; doped regions, such as doped region 30 in fig. 1, are formed in substrate 100 on both sides of the gate, and doped region 30 is used to form a source region or a drain region of a transistor. Two adjacent gates 20 may share the doped region 30 between the two gates 20 to construct a transistor corresponding to each gate 20. In the fabrication of an OTP device, generally, for the subsequent processing of the wafer, a suitable transistor is selected from the minimum transistor region to form an OTP memory cell, and taking the minimum transistor region shown in fig. 1 as the minimum transistor region of the wafer in the FinFET process as an example, in general, the transistor in the minimum transistor region disposed at the edge is an isolation device, which is used to isolate adjacent OTP memory cells and prevent the adjacent OTP memory cells from affecting each other, so as to improve the operating performance of the OTP memory cells. More specifically, in fig. 1, the transistor corresponding to the gate 10 is used to serve as the isolation device, and the 4 transistors corresponding to the gate 20 are used to construct the OTP memory cell.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention, and more particularly, the various embodiments described below can be viewed as being formed using the smallest transistor area shown in fig. 1 or a wafer structure similar thereto for further processing. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the applicability of other processes and/or the use of other materials. In addition, the structure of a first feature described below as "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an OTP memory according to an embodiment of the present invention, the OTP memory includes:

a substrate 100;

a selection MOS transistor formed on the substrate 100, the selection MOS transistor including a first gate oxide layer and a first gate 110 sequentially formed on the substrate, and further including a first source region and a first drain region respectively formed in the substrate 100 at both sides of the first gate 110;

at least one first-type memory MOS transistor formed on the substrate 100, the structure of each of said first-type memory MOS transistors forming two equivalent capacitances in series with said first source region.

In particular, the substrate 100 may include various doping configurations according to design requirements known in the art (e.g., P-type substrate or N-type substrate). Substrate 100 may also include other elementary semiconductors, such as germanium, in other embodiments. Alternatively, the substrate 100 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In this embodiment, the substrate 100 is a silicon substrate. Typically, the thickness of the substrate 100 may be, but is not limited to, about several hundred microns, and may be, for example, in the thickness range of 400 μm-800 μm. In an alternative embodiment, an isolation region, such as an STI isolation region, may be formed in the substrate 100 for isolating the OTP memory cell provided in this embodiment from other devices on the substrate 100, the isolation region is made of an insulating material, such as SiO2 or Si3N4, and the width of the isolation region may be determined according to the design requirements of the semiconductor structure.

Since the view angle of the schematic structure shown in fig. 2 is: looking down the substrate 100 from a direction parallel to the gate height of the transistor in the OTP memory cell of the present embodiment, the first gate oxide layer is shielded by the first gate 110, which is not shown in fig. 2, but it can be understood by those skilled in the art that the first gate oxide layer is arranged to isolate the first gate 110 from the substrate 100, i.e. the first gate oxide layer is necessarily arranged between the first gate 110 and the substrate 100, according to the MOS design principle. The material of the first gate oxide layer can be a thermal oxide layer, including silicon oxide or silicon oxynitride, and can also be a high-K dielectric, such as one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, La2O3, ZrO2, LaAlO, or a combination thereof, and the thickness of the first gate oxide layer is related to the design requirements of the OTP memory cell.

In an alternative embodiment, the sidewall of the first gate 110 may form a sidewall spacer (not shown) surrounding the first gate 110, and the sidewall spacer is used for insulating and isolating the first gate 110 from other devices on the substrate. The sidewall spacers may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide and/or other suitable materials, and may have a multi-layer structure with a thickness ranging from about 10nm to about 100nm, for example.

Doped regions

111 and 112 are formed in the substrate 100 on the left and right sides of the gate 110, respectively, and accordingly, the first drain region of the selection MOS transistor is formed in the doped region 111, and the first source region of the selection MOS transistor is formed in the doped region 112, thereby constructing the basic structure of the selection MOS transistor. It will be appreciated by those skilled in the art that the selection MOS transistor is used to provide the gating function of the OTP memory cell, in accordance with the principles of the OTP memory cell.

After the position of the selection MOS transistor on the substrate 100 is determined, other gates and doped regions on the substrate 100 are selected to construct the first-type storage MOS transistor in this embodiment, and the structure of the first-type storage MOS transistor and the connection relationship between the first-type storage MOS transistor and the selection MOS transistor need to satisfy that the structure of each first-type storage MOS transistor forms two equivalent capacitors connected in series with the first source region, and the two equivalent capacitors are connected in parallel. According to the principle of the OTP memory cell, the first-type memory MOS transistor is used to provide 0/1 data storage function of the OTP memory cell, since the structure of the first-type memory MOS transistor provides two equivalent capacitors connected in series with the first source region of the selection MOS transistor, and the two equivalent capacitors are arranged in parallel, which is equivalent to the first-type memory MOS transistor providing two parallel paths connected to the first source region.

Based on the above understanding, it is the key content of the disclosure intended by the embodiment shown in fig. 2 how to use other existing structures on the substrate 100 to construct the first-type memory MOS transistor, on the premise that the selection MOS transistor is formed. As shown in fig. 2, in the present embodiment, another gate on the substrate 100 adjacent to the first gate 110 is selected to construct the first-type memory MOS transistor. A typical first-type memory MOS transistor has a structure comprising: a second gate oxide layer and a second gate electrode 120 sequentially formed on the substrate 100, and a doped region formed in the substrate 100 below the second gate oxide layer, the doped region being shorted with the first source region. Wherein the doped region includes a second source region and a second drain region respectively formed in the substrate 100 at both sides of the second gate electrode 120; the second source region and the second drain region are connected by a shorting line. In particular, reference may be made to the description and parameter selection of the second gate 120 as set forth above for the first gate 110, and to the description and parameter selection of the second gate oxide as set forth above for the first gate oxide; the second drain region is formed in the doped region 112, and the first source region of the selection MOS transistor is also formed in the doped region 112, which is equivalent to the second drain region and the first source region being integrated together in the substrate 100 to form a short circuit, that is, the doped region included in the first-type storage MOS transistor and the first source region are both constructed by using the same doped region 112; the second source region is formed in the doped region 113, and the doped region 112 and the doped region 113 are shorted by the shorting line 160, so that the structure of the first-type memory MOS transistor built depending on the second gate 120 forms two parallel equivalent capacitors connected to the first source region.

In order to implement the functions of programming and reading the OTP memory, as shown in fig. 2, the OTP memory further includes: a word line 150 shorted to the first gate 110, a bit line 140 shorted to the first drain region, and a program line 130 shorted to the second gate 120. In a semiconductor process, a connection line and structures such as a gate and a doped region existing on a substrate are generally formed in different layers, so that typically, the bit line 140 is electrically connected with the doped region 111 through the contact hole 102, and the bit line 140 is short-circuited with the first drain region; the word line 150 is electrically connected with the first gate 110 through the contact hole 101, so that the word line 150 is short-circuited with the first gate 110; the program line 130 is electrically connected to the second gate 120 through the contact hole 105, so that the program line 130 is shorted with the second gate 120. Accordingly, the shorting line 160 is electrically connected to the doped region 112 through the contact hole 103, and is electrically connected to the doped region 113 through the contact hole 104, so as to short the second source region and the second drain region. When the OTP memory cell is programmed, a programming voltage is applied to the second gate 120 through the programming line 130, after the programming, the second gate oxide layer below the second gate 120 is broken down, a conductive path between the second gate 120 and the first source region is formed, and as the second gate oxide layer is broken down, two equivalent capacitors formed by the first type memory MOS transistor are broken down. Meanwhile, when the OTP memory cell is read, the gate current of the first-type memory MOS transistor flows into the substrate 100 through the breakdown point, and because the second source region and the second drain region are shorted, the gate current can simultaneously reach the first source region through the second source electrode and the second drain electrode in parallel, so that the gate current is more easily detected by a sense current amplifier connected to the first source region, and therefore, the read current of the programmed OTP memory cell is effectively increased.

To better illustrate the specific embodiment shown in fig. 2, reference is made to fig. 3, and fig. 3 is a circuit structure diagram of the OTP memory cell shown in fig. 2, where PL refers to a Program Line (Program Line), WL refers to a Word Line (Word Line), BL refers to a bit Line (bit Line), and VSS refers to ground of the substrate 100. Since the circuit diagram shown in fig. 3 is obtained by an equivalent abstract summary of the structural schematic diagram shown in fig. 2, in order to facilitate the comparative understanding of fig. 2 and fig. 3, the end portions of the circuit components appearing in fig. 3 and the corresponding structures have equal potential are labeled by the reference numerals of the corresponding structures in fig. 2, so as to clarify the corresponding relationship between the circuit diagram shown in fig. 3 and the structural schematic diagram shown in fig. 2 (in this context, this approach will also be used for other sets of structural schematic diagrams and circuit structure diagrams, so as to facilitate the comparative understanding of the two, including fig. 6, fig. 7, fig. 9 and fig. 11 in the following text). For example, the MOS transistor on the left side shown in fig. 3 is the selection MOS transistor constructed by using the first gate 110, and the MOS transistor on the right side is the first-type storage MOS transistor constructed by using the second gate 120, where there is an equivalent capacitance between the second gate 120 and the doped region 112, there is an equivalent capacitance between the second gate 120 and the doped region 113, and since the doped region 112 and the doped region 113 are shorted, it is equivalent to two equivalent capacitances on different branches between the second gate 120 and the doped region 112, and the two equivalent capacitances are connected in parallel and in series to the doped region 112, and are equivalent to being connected in series to the first source region of the selection MOS transistor. To further simplify the circuit diagram of fig. 3, after removing the circuit portion of the substrate 100 grounded, the first-type memory MOS transistor is simplified into two equivalent capacitors, as shown in fig. 4, fig. 4 is another circuit block diagram of the OTP memory cell shown in fig. 2, and it can be seen that the structure of the first-type memory MOS transistor essentially provides the capacitors C1 and C2 in series with the first source region of the select MOS transistor, while the capacitors C1 and C2 are in parallel.

It should be noted that, since fig. 2 shows an embodiment in which another gate adjacent to the first gate 110 on the selection substrate 100 is used to construct the first-type memory MOS transistor, it is equivalent to that the selection MOS transistor and the first-type memory MOS transistor are adjacent, which naturally enables the first source region of the selection MOS transistor and the doped region of the first-type memory MOS transistor to be integrated in the doped region 112 of fig. 2. In another embodiment, for example, a gate farther from the first gate 110 is selected to construct the first-type memory MOS transistor, although the circuit structure shown in fig. 3 or fig. 4 can be finally obtained, but at this time, the first source region of the selection MOS transistor and the doped region of the first-type memory MOS transistor are relatively far apart (compared with the embodiment shown in fig. 2), the first source region of the selection MOS transistor and the doped region of the first-type memory MOS transistor cannot be disposed in the same existing doped region on the substrate 100, so in this embodiment, a contact line needs to be disposed, and the first source region of the selection MOS transistor and the doped region of the first-type memory MOS transistor are connected through the contact line. The contact line may be provided with reference to the shorting line 160, in order to connect two doped regions isolated from each other. The embodiment shown in fig. 2, however, is still a preferred embodiment because it makes full use of existing structures on the substrate 100, and saves area,

in other embodiments different from the one shown in fig. 2, the OTP memory cell may further include at least one second-type memory MOS transistor formed on the substrate 100, each second-type memory MOS transistor being configured to form an equivalent capacitor in series with the first source region. Referring to fig. 5, fig. 5 is a schematic structural diagram of another embodiment of the OTP memory according to the invention, which is different from the embodiment shown in fig. 2 in that the OTP memory shown in fig. 5 further includes a typical second-type memory MOS transistor, and the structure includes: a second gate oxide layer and a second gate electrode 121 sequentially formed over the substrate 100; and the doped region is formed in the substrate below the second gate oxide layer and is short-circuited with the first source region, wherein the doped region comprises a second drain region formed in the substrate on one side of the second gate 121 close to the first gate 110. The embodiment shown in fig. 5 can be obtained by modifying the embodiment shown in fig. 2, specifically, the second-type memory MOS transistor is equivalent to only using the second gate 121 and the doped region 113 on the left side thereof to form an equivalent capacitor in series with the first source region, and at this time, in order to access the second gate 121 into the circuit of the OTP memory cell, the contact hole 106 is opened to short the second gate 120 and the second gate 121 through the program line 130. Fig. 5 shows a circuit structure of the OTP memory cell as shown in fig. 6, and as can be seen from fig. 6, after the second gate 121 is shorted with the second gate 120, an equivalent capacitor provided by the second-type memory MOS transistor is connected in series with the first source region of the selection MOS transistor, please continue to refer to fig. 7, fig. 7 is another circuit structure of the OTP memory cell shown in fig. 5, and it can be seen that the MOS transistor at the far right side in fig. 6 provides an equivalent capacitor C3 connected in series with the doped region 112.

As will be understood by those skilled in the art with reference to fig. 2 to 7, whether the first-type memory MOS transistor is provided or the second-type memory MOS transistor is formed on the basis of the first-type memory MOS transistor, this is to increase the number of equivalent capacitors connected in series with the first source region of the selection MOS transistor, which is equivalent to increasing the number of anti-fuse capacitors included in the OTP memory cell, so as to improve the programming reliability of the OTP memory cell. When the OTP memory cell is programmed, the probability of breakdown failure of a plurality of equivalent capacitors is obviously lower than that of one equivalent capacitor, and the probability of programming failure of the OTP memory cell is reduced along with the increase of the number of the equivalent capacitors connected in series with the first source region, which means that the programming reliability of the OTP memory cell is improved.

Of course, in a more preferred embodiment, the number of the first-type memory MOS transistors included in the OTP memory cell is not limited to one, please refer to fig. 8, figure 8 is a schematic diagram of a further embodiment of an OTP memory cell according to the present invention, the embodiment shown in fig. 8 may be obtained by modifying the embodiment shown in fig. 5, specifically, considering that the doped region 114 on the right side of the second gate 121 is also connected into the circuit of the OTP memory cell, by opening the contact hole 107, the doped region 112, the doped region 113 and the doped region 114 are shorted using the same shorting line 160, the circuit structure of the OTP memory cell shown in fig. 8 is shown in fig. 9, and as can be seen from fig. 8 and 9, two first-type memory MOS transistors are respectively constructed in the OTP memory cell by using a second gate 120 and a second gate 122.

Typically, the doped

regions

111, 112, 113 and 114 may be formed by ion implantation with an impurity type consistent with the device type. That is, if the device is NMOS, the impurity type of ion implantation is N type; if the device is a PMOS, the ion implanted impurity type is P-type.

Referring to fig. 5 modified from fig. 2 and a continuous idea of modifying fig. 5 to fig. 8, on the basis of the embodiment shown in fig. 8, other gates and doped regions on the substrate 100 may be accessed continuously, so that the number of the first-type memory MOS transistors and the second-type memory MOS transistors in the OTP memory cell may be increased, referring to fig. 10, fig. 10 is a schematic structural diagram of another embodiment of the OTP memory cell according to the present invention, and the embodiment shown in fig. 10 may be obtained by modifying the embodiment shown in fig. 8, specifically, by forming the contact hole 108, and short-circuiting the second gate 121, and the second gate 122 by the programming line 130, at this time, the second gate 122 is connected into the circuit of the OTP memory cell. Fig. 11 shows a circuit structure of the OTP memory cell shown in fig. 10, when the second gate 122 is shorted with the second gate 120 and the second gate 121, an equivalent capacitor C4 is connected in series to the doped region 112, which is equivalent to adding a new second-type memory MOS transistor in the OTP memory cell based on the embodiment shown in fig. 8. Since the plurality of embodiments appearing in the present specification are described in a progressive manner, the progressive embodiments are intended to illustrate the differences from the previous embodiments, and therefore the same or similar parts between the respective embodiments may be referred to each other.

In current FinFET process wafers, the 1T3C configuration of the OTP memory cell shown in fig. 10 is the embodiment that best utilizes its minimum transistor area, since it contains only 4 transistors available.

It will be understood by those skilled in the art that the embodiments of the OTP memory cells shown in fig. 2-10 can be constructed based on the minimum transistor area divided in the wafer of the current FinFET process, and therefore the OTP memory cells in the above embodiments have the same device area, which is the area of the minimum transistor area divided.

The OTP memory cell provided by the invention can also be implemented on a wafer in a hybrid process, so that any or all of the selection MOS transistor, the first-type memory MOS transistor and the second-type memory MOS transistor are fin-shaped field effect transistors. In the case where a minimum transistor area in a wafer of a certain process may include a plurality of available transistors, the OTP memory cell of the wafer adapted to the process may be implemented in a manner of 1TnC, where n is an integer greater than or equal to 1. In various common processes, two gate lines are arranged in parallel, and accordingly, the first gate and the second gate of the OTP memory cell are arranged in parallel.

In a preferred embodiment, it may be desirable that the gate oxide thickness of the selection MOS transistor in the OTP memory cell is greater than the gate oxide thickness of said first type memory MOS transistor and said second type memory MOS transistor to enhance the electrical performance of the OTP device, and therefore optionally, the thickness of said first gate oxide layer is greater than said second gate oxide layer.

In addition, the present invention also provides an OTP memory array device, including: at least one vertical memory cell array and at least one horizontal memory cell array, wherein each of the vertical memory cell array and the horizontal memory cell array comprises a plurality of OTP memory cells as described above. Referring to fig. 12, fig. 12 is a circuit schematic diagram of an embodiment of an OTP memory array device according to the present invention, which shows a typical connection method of a plurality of OTP memory cells in the OTP memory array device, that is, each of the vertical memory cell queues includes a plurality of OTP memory cells connected to the same bit line BL, and the OTP memory array device has at least two vertical memory cell queues BL0 and BL 1; each of the lateral memory cell arrays includes a plurality of OTP memory cells connected to the same word line WL and program line PL, and the OTP memory array device has at least two lateral memory cell arrays of PL0/WL0 and PL1/WL 1. In this embodiment, the structure of the OTP memory cell is implemented as the same as the embodiment shown in fig. 2, and in more embodiments, the structure of the OTP memory cell may be replaced with the embodiment shown in fig. 5, fig. 8, or fig. 10.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. An OTP memory cell, comprising:

a substrate;

2. The OTP memory cell according to claim 1, wherein said OTP memory cell further comprises:

at least one second-type memory MOS transistor formed on said substrate, each said second-type memory MOS transistor being structured to form an equivalent capacitor in series with said first source region.

3. The OTP memory cell of claim 2 wherein said first-type and second-type memory MOS transistors include:

a second gate oxide layer and a second gate electrode sequentially formed on the substrate;

and the doped region is formed in the substrate below the second gate oxide layer and is short-circuited with the first source region.

4. The OTP memory cell of claim 3 wherein:

the doped region and the first source region are integrated together in the substrate to form a short; or

The doped region is connected with the first source region through a contact line.

5. The OTP memory cell of claim 4 wherein:

the doped region includes a second drain region formed in the substrate on a side of the second gate adjacent to the first gate.

6. The OTP memory cell of claim 4 wherein:

the doped region comprises a second source region and a second drain region which are respectively formed in the substrate on two sides of the second grid electrode;

the second source region and the second drain region are connected by a shorting line.

7. The OTP memory cell according to claim 3, wherein said OTP memory cell further comprises:

the word line is short-circuited with the first grid electrode, the bit line is short-circuited with the first drain region, and the programming line is short-circuited with the second grid electrode.

8. The OTP memory cell of claim 2 wherein:

any one or all of the selection MOS transistor, the first-type storage MOS transistor, and the second-type storage MOS transistor is a fin-shaped field effect transistor.

9. The OTP memory cell of claim 3 wherein:

the first grid and the second grid are arranged in parallel.

10. The OTP memory cell of claim 3 wherein:

the thickness of the first gate oxide layer is larger than that of the second gate oxide layer.

11. An OTP memory array device, comprising:

at least one vertical memory cell array and at least one horizontal memory cell array, wherein each of the vertical memory cell arrays and the horizontal memory cell arrays comprises a plurality of OTP memory cells according to any of claims 1 to 10.