CN111902928A - Integrated circuit with metal interlocking structure - Google Patents

Integrated circuit with metal interlocking structure Download PDF

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Publication number
CN111902928A
CN111902928A CN201880086896.6A CN201880086896A CN111902928A CN 111902928 A CN111902928 A CN 111902928A CN 201880086896 A CN201880086896 A CN 201880086896A CN 111902928 A CN111902928 A CN 111902928A
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China
Prior art keywords
posts
metal
post
array
integrated
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CN201880086896.6A
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Chinese (zh)
Inventor
F·G·赫罗
J·C·王
H·冯
帕尔蒂亚·纳吉布力-***阿巴迪
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HRL Laboratories LLC
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HRL Laboratories LLC
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Publication of CN111902928A publication Critical patent/CN111902928A/en
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Abstract

An integrated component having a metallic interlocking structure; the integrated component includes: an integrated circuit integrated in a substrate having a top surface; the integrated circuit includes a first conductive line; and a first metallic interlock structure comprising a first array of independent metallic posts formed on the top surface and electrically connected to the first conductive lines.

Description

Integrated circuit with metal interlocking structure
[ CROSS-REFERENCE TO RELATED APPLICATIONS ]
Priority of U.S. provisional application No. 62/625313, filed on 1/2/2018 and entitled "INTEGRATED CIRCUIT WITH METALICINTERLOCKING STRUCTURE (integrated circuit with metal interlocking structure"), which is incorporated herein by reference. The present application also claims priority from U.S. application No. 16/213709 entitled "INTEGRATED CIRCUIT WITH METALIC INTERLOCKING STRUCTURE integrated circuit" filed concurrently 2018 on 12, 7 and 7, which is incorporated herein by reference.
[ technical field ] A method for producing a semiconductor device
The present disclosure relates to integrated components, and in particular to an integrated component that includes both an integrated circuit and a metal interlock structure that allows for removable connection of the integrated circuit. The present disclosure also relates to a method of manufacturing such an integrated component having a metallic interlocking structure. The present disclosure also relates to an integrated component assembly comprising two such integrated components removably connected together by an interlocking structure.
[ background of the invention ]
High performance electrical and mechanical contacts and interconnects are highly desirable for system-level integration of multiple semiconductor components and technologies in 3D integration technologies, such as W2W bonding (wafer-to-wafer) or D2W (die-to-wafer) assembly. However, the bonding techniques in the current art typically require heat and/or pressure based processing and are not reworkable (which means that the bond is permanent and cannot be reworked if damaged).
It is known to use interlocking structures to temporarily assemble discrete electronic components on a printed circuit board, for example by providing the printed circuit board with sockets that interlock with and electrically connect pins of the electronic component to the printed circuit board. Such known structures may use spring or bump contacts, or may use the elasticity of their interlocking pins to create temporary electrical contact structures. However, all known interlocking structures suitable for temporary connection are relatively large structures that need to be manufactured separately and then assembled to some electronic components to allow temporary connection of the electronic components to other electronic components having complementary interlocking structures. For example, known interlocking structures include a pin grid array IC package that may be assembled to an IC, wherein the pin grid array package allows for temporary connection of the IC to other ICs mounted on a board equipped with a pin grid array socket.
Some known silicon etched microstructures form MEMS "hook and loop" structures. However, such structures only allow for a single component, and they do not allow for removably connecting integrated circuits. Other known means of producing room temperature bonding require comminuted contact together to produce good electrical contact, but the resulting bond cannot be undone without destroying one or both components.
Reference to the literature
[1] US6543131B 1-Microelectronic joining processes with a temporaryosyccurrence (with a temporarily fixed Microelectronic bonding process).
[2] US6329829B 1-Interconnect and system for creating a temporary electrical connection to semiconductor components (Interconnect and system for making temporary electrical connections to semiconductor components).
[3] US6913476B 2-Temporary, compatible contacts for microelectronic components.
[4] Khumuuang, A.Qhtomo, N.Shibayama, K.Miyake and T.Itoh, "novel controlled polymer Micro-spring contact array for large area over electronics xtile,"2011IEEE 24th International reference on Micro electric mechanical systems, cancer, 2011, pp.296-299 ] -reduced polymer contacts.
[5] Chow, C.Chua, T.Hantschel, K.Van Schuylenberg and D.K.Fork, "Pressure Contact Micro-Springs in Small Pitch Flip Chip Packages," in IEEEtransformations on Components and Packaging Technologies, vol.29, No.4, pp.796-803, Dec.2006-Spring Contact.
[6] Van Bracht, g.set, j.l.herer and n.tolou, "compatible connecting-locking micro mechanism,"2016International Conference on management, Automation and Robotics at Small Scales (MARSS), Paris,2016, pp.1-7, -Comb-finger locking mechanism.
[7] Cheng et al, "lubricating characterisation and Flip-ChipA elementary Reliability," in IEEE Transactions on Components, Packaging and manufacturing Technology, vol.3, No.2pp.187-196, Feb.2013-lubricating contacts Reliability.
[8] Kataoka, S.Kawamura, T.Itoh, T.Suga, K.Ishikawa and H.Honma, "Lowcontact-force and compatible MEMS probe cutting and cutting contact," Technical digest.MEMS 2002IEEE International reference. Fiftent EEInternational reference on Micro electric Mechanical Systems (Cat.No.02CH37266), Las Vegas, NV, USA,2002, pp.364-367-cutting contact.
[9] Itoh, T.T., Kawamura, S.A., Suga, T.A., Kataoka, K., "Development of electrically activated MEMS switching probe card," Proceedings of the 50th IEEE Holm Conference on Electrical Contacts and the 22nd International Conference on Electrical Contacts, Seattle, WA,2004, pp.226-230. -electrically activated Contacts.
[10]E.M.Chow,K.Klein,D.K.Fork,T.Hantschel,C.L.Chua,L.Wong and K.VanSchuylenbergh,"Intermittency study of a stressed-metal micro-spring slidingelectrical contact"Proceedings of the 53rdElectronic Components and technology Conference, New Orleans, LA,2003, pp.1714-1717-Sliding spring contact.
[11] Haemer, J.M., Sitaraman, S.K., Fork, D.K., Chong, F.C., Mok, S., Smith, D.L., Swiatowic, F, "Flexible Micro-Spring Interconnects for High Performance combining," Proceedings of the Electronic Components and Technology Conference,2000, pp.1157-1163 "-Spring contacts.
[12] Han, E.L.Weiss and M.L.Reed, "Design and modeling of a Micromechanical Surface Bonding System," International Conference on solid-State Sensors and actors, San Francisco, CA,1991, pp.974-977-MEMS Velcro (MEMS magic tape).
[13]H.Han,L.E.Weiss and M.L.Reed,'‘Micromechanical Velcro,"in Journalof Microelectromechanical Systems,vol.1,no.1,pp.37-43,March1992.-MEM Velcro。
[14] M.S.Bakir, H.A.Reed, P.A.Kohl, K.P.Martin and J.D.Meind, "Sea of leaves high-density compliant water-level packaging Technology,"52 and electronic Components and Technology Conference 2002, (Cat.No.02CH37345), SanDiego, CA, USA,2002, pp.1087-1094. -Large scale high density springs.
There remains a need for an easy method of fabricating interlocking structures that allows reworkable conductive die bonding at fine pitch, low force and low temperature.
[ summary of the invention ]
The present disclosure discloses a metallic interlock structure that provides fine pitch scalable, reworkable conductive die bonding requiring low force and low interlock processing temperatures.
The present disclosure discloses a nano/micro scale conductive interlock structure that can be fabricated using a novel combination of standard IC fabrication processing steps, 1) is low resistance, 2) is mechanically compliant, 3) allows some circuit pads (or bumps) to be mechanically and electrically "bonded" without heat and with minimal applied force (1/5 for standard thermo-compression bonding), and 4) can be reworked or reused multiple times.
Embodiments of interlocking structures according to the present disclosure include microstructures arranged in an array to form conductive interlocking structures that can be interlocked with corresponding (e.g., identical or complementary) conductive interlocking structures according to the present disclosure. Thus, the present disclosure effectively allows for electrically and mechanically bonding together two surfaces, each provided with one of the electrically conductive interlocking structures. According to the present disclosure, two interlock structures "bonding" together can be performed at room temperature and allows electrical contact to be made between two integrated circuits that are each connected to one of the conductive interlock structures. Further, by pulling the two interlocking structures apart, the bond can be physically removed in a non-destructive manner, and the two integrated circuits can be connected, for example, to other integrated circuits having compatible conductive interlocking structures. This possibility of reworking (debonding, rebonding) an integrated component having an integrated circuit with a conductive interlock structure according to the present disclosure is useful, for example, for testing and filtering off-specification components. The bond between two interlocking structures according to the present disclosure may be reworkable or permanent depending on the frictional force that the interlocking structures exert on each other.
Embodiments of the present disclosure provide an integrated component having a metallic interlocking structure; the integrated component has: an integrated circuit integrated in a substrate having a top surface; the integrated circuit includes a first conductive line; and a first metallic interlocking structure comprising a first array of independent metallic posts formed on the top surface.
According to an embodiment of the present disclosure, the independent metal pillar is electrically connected to the first wire.
According to an embodiment of the present disclosure, the first array of independent metal posts is arranged such that introducing a post along the axis of the post between the posts of the second array of independent metal posts having a size of the same order of magnitude as the first array brings the posts of both arrays into frictional contact and temporarily attaches the first and second arrays.
According to an embodiment of the present disclosure, the individual metal posts each have a diameter of less than two microns and are at most 10 microns apart (center-to-center) from each other. According to an embodiment of the present disclosure, the individual metal posts each have a diameter of less than one micron and are at most 5 microns apart (center-to-center) from each other.
According to an embodiment of the present disclosure, at least one of the individual metal posts has a top portion having a dimension perpendicular to the axis of the post that is larger than the base of the post.
According to an embodiment of the present disclosure, the horizontal metal beam connects the tops of at least two adjacent independent metal pillars.
According to an embodiment of the present disclosure, an integrated component includes: a second conductive line different from the first conductive line; and a second metallic interlocking structure comprising a second array of independent metallic posts formed on the top surface and electrically connected to the second conductive lines.
Other embodiments of the present disclosure provide an integrated component assembly comprising: the first integrated component as described above; and a second integrated component as described above, the second integrated component being arranged upside down such that the first metallic interlocking structure of the second integrated component interlocks with the first metallic interlocking structure of the first integrated component.
According to an embodiment of the present disclosure, friction between the length of the post of the second integrated component and the length of the post of the first integrated component maintains the first and second integrated components removably attached to each other.
According to an embodiment of the present disclosure, at least some of the pillars of one of the first and second integrated components have a top portion larger than a base portion thereof; and friction of the larger top with the length of the post of the other of the first and second integrated components maintains the first and second integrated components removably attached to each other.
Other embodiments of the present disclosure provide a method of manufacturing an integrated component having a metallic interlocking structure; the method comprises the following steps: providing an integrated component having a substrate with a top surface and having an integrated circuit integrated in the substrate, the integrated circuit comprising a first conductive line; and forming a first metal interlock structure comprising a first array of independent metal posts on the top surface.
According to an embodiment of the present disclosure, the forming a first metal interlock structure comprising a first array of independent metal posts on the top surface comprises: electrically connecting the metal post to the first wire.
According to an embodiment of the present disclosure, the method includes: the first array of individual metal posts is sized such that introducing the posts along the axis of the posts between the posts of a second array of individual metal posts having a size of the same order of magnitude as the first array brings the posts of both arrays into frictional contact and temporarily attaches the first and second arrays.
According to an embodiment of the present disclosure, the method includes: forming the independent metal posts, wherein the diameter of each metal post is less than two microns; and comprises: forming the free-standing metal pillars at most 10 microns apart from each other. According to an embodiment of the present disclosure, the method includes: forming the individual metal posts, each metal post having a diameter of less than one micron; and comprises: forming the free-standing metal pillars at most 5 microns from each other.
According to an embodiment of the present disclosure, the method includes: forming at least one freestanding metal post having a top portion with a dimension perpendicular to the axis of the post that is larger than the base of the post.
According to an embodiment of the present disclosure, the method includes: forming a horizontal metal beam connecting the tops of at least two adjacent independent metal columns.
According to an embodiment of the present disclosure, the integrated circuit includes a second conductive line; the method further comprises the following steps: forming a second metallic interlocking structure comprising a second array of independent metallic posts on the top surface and electrically connected to the second conductive lines.
According to an embodiment of the present disclosure, the forming a first metal interlock structure on the top surface comprising a first array of independent metal posts electrically connected to the first conductive line provides: depositing a precursor metal layer on the top surface electrically connected to the first conductive line; electroplating the precursor metal layer; forming a post mask layer having a recess where a post is to be formed on the electroplated precursor metal layer; filling the concave portion of the mask by electroplating; and removing the pillar mask.
According to an embodiment of the disclosure, the method further comprises: forming a post top mask having a recess with a diameter larger than that of the post after filling the recess of the mask by electroplating and before removing the post mask; depositing a top-of-pillar precursor metal layer at the bottom of the recess of the top-of-pillar mask; electroplating the pre-pillar metal layer; filling the recesses of the pillar top mask by electroplating; and removing the post top mask.
According to an embodiment of the present disclosure, the method includes: the metal interlock structure is fabricated using steps compatible with subsequent processing steps used to fabricate the integrated circuit.
While specific advantages have been enumerated above, various embodiments may include none, some, or all of the enumerated advantages. In addition, other technical advantages may become apparent to one of ordinary skill in the art upon review of the following drawings and description.
[ description of the drawings ]
For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numbers represent like parts:
fig. 1 schematically illustrates an integrated component having an integrated circuit with a metal interlock structure in accordance with an embodiment of the disclosure.
Fig. 2A and 2B illustrate the interaction of two interlocking structures according to an embodiment of the present disclosure.
FIG. 3 illustrates an embodiment of an interlock structure according to the present disclosure.
FIG. 4 illustrates an embodiment of an interlock structure according to the present disclosure.
Fig. 5 illustrates the interaction of two interlocking structures according to an embodiment of the present disclosure.
Fig. 6A to 6C are pictures of an interlock structure according to three embodiments of the present disclosure.
Fig. 7 is a photograph of an interlock structure according to an embodiment of the present disclosure.
Fig. 8 is a picture of an interlock structure according to an embodiment of the present disclosure.
Fig. 9 is a photograph of an interlock structure according to an embodiment of the present disclosure.
Fig. 10 is a photograph of an interlock structure according to an embodiment of the present disclosure.
Fig. 11 is a photograph of an interlock structure according to an embodiment of the present disclosure.
Fig. 12 is a photograph of an interlock structure according to an embodiment of the present disclosure.
Fig. 13 is a picture of a test apparatus of a chip (chip) having an interlock structure according to an embodiment of the present disclosure.
Fig. 14A to 14F are pictures illustrating an exemplary use of a chip having an interlock structure according to an embodiment of the present disclosure.
Fig. 15 is a schematic diagram illustrating a connection resistance of a chip having an interlock structure according to an embodiment of the present disclosure.
Fig. 16 is a schematic diagram illustrating the forces required to interlock interlocking structures according to an embodiment of the present disclosure.
Fig. 17 is a schematic diagram comparing the interlocking force of an interlocking structure according to an embodiment of the disclosure with the bonding force required by other structures.
Fig. 18A-18F illustrate a process for manufacturing a component having an interlocking structure according to an embodiment of the present disclosure.
Fig. 19A-19I illustrate a process for manufacturing a component having an interlocking structure according to an embodiment of the present disclosure.
[ EXAMPLES ]
It should be understood at the outset that although example embodiments are illustrated below, the present techniques may be implemented using any number of techniques, whether currently known or not. The present techniques should in no way be limited to the example implementations, drawings, and techniques illustrated below. Additionally, the drawings are not necessarily drawn to scale.
The purpose of the metal interlock structure according to the present disclosure is to enable high performance interconnection between two chips (chips), or between a chip and a board (board) or wafer (wafer), while still allowing chip replacement (typically 2 functions that are mutually exclusive). According to embodiments of the present disclosure, metal interlocking structures are fabricated with processes compatible with integrated circuit fabrication and therefore can be easily implemented on semiconductor wafers, particularly without degrading the original circuit performance.
FIG. 1 schematically illustrates an integrated component 10 having a metallic interlocking structure according to an embodiment of the disclosure; the integrated component includes an integrated circuit 12 integrated in a substrate 14 having a top surface 16; integrated circuit 12 includes a first conductive line 18. As schematically illustrated in fig. 1, the integrated circuit 12 may include a block 20 of integrated active or passive electronic components having several (3 shown) input/ output conductors 18, 22, 24. Integrated circuit 12 may also include a via 26 connecting top surface 16 of substrate 14 to a bottom surface (not shown); the via 26 is connected to the block 20 by a wire 24. According to an embodiment of the present disclosure, component 10 includes a first metal interlock structure 28 that includes a first array of individual metal posts 30 formed on top surface 16 of substrate 14, and each individual metal post is electrically connected to the first conductive line.
According to an embodiment of the present disclosure, each individual metal post 30 is a cylinder with a circular base. The base of the cylinder of each post 30 may also be oval or have any desired polygonal shape. According to an embodiment of the present disclosure, the diameter of the cylinder (or more generally, the maximum transverse dimension of the column) is less than the height of the respective column, at least one fifth of the height of the respective column 30.
According to an embodiment of the present disclosure, each post 30 has a diameter of less than two microns, and the posts are at most 10 microns apart from each other. According to an embodiment of the present disclosure, the pillars 30 of the array 28 are distant from each other such that another pillar of another array of similarly sized pillars can only be introduced therebetween by frictional contact with the pillars 30. For example, array 28 of individual metal posts 30 may be sized such that introducing the posts 30 between posts of a second identical array of individual metal posts (not shown) along the post axes will bring the posts of both arrays into frictional contact, thereby temporarily attaching the first and second arrays.
According to an embodiment of the present disclosure, integrated circuit 12 includes: a second conductive line 22 different from the first conductive line 18; and a second metal interlock structure 32 comprising a second array of independent metal studs 34 formed on top surface 16 of substrate 14 and electrically connected to second conductive lines 22, any number of I/O pads of integrated circuit 12 may be connected to an array of studs such as shown in arrays 28 or 32 in accordance with embodiments of the present disclosure.
As detailed below, individual arrays of posts, such as 28, 32, may be used to implement removable connections to corresponding arrays formed on a substrate to which the integrated component 10 is to be attached, which are themselves electrically connected to circuitry on the substrate to which the integrated circuit 12 is to be connected. As detailed below, an array of posts, such as 28, 32, according to the present disclosure may be repeatedly interlocked with and unlocked from a corresponding array of posts, wherein frictional interaction of the array 28, 32 interlocked with the array of substrates maintains the member 10 attached to the substrates, thereby advantageously replacing the use of non-permanent conductive glue.
In accordance with embodiments of the present disclosure, the component 10 may additionally or alternatively include one or more additional arrays 36, 38, e.g., structurally identical to any of the arrays 28, 32 but not connected to the integrated circuit 12. The unconnected arrays 36, 38 may be arranged to interlock with corresponding unconnected arrays (not shown) on the substrate to which the component 10 is to be attached, thereby assisting in securing the component 10 to the substrate by providing an additional frictional interlock between the component and the substrate. The unconnected arrays 36, 38 may also allow for better control of the growth of the other arrays 28, 32 by electroplating (described in detail below). The inventors have noted that when growing only a small number of metal interlock structures, the growth of the metal interlock structures may be too fast and difficult to control if the current source used is not accurate enough to deliver only the correct amount of current. Growing additional metal interconnect structures helps to reduce the current in the respective metal interconnect structures, thereby making the growth of the metal interconnect structures by electroplating more easily controllable.
There are many exemplary applications for components with integrated interlocking structures according to the present disclosure:
for example, microfabricated 3D arrays featuring tiled architectures (tiled architectures) in which multiple chips are bonded side-by-side, tiling-like to form large arrays. If any individual chips in the array are a) misaligned, b) poorly performing, and/or c) degraded over time, they may be removed and replaced if they are attached to the array using a metallic interlock structure according to the present disclosure. In contrast, tiled arrays currently assembled with prior art thermal compression bonding are not modifiable. Any defects/degradation will result in loss of the entire array. For such applications, the metal interlock structure according to the present disclosure provides significant cost savings with negligible interconnect performance trade-off.
In conventional multi-chip modules (e.g., 10GHz transceiver modules for phased array applications), multiple chips from different technologies are typically "die-attached" to a metal heat spreader/backplane. Because the individual modules are very expensive, the integrators use reworkable glue to attach the chips. These glues (e.g., silver epoxy) have low thermal conductivity, but allow removal of the chip in the event of a chip failure. So that the module chip can be replaced while the entire module is maintained when the module chip fails. The metal interlocking structures according to the present disclosure advantageously replace and are superior to these conductive glues, which provide conductive bonding performance comparable to that from permanent materials (e.g., eutectic solder) while being removable as detailed below.
The metal interlock structure according to the present disclosure may enable high performance testing of chips on an advanced test board/wafer by temporarily bonding the chips having the structure to the test board/wafer.
In addition, the inventors have shown that metal interlocking structures according to the present disclosure can also be used to permanently bond chips using room temperature processing at low forces. This is a significant improvement over known thermal compression bonding (au-au) or high force room temperature indium bump processing.
The metallic interlocking structures according to the present disclosure do not require elevated temperatures to operate (no mismatch between materials with different coefficients of thermal expansion) and do not require high forces (so one can make very large area bonds and assemblies).
Metal interlock structures according to embodiments of the present disclosure allow, for example, the establishment of temporary electrical contacts for rapid prototyping, testing, and technology integration that would previously require labor intensive processing and would not be reworkable/non-temporary or would have poor electrical conductivity.
The metallic interlocking structures according to the present disclosure may also be scaled to produce bonding sites on the order of 5 microns by 5 microns, where the pitch of the bonding sites, i.e., the center-to-center distance, may be as low as 10 microns. In general, the center-to-center distance between two bonding sites along a given direction may be twice the size of the bonding sites in the same direction; or may be larger; or may be lower down to the same size as the bonding sites in the same direction.
The metal interlock structure according to the present disclosure allows for reduced repair costs because components in a system-in-package can be replaced when the components are defective or become defective. Also, if the part under test is deemed good, additional force may be applied to make the bond permanent. Such additional force may, for example, push the penetrating posts deeper, thereby increasing the contact surface of the respective posts, until the friction is so high that the component cannot be retrieved without being damaged.
Use in an infrared Focal Plane Array (FPA): the metal interlocking structures according to the present disclosure can replace indium bonding and enable tighter pitches and lower costs for large-scale FPAs, which can enable higher resolution images with higher yields (> 5 x improvement).
Advantageously, the metal interlock structure according to the present disclosure also allows for absorbing any Coefficient of Thermal Expansion (CTE) mismatch between the chip and the substrate to which the chip is attached during system operation, thereby reducing the chance of damage due to such mismatch due to bond compliance.
Application in millimeter wavelength phased arrays: the metal interlock structure according to the present disclosure is an excellent method of flip-chip bonding (integration of SiGe chip with GaN PA or LNA) that allows for a reduction in the cost associated with rework/assembly (cost reduction by >5 times due to rework capability).
Applications of photonic or MEMS devices integrated with silicon CMOS electronics: metal interlocking structures according to the present disclosure can significantly reduce assembly and rework costs, for example, for chip-scale LIDAR, such as those required for autopilots and UAVs.
Fig. 2A and 2B illustrate the interaction of two interlocking structures including a post 40 belonging to an array of posts attached to a substrate (not shown) toward the bottom of fig. 2A, and a post 42 belonging to an array attached to another substrate (not shown) toward the top of fig. 2A, in accordance with an embodiment of the present disclosure. Thus, the orientation of the posts 42 with respect to the posts 40 and the array shown in FIG. 1 can be said to be reversed. The column array illustrated in fig. 1 schematically shows uniform cylindrical columns. However, according to embodiments of the present disclosure, the posts may be non-uniform along their height. For example, the post may have a uniform cross-section along most of its height up to the head/top of the post portion of different cross-section. The bottom of fig. 2A illustrates the posts 40 having a uniform cross-section up to a larger cross-sectional head 40', thereby giving each post a "pin" shape. According to an embodiment of the present disclosure, the top of the pillar may have a parallelepiped shape spreading in a direction perpendicular to the axis of the pillar. According to embodiments of the present disclosure, the tops of two adjacent pillars may be joined so as to form a "ring" structure. The top of fig. 2A shows the tops 42' of two adjacent pillars 42 of an array according to an embodiment of the present disclosure, which are joined to form a "ring" structure, which are arranged upside down and introduced between the pillars 40 in frictional contact.
Fig. 2B illustrates a top view of posts 40 and 42 and top 42'. According to an embodiment and as illustrated, the top 42' may have a size slightly smaller than the distance between two adjacent posts 40. According to an embodiment, the top portion 40' (not shown in fig. 2B) may be sized such that the top portion 42' may pass marginally (barley) between two adjacent top portions 40 '.
Fig. 3 illustrates an embodiment of an interlock structure according to the present disclosure, comprising posts 44 having cuboid tops 44', arranged such that: the tops 44' of two adjacent columns 44 are joined to form a "ring" structure; and at least one top portion 44 'is flared in both directions from the post 44 to form a "hook" structure 44 on one side of the "loop" structure formed by the two posts 44 and their associated top portions 44'.
Fig. 4 illustrates an embodiment of an interlock structure according to the present disclosure that includes posts 46 having rectangular prismatic/parallelepiped tops 46 'that all open in the same direction perpendicular to the axis of the posts 46, such that each pair of posts 46 and their tops 46' form a "hook" structure.
Fig. 5 illustrates the interaction of two interlocking structures according to an embodiment of the present disclosure. The bottom of fig. 5 shows "pin" shaped posts 40, each having a substantially spherical top 40' with a diameter larger than the cross-section of the post, which interlocks with an inverted array of uniform posts 30 such as illustrated in fig. 1. Pillars 30 may have the same areal density as pillars 40, or they may have a lesser areal density, so long as the introduction of pillars of one array between pillars of another array creates frictional contact between the pillars (or between the tops of pillars of one array and pillars of another array). According to embodiments of the present disclosure, posts 30 may have a different diameter and spacing than posts 40, so long as the "frictional contact" constraint is satisfied. Moreover, neither the array comprising pillars 30 nor the array comprising pillars 40 need be completely filled.
Fig. 6A-6C show SEM micrographs of fabricated metallic interlocking structures according to the present disclosure, in which horizontal elements are formed between the tops of adjacent pillars, thereby forming an array of rings. Such an array of rings is provided, for example, for frictionally engaging an array of posts (such as simple posts in fig. 1; or pin-headed posts in fig. 5; or double-pin-headed posts as described in detail below; or posts with a convex middle portion as described in detail below). In the illustrated example, the pillars have a width/diameter of 0.5 to 4 microns and a pillar spacing ranging from < 2 microns to 10 microns (the spacing is measured between the centers of two consecutive pillars, the minimum spacing of the pillars of diameter d being 2d, preferably slightly higher than 2 d). For example, the posts may have a diameter of 1 micron with a pitch of 2 microns. As shown in fig. 6A and 6B, the tops of the posts forming adjacent loops may be connected together to form a series of loops attached together along straight or zig-zag lines. As shown in fig. 6C, the top-coupled pillars may be arranged to form an array of adjacent individual rings.
Fig. 7 shows an SEM micrograph of an array of pillars, wherein the pillars have a substantially constant diameter and are arranged along a regular array of groups of four pillars, in accordance with an embodiment of the present disclosure.
Fig. 8 shows an SEM micrograph of an array of pillars, wherein the pillars have a substantially constant diameter and are arranged along a regular array of pillars, substantially as illustrated in fig. 1, according to an embodiment of the present disclosure.
Fig. 9 shows an SEM micrograph of an array of pillars according to an embodiment of the present disclosure, such as illustrated in fig. 4, where horizontal elements wider than the pillars may be formed at the top of one or more pillars, e.g., horizontal elements that are spread out in a given direction from the top of each pillar so as to form a "hook" shape. According to embodiments of the present disclosure, the "hook" shape of the interlocking structure may be arranged to cooperate with a "loop" shaped interlocking structure, as exemplified in fig. 3 or fig. 6A-6C, for example.
Fig. 10 shows an SEM micrograph of an array of fabricated metallic interlocking structures or posts according to the present disclosure, wherein each post comprises a pin-headed post formed on top of the pin-headed post.
Fig. 11 shows an SEM micrograph of an array of pillars according to the present disclosure, wherein each pillar includes a convex middle portion.
Fig. 12 shows an SEM micrograph of a fabricated metallic interlock structure according to the present disclosure, wherein each post is substantially a simple cylinder. Fig. 12 shows that an array of pillars according to an embodiment of the present disclosure may include a large number of pillars, for example, 70 × 70 pillars with a 25 μm pitch, which form a 1.75 × 1.75mm array.
Fig. 13 is a photograph of a test apparatus of an integrated component 10 having an interlocking structure according to an embodiment of the present disclosure. A silicon wafer 50 is fabricated that includes a test integrated circuit having a plurality of integrated interlocking structures arranged to interlock with an array of posts (e.g., 28, 32, 36, 38) of the inverted integrated component 10 as illustrated in fig. 1. The test wafer 50 may be described as a wafer comprising a plurality of integrated components as shown in fig. 1 unsingulated after fabrication. The component 10 is then attached to the wafer by positioning the component over the area to which the component is to be attached, and the component is gently depressed so that the array of posts of the component interpenetrate the array of posts of the wafer, and frictional contact between the posts of the array maintains the component attached to the wafer. For testing, a further test chip 52, identical to the component 10 but having a known thermocompression bonding pad instead of an array of pillars, is bonded with thermocompression to a further part of the test wafer, which is also provided with a known thermocompression bonding pad instead of an array of pillars.
Embodiments of the present disclosure also include an integrated component assembly as illustrated in fig. 13, comprising: a first integrated component as shown, for example, in fig. 1; and a second integrated component 10 as claimed in claim 1, the second integrated component being arranged upside down such that the metallic interlocking structure of the second integrated component interlocks with the metallic interlocking structure of the first integrated component.
Fig. 14A-14F are photographs of an exemplary use of the test wafer 50 of fig. 13. Fig. 14A shows that all the test parts 10 are placed on the wafer 50 with tweezers and the wafer 50 after attachment is lightly pressed. Fig. 14B shows the user shaking the wafer 50 without causing the test parts to fall. At this particular moment, the electrical connection of the wafer to the respective component 10 is tested, as exemplified below. Fig. 14C-14E illustrate the user removing the component 10, thereby demonstrating at least the removability of the component according to embodiments of the present disclosure after assembling the component to the wafer and verifying the component-to-wafer electrical connections. Fig. 14F shows that the user checks that the thermocompression bonding member cannot be separated from the wafer.
Fig. 15 is a schematic diagram illustrating an example of DC resistance measurements (data labeled "NEA chips") from the test structure shown in fig. 13. Resistance of a thermo-compression assembly of two thermo-compression pads (using standard Au metal pads and at 250 ℃ and high force (e.g., 30 Kg/mm)2) Thermal compression bonding for 3 minutes; data labeled "reference chip") was 35% lower than the resistance of the interlocking array of metal posts according to the present disclosure of a chip assembled using metal interlocking structures according to the present disclosure. Further, testing indicated that components assembled using metal interlocking structures according to the present disclosure showed high bonding yields (> 200 bonded solder joints)A disk without any shorts (i.e., two pads that should not be connected are connected) or opens (i.e., two pads that should not be connected are not connected).
FIG. 16 is a schematic diagram showing 4-point probe resistance measurements made at various forces and temperatures. Measurements were performed at room temperature and on structures bonded using different levels of normalized force. Bonding structures bonded according to embodiments of the present disclosure at room temperature; thermal compression bonding of the reference structure was performed at 250 ℃. The data was normalized for the thermally compression attached reference chip (labeled "NEA treatment"). Tests have shown that chips assembled using metal interlocking structures according to the present disclosure enable the use of only 20% of the bonding force required for known thermal compression processes, no heat, and only an increase in bond resistance of about 30% of the resistance of known thermal compression processes.
Fig. 17 is a schematic diagram comparing the interlocking force of an interlocking structure according to an embodiment of the present disclosure with the bonding force required by other structures. Fig. 17 is a graph of normalized resistance versus normalized force applied during bonding for an interlock structure and a thermocompression bonding structure in accordance with an embodiment of the present disclosure. As illustrated in fig. 17: 1/Low force interlocking components of a carrier circuit according to the present disclosure can be reworked (unbaked or unblanked); 2/the high force interlocking components of the carrier circuit according to the present disclosure cannot be manually reworked (unbaked or unbocked); 3/reused (re-interlocked) chips carrying circuits according to the present disclosure show negligible resistive degradation (< 10%); and 4/bonded reworkable components carrying electrical circuits according to the present disclosure can then be permanently bonded/re-interlocked by applying a greater interlocking force (useful for functional testing prior to final assembly).
Fig. 18A to 18F illustrate a process of manufacturing a component having an interlocking structure according to an embodiment of the present disclosure. These figures specifically illustrate processing on a Si substrate 14, but it can be applied to virtually any technology, as metal layers can be interchanged with other metals.
Fig. 18A illustrates a step including providing a substrate 14 having a top surface 16, wherein an integrated circuit 12 (not shown) is integrated in the substrate 14 below an insulating dielectric top layer 16', and wherein conductive lines 18, 22 connected to the integrated circuit 12 are formed on top of the dielectric layer 16'. Note that the wires 18, 22 are illustrated as being parallel to the surface of the substrate 14. According to embodiments of the present disclosure, at least one of the wires 18, 22 may alternatively include a via extending from the circuit 12 into the substrate 14 perpendicular to the surface of the substrate 14. According to embodiments of the present description, at least one of the wires 18, 22 may alternatively comprise a mix of conductors extending into the substrate 14 parallel and perpendicular to the surface of the substrate 14.
Fig. 18B illustrates a procedure including the following processes: depositing a precursor (precursor) metal layer 60 electrically connected to the conductive lines 18 and 22 on the top surface 16 of the substrate 14; a thicker layer of plated metal 62 is then formed on top of the precursor layer 60. The precursor layer 60 may be formed by metal evaporation or sputtering. It may comprise Ti/Au. According to an embodiment of the present disclosure, both layers 60 and 62 completely cover an area of surface 16.
Fig. 18C illustrates a step including forming a pillar mask layer 64 on the plated metal layer 62 having recesses 66 in which pillars 30, 34 are to be formed. The mask 64 may be implemented by high aspect ratio (high aspect ratio) patterning using a photoresist layer, which allows the creation of metal pillars and pads (e.g., aspect ratios of at least 5:1, feature diameters < 2 microns and/or pitches of no more than 10 μm, pitch measured as the pillar center to pillar center distance). According to embodiments of the present disclosure, the diameter and pitch of the pillars may be such that a second array of pillars may be introduced between the pillars of the first array, such that friction between the pillars of the first and second arrays maintains the two arrays joined together, and such that a predetermined strength needs to be applied to separate the two arrays from each other. This predetermined strength may be comparable to the strength required to separate the chip package from the socket. This predetermined strength must be sufficient to prevent the array from being separated by forces due to the acceleration expected of the array in use (e.g. due to the device using the array falling on the ground).
Fig. 18D illustrates a step including filling the recesses 66 of the mask 64 by electroplating (e.g., using Au & Ni, or Pt and Cu) to form the pillars 30, 34. Embodiments of the present disclosure include forming only narrow pillars or only wide pillars or any mixture of wide and narrow pillars.
FIG. 18E illustrates a further step including the removal of the photoresist mask 64; and fig. 18F illustrates further steps including: the plated films 60 and 62 are removed as necessary (e.g., by protecting the pads with resist, removing the metal between the pads with a dry or wet etching technique, and then removing the resist) to isolate the respective pillar arrays from each other; maintaining the pillars 30 of the array 28 in contact with the conductive lines 18; and maintaining pillars 34 of array 32 in contact with wires 22 and isolating pillars (not shown) of arrays 36, 38 (not shown) from other conductors on surface 16.
Advantageously, forming the pillars by electroplating allows the formation of metal pillars having very high aspect ratios (e.g., at least 5 times as high as their width). It should be understood that the posts may be uniform, for example as illustrated in fig. 1, 7, 8, 12. The top of the post is optionally wider than the base of the post. It should also be noted that more than two plating masks may be used. For example, as illustrated in fig. 11, an additional pillar mask may be used on top of the pillar top mask to form a pillar with a middle portion wider than the base and top portions. Also, for example, as illustrated in fig. 10, an additional post top mask may be used to form "pin head" posts on top of the "pin head" posts.
Advantageously, the fabrication steps illustrated in fig. 18A-18E may be performed using processing steps (metal layer sputtering, metal layer plating, mask formation and removal, partial metal etching) compatible with back-end-of-line processing for fabricating integrated circuits. Thus, metal interconnect structures including arrays of micron or sub-micron (e.g., 800nm) level pillars according to embodiments of the present disclosure may be formed directly on the top surface of an integrated circuit chip as a final step in the fabrication process of the integrated circuit chip to allow flip-chip assembly of the chip.
Fig. 19A-19I illustrate a manufacturing process of a component having an interlocking structure, wherein the post does not have a uniform diameter along its entire length, according to an embodiment of the present disclosure. Fig. 19A to 19D are substantially the same as fig. 18A to 18D in that they allow an array of pillars 30, 34 to be formed on the surface 16 of the substrate 14, each pillar having a constant diameter, in contact with both of the wires 18 and 22.
Fig. 19E illustrates a step including forming a post top mask 68 having a recess 70 in which a post top wider than the post base/diameter is to be formed. As described above, a post top wider than the post diameter may be used to form a "hook" shaped post as well as a "pin" shaped post, or to join two posts to form a "loop" shape.
Fig. 19F illustrates a step that includes depositing a post top precursor metal layer 72 at the bottom of the recess 70 of the post top mask 68, for example, by depositing an evaporation coating (e.g., using Ti/Au). A first resist mold may be used to define the plating area.
Fig. 19G illustrates a step including forming the pillar tops 74, 76 by electroplating (e.g., using Au & Ni, or Pt and Cu; e.g., through an auxiliary resist mold) on top of the pillar top precursor metal layer 72 in the recess 70. As illustrated, the post tops 74 may extend from the top of the single post (30 in the figure) parallel to the surface of the substrate 14 to form a "hook" structure. As also illustrated, the post tops 76 may alternatively extend parallel to the surface of the substrate 14 from the top of at least two posts (34 in the figures) to form a "ring" structure. According to embodiments of the present disclosure, a post array comprising "hook" structures may be provided to interlock with a post array comprising "loop" structures. According to embodiments of the present disclosure, a post array comprising "hook" or "loop" structures may be provided to interlock with a post array comprising "pin" structures as described above.
Fig. 19H illustrates a step including removing all the photoresist masks, and fig. 19I illustrates a step including removing the plating films 60 and 62 as necessary to isolate the respective pillar arrays from each other.
Note that the cross-section of the posts may be circular, square, rectangular, oval, triangular, or have any shape suitable to cause the first array of posts according to embodiments of the present disclosure to form a predetermined friction with the interlocked second array of posts according to embodiments of the present disclosure.
Embodiments of the present disclosure provide room temperature bondable metal contacts that can be debonded and reused on a micron scale.
Embodiments of the present disclosure provide for the fabrication of high density pillar arrays for mechanical and electrical structures such as interconnects, contact pads, solder bumps (as dense as 0.8 micron pillars with, for example, a 2 micron pitch).
Embodiments of the present disclosure provide for making temporary/reworkable bonds permanent by applying additional force at temperatures from 22 ℃ + and up to 150 ℃.
Embodiments of the present disclosure provide that the distance between the posts is about the diameter of the posts.
For purposes of illustration and disclosure, the foregoing detailed description of exemplary and preferred embodiments has been presented as required by the law. It is not intended to be exhaustive or to limit the disclosure to the precise form described, but only to enable others skilled in the art to understand how the disclosure may be adapted for a particular use or embodiment. The possibilities of modifications and variations will be apparent to a person skilled in the art. The description of the exemplary embodiments is not intended to be limiting, and these embodiments may have included tolerances, feature sizes, specific operating conditions, engineering specifications, etc., and may vary from implementation to implementation or with variations in the state of the art, and no limitations should be implied therefrom. The applicant has made this disclosure in relation to the current state of the art, but advances are also contemplated and future adaptations may take these into account, i.e. in accordance with the current state of the art at the time. Reference to a feature element in the singular is not intended to mean "one and only one" unless explicitly so stated. Furthermore, no element, component, method, or process step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, method, or process step is explicitly recited in the present disclosure. None of the elements disclosed herein are to be interpreted under the provisions of chapter 112, sixth, 35u.s.c. unless the element is explicitly recited using the phrase "means for … …", and none of the methods or process steps herein are to be interpreted under these provisions unless the step is explicitly recited using the phrase "including the step for … …".
Broadly, this document discloses at least the following: an integrated component having a metallic interlocking structure; the integrated component includes: an integrated circuit integrated in a substrate having a top surface; the integrated circuit includes a first conductive line; and a first metallic interlock structure comprising a first array of independent metallic posts formed on the top surface and electrically connected to the first conductive lines.

Claims (20)

1. An integrated component having a metallic interlocking structure; the integrated component includes:
an integrated circuit integrated in a substrate having a top surface; the integrated circuit includes a first conductive line; and
a first metallic interlocking structure comprising a first array of independent metallic posts formed on the top surface.
2. The integrated component of claim 1, wherein the free-standing metal post is electrically connected to the first wire.
3. The integrated component of claim 1, wherein the first array of independent metal posts is arranged such that, along the axis of the posts, the posts are introduced between the posts of the second array of independent metal posts having a size of the same order of magnitude as the first array, bringing the posts of the two arrays into frictional contact and temporarily attaching the first and second arrays.
4. The integrated component of claim 1, wherein the independent metal posts each have a diameter of less than two microns and are at most 10 microns from each other.
5. The integrated component of claim 1, wherein at least one freestanding metal post has a top portion having a dimension perpendicular to the axis of the post that is larger than a base portion of the post.
6. The integrated component of claim 1, wherein a horizontal metal beam connects the tops of at least two adjacent independent metal posts.
7. The integrated component of claim 2, comprising: a second conductive line different from the first conductive line; and
a second metallic interlocking structure comprising a second array of independent metallic posts formed on the top surface and electrically connected to the second conductive lines.
8. An integrated component assembly, comprising:
a first integrated component according to claim 1; and
the second integrated component of claim 1, which is arranged upside down such that the first metallic interlocking structure of the second integrated component interlocks with the first metallic interlocking structure of the first integrated component.
9. The integrated component assembly of claim 8, wherein friction between the length of the post of the second integrated component and the length of the post of the first integrated component maintains the first and second integrated components removably attached to one another.
10. The integrated component assembly of claim 8, wherein at least some of the posts of one of the first and second integrated components have a top portion that is larger than its base portion; and wherein friction of the larger top with the length of the post of the other of the first and second integrated components maintains the first and second integrated components removably attached to each other.
11. A method of manufacturing an integrated component having a metallic interlocking structure; the method comprises the following steps:
providing an integrated component having a substrate with a top surface and having an integrated circuit integrated in the substrate, the integrated circuit comprising a first conductive line; and
a first metal interlock structure comprising a first array of independent metal posts is formed on the top surface.
12. The method of claim 11, wherein said forming a first metal interlock structure comprising a first array of independent metal posts on said top surface comprises: electrically connecting the metal post to the first wire.
13. The method of claim 12, comprising: the first array of individual metal posts is sized such that introducing the posts along the axis of the posts between the posts of a second array of individual metal posts having a size of the same order of magnitude as the first array brings the posts of both arrays into frictional contact and temporarily attaches the first and second arrays.
14. The method of claim 12, comprising: forming the independent metal posts, wherein the diameter of each metal post is less than two microns; and comprises: forming the free-standing metal pillars at most 10 microns apart from each other.
15. The method of claim 12, comprising: forming at least one freestanding metal post having a top portion with a dimension perpendicular to the axis of the post that is larger than the base of the post.
16. The method of claim 12, comprising: forming a horizontal metal beam connecting the tops of at least two adjacent independent metal columns.
17. The method of claim 12, wherein the integrated circuit includes a second conductive line;
the method further comprises the following steps: forming a second metallic interlocking structure comprising a second array of independent metallic posts on the top surface and electrically connected to the second conductive lines.
18. The method of claim 12, wherein said forming a first metal interlock structure on said top surface comprising a first array of independent metal posts electrically connected to said first wire comprises:
depositing a precursor metal layer on the top surface electrically connected to the first conductive line;
electroplating the precursor metal layer;
forming a post mask layer having a recess where the post is to be formed on the electroplated precursor metal layer;
filling the recess of the mask by electroplating; and
the pillar mask is removed.
19. The method of claim 18, further comprising: after filling the recesses of the mask by electroplating and before removing the pillar mask,
forming a post top mask having a recess with a diameter larger than the post;
depositing a top-of-post precursor metal layer at the bottom of the recess of the top-of-post mask;
electroplating the pre-pillar metal layer;
filling the concave portion of the post top mask by electroplating; and
and removing the post top mask.
20. The method of claim 12, comprising: the metal interlock structure is fabricated using steps compatible with subsequent processing steps used to fabricate the integrated circuit.
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