CN111900145A - Semiconductor structure and manufacturing method thereof, semiconductor device and chip - Google Patents

Semiconductor structure and manufacturing method thereof, semiconductor device and chip Download PDF

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Publication number
CN111900145A
CN111900145A CN202010590179.6A CN202010590179A CN111900145A CN 111900145 A CN111900145 A CN 111900145A CN 202010590179 A CN202010590179 A CN 202010590179A CN 111900145 A CN111900145 A CN 111900145A
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China
Prior art keywords
layer
dielectric layer
cobalt
metal
interconnection line
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Inventor
裴俊值
高建峰
李俊杰
刘卫兵
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Priority to CN202010590179.6A priority Critical patent/CN111900145A/en
Publication of CN111900145A publication Critical patent/CN111900145A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure provides a semiconductor structure, a method for manufacturing the same, a semiconductor device, and a chip, wherein the semiconductor structure includes: a semiconductor substrate and a dielectric layer thereon; a via hole in the dielectric layer; a metal interconnection line formed in the via hole; and a cobalt-containing capping layer on the metal interconnect line. The manufacturing method of the semiconductor structure comprises the following steps: providing a semiconductor substrate and a dielectric layer on the semiconductor substrate, wherein a through hole is formed in the dielectric layer; depositing metal in the via hole to form a metal interconnection line; grinding the metal interconnection line to the position below the surface of the dielectric layer; and selectively depositing a cobalt-containing covering layer on the metal interconnection line, so that the cobalt-containing covering layer is positioned above the metal interconnection line. According to the method, the cobalt-containing covering layer is selectively formed on the metal interconnection line, and the cobalt-containing covering layer loads stress migration and electromigration, so that charges in the metal interconnection line are effectively prevented from migrating into the dielectric layer, the condition that the metal interconnection line is damaged due to stress migration or electromigration is reduced, and the reliability of a device is improved.

Description

Semiconductor structure and manufacturing method thereof, semiconductor device and chip
Technical Field
The disclosure belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure, a manufacturing method thereof, a semiconductor device and a chip.
Background
In the subsequent process of the semiconductor device, metal interconnection layers are required to be formed on the semiconductor device, each metal interconnection layer comprises a metal interconnection line and a dielectric layer, a via hole is required to be formed in the dielectric layer, and metal is deposited in the via hole to form the metal interconnection line.
Under the influence of environmental pressure in the manufacturing process, voltage in the working process and other factors, the metal interconnection line has certain Stress Migration (SM) and Electro-migration (EM) conditions. Particularly, as the integration degree of semiconductors is higher and higher, the sizes of metal interconnection lines are also reduced, and under the condition of smaller sizes, the stress migration and electromigration of the metal interconnection lines have greater influence on the performance of the semiconductor device, and even cause the failure of the semiconductor device.
Disclosure of Invention
In order to solve the problems of the existing semiconductor device, the disclosure provides a semiconductor structure, a manufacturing method thereof, a semiconductor device and a chip, wherein a cobalt-containing covering layer is selectively formed on a metal interconnection line, and the cobalt-containing covering layer loads stress migration and electromigration, so that charges in the metal interconnection line are effectively prevented from migrating into a dielectric layer, the condition that the metal interconnection line is damaged by the stress migration or the electromigration is reduced, and the reliability of the device is improved.
In accordance with one or more embodiments, a semiconductor structure comprises: the semiconductor device comprises a semiconductor substrate and a dielectric layer formed on the semiconductor substrate; a via hole embedded in the dielectric layer; a metal interconnection line formed in the via hole; and a cobalt-containing capping layer formed on the metal interconnect.
According to one or more embodiments, a semiconductor device includes the semiconductor structure described above.
According to one or more embodiments, a chip includes the semiconductor device described above.
According to one or more embodiments, a method of fabricating a semiconductor structure includes: providing a semiconductor substrate and a dielectric layer formed on the semiconductor substrate, wherein a via hole is formed in the dielectric layer; depositing metal in the via hole to form a metal interconnection line; grinding the metal interconnection line to the position below the surface of the dielectric layer; and selectively depositing a cobalt-containing covering layer on the metal interconnection line, so that the cobalt-containing covering layer is positioned above the metal interconnection line.
The beneficial effect of this disclosure does:
the cobalt-containing covering layer is selectively formed on the upper portion of the metal interconnection line, stress migration and electromigration are loaded through the cobalt-containing covering layer, charges in the metal interconnection line are effectively prevented from migrating into the dielectric layer, the situation that the metal interconnection line is damaged due to the stress migration or the electromigration is reduced, and the reliability of a semiconductor device is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings.
In the drawings:
fig. 1 is a schematic cross-sectional view of a semiconductor structure in some embodiments of the present disclosure.
Fig. 2 is a schematic view of a dielectric layer and a via in a semiconductor structure according to some embodiments of the present disclosure.
Fig. 3 is a circuit diagram of forming a barrier metal layer and a metal interconnect line in the semiconductor structure shown in fig. 2 in some embodiments of the present disclosure.
Fig. 4 is a schematic structural diagram of the barrier metal layer and the metal interconnection line shown in fig. 3 obtained by performing chemical mechanical polishing in some embodiments of the present disclosure.
Fig. 5 is a schematic diagram of a cobalt-containing capping layer formed on the metal interconnect line shown in fig. 4 according to some embodiments of the present disclosure.
Fig. 6 is a schematic structural view of a cobalt-containing capping layer formed on a metal interconnect line by cmp according to some embodiments of the present disclosure.
Figure 7 is a schematic structural view of the metal interconnect line shown in figure 3 after chemical mechanical polishing in some embodiments of the present disclosure.
Fig. 8 is a schematic diagram of a cobalt-containing capping layer formed on the metal interconnect line shown in fig. 7 according to some embodiments of the present disclosure.
The reference symbols in the above figures represent the following meanings:
100. the structure comprises a semiconductor substrate, 101, a dielectric layer, 102, a via hole, 103, a metal interconnection line, 104, a cobalt-containing covering layer, 105, a barrier metal layer, 106 and a stop layer.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Some embodiments of the present disclosure provide a semiconductor structure, which includes a semiconductor substrate 100, referring to fig. 1, the semiconductor substrate 100 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, a group III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG), or the like. The semiconductor structure may further include a dielectric layer 101 formed on the semiconductor substrate 100, the dielectric layer 101 may be an interlayer dielectric layer or an intermetallic dielectric layer, the dielectric layer 101 may be a nitride capable of being etched, so as to form a via hole on the dielectric layer 101 through an etching process, the via hole may be a damascene structure obtained by etching the dielectric layer 101 through a damascene etching process, and the damascene structure includes a trench (trench) and a through hole (via).
The semiconductor structure may further include a via hole 102 embedded in the dielectric layer 101 and a metal interconnection line 103 formed in the via hole 102, and a metal material of the metal interconnection line 103 may be at least one of copper (Cu), tungsten (W), aluminum (Al), and the like, or an alloy thereof. Since the metal interconnection line 103 is formed in the via hole 102, the via hole 102 is not shown in fig. 1, and a space for accommodating the metal interconnection line 103 is the via hole 102.
The semiconductor structure may further include a cobalt-containing capping layer 104 formed only on the metal interconnect line 103. As shown in fig. 1, the upper surface of the metal interconnection line 103 is lower than the upper surface of the dielectric layer 101; the upper surface of the cobalt-containing capping layer 104 is flush with the upper surface of the dielectric layer 101. The cobalt-containing capping layer 104 covers only the metal interconnection line 103, and the material of the cobalt-containing capping layer 104 may be cobalt (Co) or a metal compound containing cobalt element, such as cobalt silicide, cobalt nitride, etc.
As shown in fig. 1, the semiconductor structure may further include a barrier metal layer 105 formed between the inner wall of the via hole 102 and the metal interconnection line 103, and the material of the barrier metal layer 105 may be tantalum (Ta), tantalum nitride (TaN), or the like. The semiconductor structure may further include a stop layer 106106 formed on the dielectric layer 101 and the cobalt-containing capping layer 104, and the material of the stop layer 106 may be silicon nitride. The semiconductor structure may further form one or more dielectric layers 101 on the stop layer 106, and the metal interconnection line 103 in each dielectric layer 101 may be covered with the cobalt-containing capping layer 104.
In a semiconductor structure, if stress migration or electromigration occurs in the metal interconnection line 103, charges in the metal interconnection line 103 may migrate from the top of the metal interconnection line 103 into the dielectric layer 101, thereby causing performance loss of the semiconductor device. In the semiconductor structure provided by the embodiment of the present disclosure, the cobalt-containing capping layer 104 is selectively formed on the upper portion of the metal interconnection line 103, and stress migration and electromigration are loaded by the cobalt-containing capping layer 104, so that charges in the metal interconnection line 103 are effectively prevented from migrating into the dielectric layer 101, the damage of the metal interconnection line 103 due to stress migration or electromigration is reduced, and the reliability of the semiconductor device is improved.
In other embodiments of the present disclosure, a semiconductor device is provided that includes the semiconductor structure of any of the embodiments of the present disclosure. In the semiconductor device according to the other embodiments of the present disclosure, the cobalt-containing capping layer 104 is selectively deposited on the metal interconnection line 103, and the cobalt-containing capping layer 104 is used to load stress migration and electromigration, so that charges in the metal interconnection line 103 are effectively prevented from migrating into the dielectric layer 101, the damage of the metal interconnection line 103 due to stress migration or electromigration is reduced, and the reliability of the semiconductor device is improved.
Still other embodiments of the present disclosure also provide a chip including the semiconductor device in the various embodiments of the present disclosure.
Some embodiments of the present disclosure also provide methods of fabricating the semiconductor structures in the various embodiments described above.
Referring to fig. 2, a semiconductor substrate 100 and a dielectric layer 101 formed on the semiconductor substrate 100 are provided, wherein a via hole 102 is formed in the dielectric layer 101. The dielectric layer 101 may be an interlayer dielectric layer 101 or an inter-metal dielectric layer 101. And etching the dielectric layer 101 by adopting a Damascus etching process to form a via hole 102 in the dielectric layer 101. The via hole 102 may be a damascene structure obtained by etching the dielectric layer 101 through a damascene etching process, and the damascene structure includes a trench (trench) and a through hole (via).
After etching the via hole 102 in the dielectric layer 101, metal is deposited in the via hole 102 to form a metal interconnection line 103. As shown in fig. 3, a barrier metal layer 105 is electroplated on the surface of the dielectric layer 101 and the inner wall of the via hole 102, and then a metal material is electroplated on the barrier metal layer 105 to form a metal interconnection line 103. The material of the barrier metal layer 105 may be tantalum (Ta), tantalum nitride (TaN), or the like. The metal material of the metal interconnection line 103 may be at least one of copper (Cu), tungsten (W), aluminum (Al), or the like, or an alloy thereof.
After the metal interconnection line 103 is formed, the metal interconnection line 103 is polished to a position below the surface of the dielectric layer 101 by using a Chemical Mechanical Polishing (CMP) process. Specifically, the barrier metal layer 105 on the dielectric layer 101 is chemically and mechanically polished until the upper surface of the dielectric layer 101 is exposed. The metal interconnect 103 is subjected to an excessive cmp until the upper surface of the metal interconnect 103 is lower than the upper surface of the dielectric layer 101, as shown in fig. 4. In the embodiment of the disclosure, the over-polishing of the metal interconnection line 103 may be realized by adjusting the duration of the chemical mechanical polishing process or the process conditions such as the polishing pressure.
A cobalt-containing capping layer 104 is then selectively deposited over the metal interconnect lines 103 such that the cobalt-containing capping layer 104 is only over the metal interconnect lines 103. Specifically, a cobalt-containing capping layer 104 is deposited on the surface of the metal interconnect line 103 using a selective deposition technique. The embodiments of the present disclosure may deposit the cobalt-containing capping layer 104 on the surface of the metal interconnect line 103 by using a mixed gas of cobalt sulfide and cobalt chloride. Selective deposition of the cobalt-containing capping layer 104, i.e., deposition of the cobalt-containing capping layer 104 only on the metal interconnect line 103, can be achieved by adjusting the process conditions of the gas density, deposition duration, pressure, etc. of the mixed gas.
Some cobalt-containing capping layer 104 may be deposited on the top surface of dielectric layer 101 during the deposition of cobalt-containing capping layer 104, and cobalt-containing capping layer 104 may be higher than the top surface of dielectric layer 101, as shown in fig. 5. Therefore, in the embodiment of the present disclosure, the cobalt-containing capping layer 104 is further subjected to chemical mechanical polishing until the cobalt-containing capping layer 104 on the surface of the dielectric layer 101 is removed, the upper surface of the cobalt-containing capping layer 104 on the metal interconnection line 103 is flush with the upper surface of the dielectric layer 101, and the positional relationship among the metal interconnection line 103, the cobalt-containing capping layer 104 and the dielectric layer 101 after the chemical mechanical polishing is shown in fig. 6. The upper surface of the dielectric layer 101 is flush with the upper surface of the cobalt-containing covering layer 104 by chemical mechanical polishing, that is, the node separation is realized by chemical mechanical polishing, and the process is simple.
After the upper surface of the dielectric layer 101 is leveled with the upper surface of the cobalt-containing capping layer 104 by chemical mechanical polishing, a stop layer 106 is deposited over the cobalt-containing capping layer 104 and the dielectric layer 101, as shown in fig. 1. The material of stop layer 106 may be silicon nitride.
According to the embodiment of the disclosure, the cobalt-containing covering layer 104 is selectively formed on the upper portion of the metal interconnection line 103, and the cobalt-containing covering layer 104 is used for loading stress migration and electromigration, so that charges in the metal interconnection line 103 are effectively prevented from migrating into the dielectric layer 101, the damage of the metal interconnection line 103 due to the stress migration or electromigration is reduced, and the reliability of the semiconductor device is improved. The required film quality can be manufactured by a deposition process and a chemical mechanical polishing process without adding a complex process, and the process is simple and low in cost.
Other embodiments of the present disclosure also provide another method of fabricating the semiconductor structure in the above embodiments.
Referring to fig. 2 and 3, a semiconductor substrate 100 and a dielectric layer 101 formed on the semiconductor substrate 100 are provided, wherein a via hole 102 is formed in the dielectric layer 101. A barrier metal layer 105 is electroplated on the surface of the dielectric layer 101 and the inner wall of the via hole 102, and then a metal material is electroplated on the barrier metal layer 105 to form a metal interconnection line 103. The formation processes of the via hole 102, the barrier metal layer 105 and the metal interconnection line 103 are all the same as those of the manufacturing methods provided in the above embodiments, and are not described herein again.
After the metal interconnection line 103 is formed, the metal interconnection line 103 is polished to a position below the surface of the dielectric layer 101 by using a Chemical Mechanical Polishing (CMP) process. In the embodiment of the present disclosure, only the metal interconnection line 103 is ground, the barrier metal layer 105 is not ground, and the metal interconnection line 103 is over-ground so that the upper surface of the metal interconnection line 103 is lower than the upper surface of the dielectric layer 101, as shown in fig. 7. In the embodiment of the disclosure, the over-polishing of the metal interconnection line 103 may be realized by adjusting the duration of the chemical mechanical polishing process or the process conditions such as the polishing pressure.
A cobalt-containing capping layer 104 is then selectively deposited over the metal interconnect lines 103 such that the cobalt-containing capping layer 104 is only over the metal interconnect lines 103. Specifically, a cobalt-containing capping layer 104 is deposited on the surface of the metal interconnect line 103 using a selective deposition technique. The embodiments of the present disclosure may deposit the cobalt-containing capping layer 104 on the surface of the metal interconnect line 103 by using a mixed gas of cobalt sulfide and cobalt chloride. Selective deposition of the cobalt-containing capping layer 104, i.e., deposition of the cobalt-containing capping layer 104 only on the metal interconnect line 103, can be achieved by adjusting the process conditions of the gas density, deposition duration, pressure, etc. of the mixed gas.
It is inevitable during the deposition of the cobalt-containing capping layer 104 that some of the cobalt-containing capping layer 104 will be deposited on the barrier metal layer 105 on the surface of the dielectric layer 101, as shown in fig. 8. In order to avoid short circuit between the metal interconnection line 103 between adjacent vias 102 through the barrier metal layer 105 and the cobalt-containing capping layer 104, in the embodiment of the present disclosure, the cobalt-containing capping layer 104 and the barrier metal layer 105 on the dielectric layer 101 are further subjected to chemical mechanical polishing until the upper surface of the dielectric layer 101 is exposed, and the upper surface of the cobalt-containing capping layer 104 is flush with the upper surface of the dielectric layer 101, and the positional relationship between the metal interconnection line 103, the cobalt-containing capping layer 104 and the dielectric layer 101 after the chemical mechanical polishing is shown in fig. 6. The upper surface of the dielectric layer 101 is flush with the upper surface of the cobalt-containing covering layer 104 by chemical mechanical polishing, that is, the node separation is realized by chemical mechanical polishing, and the process is simple.
After the upper surface of the dielectric layer 101 is leveled with the upper surface of the cobalt-containing capping layer 104 by chemical mechanical polishing, a stop layer 106 is deposited over the cobalt-containing capping layer 104 and the dielectric layer 101, as shown in fig. 1. The material of stop layer 106 may be silicon nitride.
According to the embodiment of the disclosure, the cobalt-containing covering layer 104 is selectively formed on the upper portion of the metal interconnection line 103, and the cobalt-containing covering layer 104 is used for loading stress migration and electromigration, so that charges in the metal interconnection line 103 are effectively prevented from migrating into the dielectric layer 101, the damage of the metal interconnection line 103 due to the stress migration or electromigration is reduced, and the reliability of the semiconductor device is improved. The required film quality can be manufactured by a deposition process and a chemical mechanical polishing process without adding a complex process, and the process is simple and low in cost.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (14)

1. A semiconductor structure, comprising:
the semiconductor device comprises a semiconductor substrate and a dielectric layer formed on the semiconductor substrate;
a via hole embedded in the dielectric layer;
a metal interconnection line formed in the via hole; and the number of the first and second groups,
a cobalt-containing capping layer formed on the metal interconnect line.
2. The semiconductor structure of claim 1,
the upper surface of the metal interconnection line is lower than the upper surface of the dielectric layer;
the upper surface of the cobalt-containing covering layer is flush with the upper surface of the dielectric layer.
3. The semiconductor structure of claim 1,
the dielectric layer is an interlayer dielectric layer or an intermetallic dielectric layer.
4. The semiconductor structure of claim 1, further comprising
A stop layer formed on the dielectric layer and the cobalt-containing capping layer.
5. The semiconductor structure of claim 1, further comprising
And the barrier metal layer is formed between the inner wall of the through hole and the metal interconnection line.
6. A semiconductor device comprising the semiconductor structure of any one of claims 1-5.
7. A chip comprising the semiconductor device of claim 6.
8. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate and a dielectric layer formed on the semiconductor substrate, wherein a via hole is formed in the dielectric layer;
depositing metal in the via hole to form a metal interconnection line;
grinding the metal interconnection line to the position below the surface of the dielectric layer;
and selectively depositing a cobalt-containing covering layer on the metal interconnection line, so that the cobalt-containing covering layer is positioned above the metal interconnection line.
9. The method of claim 8, wherein depositing metal in the via to form a metal interconnect line, comprises:
electroplating a barrier metal layer on the surface of the dielectric layer and the inner wall of the via hole;
and electroplating metal materials on the barrier metal layer to form a metal interconnection line.
10. The method of claim 9, wherein grinding the metal interconnect line below the surface of the dielectric layer comprises:
carrying out chemical mechanical polishing on the barrier metal layer on the dielectric layer until the upper surface of the dielectric layer is exposed;
and carrying out chemical mechanical grinding on the metal interconnection line until the upper surface of the metal interconnection line is lower than the upper surface of the dielectric layer.
11. The method of claim 10, wherein selectively depositing a cobalt-containing capping layer on the metal interconnect line with the cobalt-containing capping layer over the metal interconnect line comprises:
depositing a cobalt-containing capping layer on the surface of the metal interconnect line using a selective deposition technique;
and carrying out chemical mechanical grinding on the cobalt-containing covering layer until the upper surface of the cobalt-containing covering layer is flush with the upper surface of the dielectric layer.
12. The method of claim 9, wherein selectively depositing a cobalt-containing capping layer on the metal interconnect line with the cobalt-containing capping layer over the metal interconnect line comprises:
depositing a cobalt-containing capping layer on the surface of the metal interconnect line using a selective deposition technique;
and carrying out chemical mechanical grinding on the cobalt-containing covering layer and the barrier metal layer positioned on the dielectric layer until the upper surface of the dielectric layer is exposed and the upper surface of the cobalt-containing covering layer is flush with the upper surface of the dielectric layer.
13. The method of claim 11 or 12, further comprising:
and depositing a stop layer on the cobalt-containing covering layer and the dielectric layer.
14. The method according to any one of claims 8 to 12,
the dielectric layer is an interlayer dielectric layer or an intermetallic dielectric layer.
CN202010590179.6A 2020-06-24 2020-06-24 Semiconductor structure and manufacturing method thereof, semiconductor device and chip Pending CN111900145A (en)

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Citations (6)

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Publication number Priority date Publication date Assignee Title
CN102881647A (en) * 2012-10-12 2013-01-16 上海华力微电子有限公司 Preparation method of copper metal covering layer
CN102881646A (en) * 2012-10-12 2013-01-16 上海华力微电子有限公司 Method for preparing copper metal covering layer
CN102915962A (en) * 2012-11-12 2013-02-06 上海华力微电子有限公司 Method for preparing copper metal coating layer
CN102938393A (en) * 2012-11-28 2013-02-20 上海华力微电子有限公司 Copper coating manufacturing method
CN103794545A (en) * 2012-10-29 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for manufacturing metal interconnecting wire
CN104795358A (en) * 2015-04-13 2015-07-22 上海华力微电子有限公司 Formation method and metal interconnection process of cobalt barrier layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102881647A (en) * 2012-10-12 2013-01-16 上海华力微电子有限公司 Preparation method of copper metal covering layer
CN102881646A (en) * 2012-10-12 2013-01-16 上海华力微电子有限公司 Method for preparing copper metal covering layer
CN103794545A (en) * 2012-10-29 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for manufacturing metal interconnecting wire
CN102915962A (en) * 2012-11-12 2013-02-06 上海华力微电子有限公司 Method for preparing copper metal coating layer
CN102938393A (en) * 2012-11-28 2013-02-20 上海华力微电子有限公司 Copper coating manufacturing method
CN104795358A (en) * 2015-04-13 2015-07-22 上海华力微电子有限公司 Formation method and metal interconnection process of cobalt barrier layer

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Application publication date: 20201106