CN111900132B - Semiconductor tube core with sealing ring structure and preparation method thereof - Google Patents
Semiconductor tube core with sealing ring structure and preparation method thereof Download PDFInfo
- Publication number
- CN111900132B CN111900132B CN202010638090.2A CN202010638090A CN111900132B CN 111900132 B CN111900132 B CN 111900132B CN 202010638090 A CN202010638090 A CN 202010638090A CN 111900132 B CN111900132 B CN 111900132B
- Authority
- CN
- China
- Prior art keywords
- metal
- layer
- nanoparticle layer
- metal nanoparticles
- metal nanoparticle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
Abstract
The invention relates to a semiconductor tube core with a sealing ring structure and a preparation method thereof, comprising the following steps: forming a groove in a seal ring area of a semiconductor wafer, forming a first metal nanoparticle layer in the groove, and then sequentially forming a first dielectric layer, a first metal column, a second metal nanoparticle layer, a second dielectric layer, a second metal column, a third metal nanoparticle layer, a third dielectric layer, a third metal column, a fourth metal nanoparticle layer and a fourth dielectric layer on the semiconductor wafer, wherein the fourth dielectric layer completely covers the fourth metal nanoparticle layer.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a semiconductor tube core with a sealing ring structure and a preparation method thereof.
Background
In the manufacturing process of a semiconductor die, the periphery of the die needs to be kept in a sealed state through a sealing ring structure. The conventional sealing ring structure generally adopts a plurality of metal layers which are stacked, and is generally a single sealing ring structure, a double-layer sealing ring structure or a three-layer sealing ring structure, wherein the width of the metal is about 10-20 micrometers. The sealing ring is a continuous metal wire and surrounds the outer ring of the chip. The circuit area of the inner side of the sealing ring can be free from the influence of the external environment, the chip is prevented from being broken, and the long-time stability of the performance of the semiconductor chip is ensured. There is room for improvement in current seal ring structures.
Disclosure of Invention
It is an object of the present invention to overcome the above-mentioned deficiencies of the prior art and to provide a semiconductor die having a seal ring structure and a method of making the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method for preparing a semiconductor die with a seal-ring structure comprises the following steps:
1) providing a semiconductor wafer, wherein the semiconductor wafer comprises a cutting area, an integrated circuit area and a seal ring area positioned between the cutting area and the integrated circuit area, and a groove is formed in the seal ring area of the semiconductor wafer.
2) Then, a mask is formed on the semiconductor wafer, the mask only exposes the region where the groove is located, then a solution containing metal nanoparticles is spin-coated on the semiconductor wafer to form a first metal nanoparticle layer in the groove, and then the mask is removed.
3) Then, a first dielectric layer is formed on the semiconductor wafer, a plurality of first through holes are formed on the first dielectric layer, the first through holes are arranged at intervals and expose the first metal nano-particle layer, and then metal materials are deposited in the first through holes to form a plurality of first metal columns.
4) Then, a mask layer is formed on the semiconductor wafer, a first annular groove is formed in the mask layer, the first annular groove exposes the plurality of first metal columns, a solution containing metal nanoparticles is spun on the first annular groove, so that a second metal nanoparticle layer is formed in the first annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the first metal nanoparticle layer is larger than that of the metal nanoparticles in the second metal nanoparticle layer.
5) And then forming a second dielectric layer on the semiconductor wafer, wherein the second dielectric layer completely covers the second metal nanoparticle layer, then forming a plurality of second through holes on the second dielectric layer, the second through holes are arranged at intervals and expose the second metal nanoparticle layer, and then depositing a metal material in the second through holes to form a plurality of second metal columns.
6) Then, a mask layer is formed on the semiconductor wafer, a second annular groove is formed in the mask layer, the second annular groove exposes the plurality of second metal columns, a solution containing metal nanoparticles is spun on the second annular groove, so that a third metal nanoparticle layer is formed in the second annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the second metal nanoparticle layer is larger than that of the metal nanoparticles in the third metal nanoparticle layer.
7) And then forming a third dielectric layer on the semiconductor wafer, wherein the third dielectric layer completely covers the third metal nanoparticle layer, then forming a plurality of third through holes on the third dielectric layer, the third through holes are arranged at intervals and expose the third metal nanoparticle layer, and then depositing a metal material in the third through holes to form a plurality of third metal columns.
8) Then, a mask layer is formed on the semiconductor wafer, a third annular groove is formed in the mask layer, the third annular groove exposes the plurality of third metal columns, a solution containing metal nanoparticles is spun on the third annular groove, a fourth metal nanoparticle layer is formed in the third annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the third metal nanoparticle layer is larger than that of the metal nanoparticles in the fourth metal nanoparticle layer.
9) And then forming a fourth dielectric layer on the semiconductor wafer, wherein the fourth dielectric layer completely covers the fourth metal nano-particle layer.
Preferably, in the step 1), the trench is formed by wet etching or dry etching, and the depth of the trench is 800-2500 nm.
Preferably, in the step 2), the first metal nanoparticle layer fills the trench, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle diameter of the metal nanoparticles in the first metal nanoparticle layer is 200-500 nm.
Preferably, in the steps 3), 5) and 7), the metal material includes one or more of gold, silver, copper, aluminum, palladium, titanium and nickel, and the first metal pillar, the second metal pillar and the third metal pillar are formed by thermal evaporation, magnetron sputtering, electron beam evaporation, electroplating or electroless plating.
Preferably, in the step 4), the second metal nanoparticle layer fills the first annular groove, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the second metal nanoparticle layer is 100-300 nm.
Preferably, in the step 6), the third metal nanoparticle layer fills the second annular groove, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle diameter of the metal nanoparticles in the third metal nanoparticle layer is 50 to 150 nm.
Preferably, in the step 8), the fourth metal nanoparticle layer fills the third annular groove, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the third metal nanoparticle layer is 10 to 60 nanometers.
The invention also provides a semiconductor tube core with the sealing ring structure, which is prepared and formed by adopting the method.
Compared with the prior art, the invention has the following advantages:
in the preparation process of the semiconductor tube core with the sealing ring structure, the sealing ring structure formed by sequentially stacking the first metal nanoparticle layer, the first metal column, the second metal nanoparticle layer, the second metal column, the third metal nanoparticle layer, the third metal column and the fourth metal nanoparticle layer can effectively eliminate cutting stress, and the sealing ring structure has excellent water vapor permeation resistance by optimizing specific process parameters of each functional layer.
Drawings
Fig. 1 is a schematic diagram of a semiconductor die having a seal-ring structure according to the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, etc. may be used to describe semiconductor chips in embodiments of the present invention, these semiconductor chips should not be limited to these terms. These terms are only used to distinguish the semiconductor chips from one another. For example, the first semiconductor chip may also be referred to as a second semiconductor chip, and similarly, the second semiconductor chip may also be referred to as a first semiconductor chip, without departing from the scope of embodiments of the present invention.
Referring to fig. 1, it should be noted that the illustration provided in the embodiment is only a schematic illustration of the basic idea of the present invention, and only the components related to the present invention are shown in the illustration rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, number and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The embodiment provides a method for preparing a semiconductor die with a seal ring structure, which comprises the following steps:
as shown in fig. 1, 1) a semiconductor wafer 1 is provided, the semiconductor wafer 1 includes a dicing area 11, an integrated circuit area 12, and a seal ring area 13 located between the dicing area 11 and the integrated circuit area 12, and a trench 14 is formed in the seal ring area 13 of the semiconductor wafer 1.
The semiconductor wafer 1 may be a silicon substrate, a germanium substrate, a silicon germanium substrate or an SOI substrate, the integrated circuit region 12 has devices such as a field effect transistor, a resistor, a capacitor, an inductor, a diode, etc., the trench 14 is formed by wet etching or dry etching, and the depth of the trench 14 is 800-.
In a specific embodiment, a photoresist is coated on the semiconductor wafer 1, a mask having an exposed portion of the semiconductor wafer is formed through an exposure and development process, and then a trench 14 is formed in the seal ring region 13 through wet etching or dry etching, wherein the depth of the trench 14 is preferably 1000-.
Then step 2) is performed, then a mask is formed on the semiconductor wafer 1, the mask only exposes the region where the trench 14 is located, then a solution containing metal nanoparticles is spin-coated on the semiconductor wafer 1 to form a first metal nanoparticle layer 2 in the trench, and then the mask is removed.
The groove 14 is filled with the first metal nanoparticle layer 2, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, the particle size of the metal nanoparticles in the first metal nanoparticle layer 2 is 200-500 nm, the concentration of the metal nanoparticles in the solution containing the metal nanoparticles is 10-50mg/ml, the rotation speed of the solution containing the metal nanoparticles in spin coating is 3000-8000 rpm, and the spin coating time is 1-3 minutes.
In a specific embodiment, the metal nanoparticles may be specifically silver nanoparticles or copper nanoparticles, the particle size of the metal nanoparticles in the first metal nanoparticle layer 2 is 200-300 nm, 300-400 nm or 400-500 nm, the concentration of the metal nanoparticles in the solution containing the metal nanoparticles is preferably 20mg/ml, 30mg/ml or 40mg/ml, the rotation speed of spin-coating the solution containing the metal nanoparticles is 3000 rpm, 4000 rpm, 5000 rpm, 6000 rpm, 7000 rpm or 8000 rpm, and the spin-coating time is 1 minute, 2 minutes or 3 minutes.
Then, step 3) is performed, a first dielectric layer 3 is formed on the semiconductor wafer 1, a plurality of first through holes are formed on the first dielectric layer 3, the first through holes are arranged at intervals and expose the first metal nanoparticle layer 2, and a metal material is deposited in the first through holes to form a plurality of first metal pillars 4.
In the step 3), the first dielectric layer 3 may be made of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, zirconium oxide, tantalum oxide, silicon oxynitride, or silicon oxycarbide, and may be deposited by a chemical vapor deposition method, a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, an atomic layer deposition, or a physical vapor deposition method to form the first dielectric layer 3, the metal material may include one or more of gold, silver, copper, aluminum, palladium, titanium, and nickel, and the first metal pillar 4 is formed by thermal evaporation, magnetron sputtering, electron beam evaporation, electroplating, or chemical plating.
In a specific embodiment, the material of the first dielectric layer 3 is preferably silicon dioxide/silicon oxynitride/silicon oxycarbide with a stacked structure, and the first dielectric layer 3 may be formed by a plasma enhanced chemical vapor deposition method, where the metal material is copper or aluminum, and the first metal pillar 4 is formed by thermal evaporation.
Then, step 4) is performed, a mask layer is formed on the semiconductor wafer 1, a first annular groove is formed in the mask layer, the first annular groove exposes the plurality of first metal pillars, a solution containing metal nanoparticles is spin-coated to form a second metal nanoparticle layer 5 in the first annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the first metal nanoparticle layer 2 is larger than that of the metal nanoparticles in the second metal nanoparticle layer 5.
In the step 4), the first annular groove is filled with the second metal nanoparticle layer, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, the particle size of the metal nanoparticles in the second metal nanoparticle layer is 100-.
In a specific embodiment, the metal nanoparticles may be specifically silver nanoparticles or copper nanoparticles, the particle size of the metal nanoparticles in the second metal nanoparticle layer 5 is 100-150 nm, 150-200 nm or 200-300 nm, the concentration of the metal nanoparticles in the solution containing the metal nanoparticles is preferably 30mg/ml, 50mg/ml or 70mg/ml, the rotation speed of spin-coating the solution containing the metal nanoparticles is 3000 rpm, 4000 rpm, 5000 rpm, 6000 rpm, 7000 rpm or 8000 rpm, and the spin-coating time is 1 minute, 2 minutes or 3 minutes.
Then, step 5) is performed, a second dielectric layer 6 is formed on the semiconductor wafer 1, the second dielectric layer 6 completely covers the second metal nanoparticle layer 5, a plurality of second through holes are formed on the second dielectric layer 6, the second through holes are arranged at intervals and expose the second metal nanoparticle layer 5, and a metal material is deposited in the second through holes to form a plurality of second metal pillars 7.
In the step 5), the second dielectric layer 6 may be made of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, zirconium oxide, tantalum oxide, silicon oxynitride, or silicon oxycarbide, and may be deposited by a chemical vapor deposition method, a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, an atomic layer deposition method, or a physical vapor deposition method to form the second dielectric layer 6, where the metal material includes one or more of gold, silver, copper, aluminum, palladium, titanium, and nickel, and the second metal pillar 7 is formed by thermal evaporation, magnetron sputtering, electron beam evaporation, electroplating, or chemical plating.
In a specific embodiment, the material of the second dielectric layer 6 is preferably silicon dioxide/silicon oxynitride/silicon oxycarbide with a stacked structure, and the second dielectric layer 6 may be formed by a plasma enhanced chemical vapor deposition method, where the metal material is copper or aluminum, and the second metal pillar 7 is formed by thermal evaporation.
Then, step 6) is performed, a mask layer is formed on the semiconductor wafer 1, a second annular groove is formed in the mask layer, the second annular groove exposes the plurality of second metal pillars, a solution containing metal nanoparticles is spin-coated to form a third metal nanoparticle layer 8 in the second annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the second metal nanoparticle layer 5 is larger than that of the metal nanoparticles in the third metal nanoparticle layer.
In the step 6), the second annular groove is filled with the third metal nanoparticle layer 8, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, the particle size of the metal nanoparticles in the third metal nanoparticle layer 8 is 50-150 nm, the concentration of the metal nanoparticles in the solution containing the metal nanoparticles is 30-60mg/ml, the rotation speed of the solution containing the metal nanoparticles in spin coating is 3000-8000 rpm, and the spin coating time is 1-3 minutes.
In a specific embodiment, the metal nanoparticles may be specifically silver nanoparticles or copper nanoparticles, the metal nanoparticles in the third metal nanoparticle layer 8 have a particle size of 50-80 nm, 80-120 nm or 120-150 nm, the concentration of the metal nanoparticles in the solution containing the metal nanoparticles is preferably 35mg/ml, 45mg/ml or 55mg/ml, the rotation speed of spin-coating the solution containing the metal nanoparticles is 3000 rpm, 4000 rpm, 5000 rpm, 6000 rpm, 7000 rpm or 8000 rpm, and the spin-coating time is 1 minute, 2 minutes or 3 minutes.
Then, step 7) is performed, a third dielectric layer 9 is formed on the semiconductor wafer, the third dielectric layer 9 completely covers the third metal nanoparticle layer 8, a plurality of third through holes are formed in the third dielectric layer 9, the third through holes are arranged at intervals and expose the third metal nanoparticle layer 8, and a metal material is deposited in the third through holes to form a plurality of third metal pillars 10.
In the step 7), the material of the third dielectric layer 9 may be silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, zirconium oxide, tantalum oxide, silicon oxynitride or silicon oxycarbide, and may be deposited by a chemical vapor deposition method, a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, an atomic layer deposition method or a physical vapor deposition method to form the third dielectric layer 9, the metal material includes one or more of gold, silver, copper, aluminum, palladium, titanium and nickel, and the third metal pillar 10 is formed by thermal evaporation, magnetron sputtering, electron beam evaporation, electroplating or chemical plating.
In a specific embodiment, the material of the third dielectric layer 9 is preferably silicon dioxide/silicon oxynitride/silicon oxycarbide with a stacked structure, and the third dielectric layer 9 may be formed by a plasma enhanced chemical vapor deposition method, where the metal material is copper or aluminum, and the third metal pillar 10 is formed by thermal evaporation.
Then, step 8) is performed, a mask layer is formed on the semiconductor wafer 1, a third annular groove is formed in the mask layer, the third annular groove exposes the plurality of third metal pillars, a solution containing metal nanoparticles is spin-coated to form a fourth metal nanoparticle layer 15 in the third annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the third metal nanoparticle layer 8 is larger than that of the metal nanoparticles in the fourth metal nanoparticle layer 15.
In the step 8), the third annular groove is filled with the fourth metal nanoparticle layer 15, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the fourth metal nanoparticle layer 15 is 10 to 60 nanometers. The concentration of the metal nanoparticles in the solution containing the metal nanoparticles is 40-100mg/ml, the rotating speed of the solution containing the metal nanoparticles in spin coating is 3000-8000 rpm, and the spin coating time is 1-3 minutes.
In a specific embodiment, the metal nanoparticles may be specifically silver nanoparticles or copper nanoparticles, the metal nanoparticles in the fourth metal nanoparticle layer 15 have a particle size of 10-25 nm, 25-45 nm or 45-60 nm, the concentration of the metal nanoparticles in the solution containing the metal nanoparticles is preferably 55mg/ml, 75mg/ml or 95mg/ml, the solution containing the metal nanoparticles is spin-coated at a rotation speed of 3000 rpm, 4000 rpm, 5000 rpm, 6000 rpm, 7000 rpm or 8000 rpm, and the spin-coating time is 1 minute, 2 minutes or 3 minutes.
Then, step 9) is performed, and a fourth dielectric layer 16 is formed on the semiconductor wafer, wherein the fourth dielectric layer 16 completely covers the fourth metal nanoparticle layer 15.
In the step 9), the material of the fourth dielectric layer 16 may be silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, zirconium oxide, tantalum oxide, silicon oxynitride, or silicon oxycarbide, and may be deposited by a chemical vapor deposition method, a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, an atomic layer deposition method, or a physical vapor deposition method to form the fourth dielectric layer 16.
In a specific embodiment, the material of the fourth dielectric layer 16 is preferably silicon dioxide/silicon oxynitride/silicon oxycarbide with a stacked structure, and the fourth dielectric layer 16 may be formed by using a plasma enhanced chemical vapor deposition method.
The invention also provides a semiconductor die with a sealing ring structure, which is prepared and formed by adopting the method as shown in FIG. 1.
In the preparation process of the semiconductor tube core with the sealing ring structure, the sealing ring structure formed by sequentially stacking the first metal nanoparticle layer, the first metal column, the second metal nanoparticle layer, the second metal column, the third metal nanoparticle layer, the third metal column and the fourth metal nanoparticle layer can effectively eliminate cutting stress, and the sealing ring structure has excellent water vapor permeation resistance by optimizing specific process parameters of each functional layer.
The invention provides a semiconductor tube core with a sealing ring structure and a preparation method thereof.
Implementation 1: a method for preparing a semiconductor die with a seal-ring structure comprises the following steps:
1) providing a semiconductor wafer, wherein the semiconductor wafer comprises a cutting area, an integrated circuit area and a seal ring area positioned between the cutting area and the integrated circuit area, and a groove is formed in the seal ring area of the semiconductor wafer.
2) Then, a mask is formed on the semiconductor wafer, the mask only exposes the region where the groove is located, then a solution containing metal nanoparticles is spin-coated on the semiconductor wafer to form a first metal nanoparticle layer in the groove, and then the mask is removed.
3) Then, a first dielectric layer is formed on the semiconductor wafer, a plurality of first through holes are formed on the first dielectric layer, the first through holes are arranged at intervals and expose the first metal nano-particle layer, and then metal materials are deposited in the first through holes to form a plurality of first metal columns.
4) Then, a mask layer is formed on the semiconductor wafer, a first annular groove is formed in the mask layer, the first annular groove exposes the plurality of first metal columns, a solution containing metal nanoparticles is spun on the first annular groove, so that a second metal nanoparticle layer is formed in the first annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the first metal nanoparticle layer is larger than that of the metal nanoparticles in the second metal nanoparticle layer.
5) And then forming a second dielectric layer on the semiconductor wafer, wherein the second dielectric layer completely covers the second metal nanoparticle layer, then forming a plurality of second through holes on the second dielectric layer, the second through holes are arranged at intervals and expose the second metal nanoparticle layer, and then depositing a metal material in the second through holes to form a plurality of second metal columns.
6) Then, a mask layer is formed on the semiconductor wafer, a second annular groove is formed in the mask layer, the second annular groove exposes the plurality of second metal columns, a solution containing metal nanoparticles is spun on the second annular groove, so that a third metal nanoparticle layer is formed in the second annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the second metal nanoparticle layer is larger than that of the metal nanoparticles in the third metal nanoparticle layer.
7) And then forming a third dielectric layer on the semiconductor wafer, wherein the third dielectric layer completely covers the third metal nanoparticle layer, then forming a plurality of third through holes on the third dielectric layer, the third through holes are arranged at intervals and expose the third metal nanoparticle layer, and then depositing a metal material in the third through holes to form a plurality of third metal columns.
8) Then, a mask layer is formed on the semiconductor wafer, a third annular groove is formed in the mask layer, the third annular groove exposes the plurality of third metal columns, a solution containing metal nanoparticles is spun on the third annular groove, a fourth metal nanoparticle layer is formed in the third annular groove, and then the mask is removed, wherein the particle size of the metal nanoparticles in the third metal nanoparticle layer is larger than that of the metal nanoparticles in the fourth metal nanoparticle layer.
9) And then forming a fourth dielectric layer on the semiconductor wafer, wherein the fourth dielectric layer completely covers the fourth metal nano-particle layer.
Implementation 2: in the step 1), the trench is formed by wet etching or dry etching, and the depth of the trench is 800-2500 nm.
Implementation 3: in the step 2), the first metal nanoparticle layer fills the trench, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle diameter of the metal nanoparticles in the first metal nanoparticle layer is 200-500 nm.
Implementation 4: in the steps 3), 5) and 7), the metal material includes one or more of gold, silver, copper, aluminum, palladium, titanium and nickel, and the first metal pillar, the second metal pillar and the third metal pillar are formed by thermal evaporation, magnetron sputtering, electron beam evaporation, electroplating or electroless plating.
Implementation 5: in the step 4), the second metal nanoparticle layer fills the first annular groove, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the second metal nanoparticle layer is 100-300 nm.
Implementation 6: in the step 6), the second annular groove is filled with the third metal nanoparticle layer, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the third metal nanoparticle layer is 50-150 nm.
Implementation 7: in the step 8), the third annular groove is filled with the fourth metal nanoparticle layer, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the third metal nanoparticle layer is 10-60 nm.
Implementation 8: the invention also provides a semiconductor tube core with the sealing ring structure, which is prepared and formed by adopting the method.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for preparing a semiconductor die with a seal ring structure is characterized in that: the method comprises the following steps:
1) providing a semiconductor wafer, wherein the semiconductor wafer comprises a cutting area, an integrated circuit area and a seal ring area positioned between the cutting area and the integrated circuit area, and a groove is formed in the seal ring area of the semiconductor wafer;
2) forming a mask on the semiconductor wafer, wherein the mask only exposes the region where the groove is located, then spin-coating a solution containing metal nanoparticles on the semiconductor wafer to form a first metal nanoparticle layer in the groove, and then removing the mask;
3) forming a first dielectric layer on the semiconductor wafer, forming a plurality of first through holes on the first dielectric layer, wherein the first through holes are arranged at intervals and expose the first metal nano-particle layer, and depositing a metal material in the first through holes to form a plurality of first metal columns;
4) forming a mask layer on the semiconductor wafer, forming a first annular groove in the mask layer, exposing the plurality of first metal columns in the first annular groove, spin-coating a solution containing metal nanoparticles to form a second metal nanoparticle layer in the first annular groove, and removing the mask, wherein the particle size of the metal nanoparticles in the first metal nanoparticle layer is larger than that of the metal nanoparticles in the second metal nanoparticle layer;
5) forming a second dielectric layer on the semiconductor wafer, wherein the second dielectric layer completely covers the second metal nanoparticle layer, forming a plurality of second through holes on the second dielectric layer, the second through holes are arranged at intervals and expose the second metal nanoparticle layer, and depositing a metal material in the second through holes to form a plurality of second metal columns;
6) forming a mask layer on the semiconductor wafer, forming a second annular groove in the mask layer, exposing the plurality of second metal columns in the second annular groove, spin-coating a solution containing metal nanoparticles to form a third metal nanoparticle layer in the second annular groove, and removing the mask, wherein the particle size of the metal nanoparticles in the second metal nanoparticle layer is larger than that of the metal nanoparticles in the third metal nanoparticle layer;
7) forming a third dielectric layer on the semiconductor wafer, wherein the third dielectric layer completely covers the third metal nanoparticle layer, forming a plurality of third through holes on the third dielectric layer, the third through holes are arranged at intervals and expose the third metal nanoparticle layer, and depositing a metal material in the third through holes to form a plurality of third metal columns;
8) forming a mask layer on the semiconductor wafer, forming a third annular groove in the mask layer, exposing the plurality of third metal columns in the third annular groove, spin-coating a solution containing metal nanoparticles to form a fourth metal nanoparticle layer in the third annular groove, and removing the mask, wherein the particle size of the metal nanoparticles in the third metal nanoparticle layer is larger than that of the metal nanoparticles in the fourth metal nanoparticle layer;
9) and then forming a fourth dielectric layer on the semiconductor wafer, wherein the fourth dielectric layer completely covers the fourth metal nano-particle layer.
2. The method of manufacturing a semiconductor die having a seal ring structure as defined in claim 1, wherein: in the step 1), the trench is formed by wet etching or dry etching, and the depth of the trench is 800-2500 nm.
3. The method of manufacturing a semiconductor die having a seal ring structure as defined in claim 1, wherein: in the step 2), the first metal nanoparticle layer fills the trench, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle diameter of the metal nanoparticles in the first metal nanoparticle layer is 200-500 nm.
4. The method of manufacturing a semiconductor die having a seal ring structure as defined in claim 1, wherein: in the steps 3), 5) and 7), the metal material includes one or more of gold, silver, copper, aluminum, palladium, titanium and nickel, and the first metal pillar, the second metal pillar and the third metal pillar are formed by thermal evaporation, magnetron sputtering, electron beam evaporation, electroplating or electroless plating.
5. The method of manufacturing a semiconductor die having a seal ring structure as defined in claim 1, wherein: in the step 4), the second metal nanoparticle layer fills the first annular groove, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the second metal nanoparticle layer is 100-300 nm.
6. The method of manufacturing a semiconductor die having a seal ring structure as defined in claim 1, wherein: in the step 6), the second annular groove is filled with the third metal nanoparticle layer, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the third metal nanoparticle layer is 50-150 nm.
7. The method of manufacturing a semiconductor die having a seal ring structure as defined in claim 1, wherein: in the step 8), the third annular groove is filled with the fourth metal nanoparticle layer, the material of the metal nanoparticles in the solution containing the metal nanoparticles is one of gold, silver, copper and iron, and the particle size of the metal nanoparticles in the third metal nanoparticle layer is 10-60 nm.
8. A semiconductor die having a seal-ring structure formed by the method of any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010638090.2A CN111900132B (en) | 2020-07-03 | 2020-07-03 | Semiconductor tube core with sealing ring structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010638090.2A CN111900132B (en) | 2020-07-03 | 2020-07-03 | Semiconductor tube core with sealing ring structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111900132A CN111900132A (en) | 2020-11-06 |
| CN111900132B true CN111900132B (en) | 2022-01-11 |
Family
ID=73191558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010638090.2A Active CN111900132B (en) | 2020-07-03 | 2020-07-03 | Semiconductor tube core with sealing ring structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111900132B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584433B (en) * | 2020-06-08 | 2021-12-10 | 上海领矽半导体有限公司 | Protective ring and forming method thereof |
| CN112420621A (en) * | 2020-11-26 | 2021-02-26 | 苏州矽锡谷半导体科技有限公司 | Guard ring member of semiconductor wafer and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1617312A (en) * | 2003-11-10 | 2005-05-18 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN108155155A (en) * | 2016-12-02 | 2018-06-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111009336A (en) * | 2019-12-10 | 2020-04-14 | 珠海量致科技有限公司 | Flexible and transparent conductive film and preparation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7265436B2 (en) * | 2004-02-17 | 2007-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-repeated and non-uniform width seal ring structure |
| US20130087925A1 (en) * | 2011-10-05 | 2013-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Structures of Integrated Circuits |
-
2020
- 2020-07-03 CN CN202010638090.2A patent/CN111900132B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1617312A (en) * | 2003-11-10 | 2005-05-18 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN108155155A (en) * | 2016-12-02 | 2018-06-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111009336A (en) * | 2019-12-10 | 2020-04-14 | 珠海量致科技有限公司 | Flexible and transparent conductive film and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111900132A (en) | 2020-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111900132B (en) | Semiconductor tube core with sealing ring structure and preparation method thereof | |
| TWI590380B (en) | Method of forming an interconnect structure for a semiconductor device | |
| CN111564411B (en) | Semiconductor device and forming method thereof | |
| WO2020037497A1 (en) | Capacitor and processing method therefor | |
| CN111900131B (en) | Sealing ring structure of semiconductor wafer and preparation method thereof | |
| CN112366138B (en) | Storage chip packaging structure and preparation method thereof | |
| WO2022110934A1 (en) | Protective ring member for semiconductor wafer and forming method therefor | |
| TWI278034B (en) | A method of manufacturing a semiconductor device | |
| CN113410175B (en) | TSV conductive through hole structure preparation method | |
| US20030096496A1 (en) | Method of forming dual damascene structure | |
| CN111584433B (en) | Protective ring and forming method thereof | |
| CN111584374B (en) | Packaging method of semiconductor device | |
| WO2022007445A1 (en) | Method for preparing three-dimensional capacitor | |
| CN112018071B (en) | Multifunctional TSV structure and preparation method thereof | |
| CN111508852B (en) | Packaging component of semiconductor tube core and preparation method thereof | |
| CN111864064A (en) | Three-dimensional capacitor | |
| KR100896841B1 (en) | Method for forming bond pad on fabricating a semiconductor device | |
| TWI701793B (en) | Electronic device and method of manufacturing the same | |
| CN111799185B (en) | Tube core packaging structure and preparation method thereof | |
| CN104112701A (en) | Semiconductor structure and manufacturing method thereof | |
| CN114267634A (en) | Preparation method of low-through-hole dual damascene structure | |
| CN113809005A (en) | Manufacturing method, circuit and application of NOR flash memory | |
| KR20100011121A (en) | Semiconductor device and method for manufacturing the device | |
| KR100322887B1 (en) | Method for forming multilayered metal-line of semiconductor device | |
| KR20030038521A (en) | Process for fabricating a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221208 Address after: 215600 Shen Jiahui, No. 8, Zhongxin South Road, Jingang town, Zhangjiagang City, Suzhou City, Jiangsu Province Patentee after: ZHANGJIAGANG SHANMU NEW MATERIAL TECHNOLOGY DEVELOPMENT Co.,Ltd. Address before: 215600 Shen Jiahui, No. 8, Zhongxin South Road, Jingang town, Zhangjiagang City, Suzhou City, Jiangsu Province Patentee before: Shen Jiahui |
|
| TR01 | Transfer of patent right |