CN111900095A - Multi-chip integrated packaging method and packaging structure - Google Patents

Multi-chip integrated packaging method and packaging structure Download PDF

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Publication number
CN111900095A
CN111900095A CN202010806238.9A CN202010806238A CN111900095A CN 111900095 A CN111900095 A CN 111900095A CN 202010806238 A CN202010806238 A CN 202010806238A CN 111900095 A CN111900095 A CN 111900095A
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China
Prior art keywords
chip
conductive
reconstituted wafer
front side
wafer
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CN202010806238.9A
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Chinese (zh)
Inventor
徐成
曹立强
孙鹏
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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Priority to CN202010806238.9A priority Critical patent/CN111900095A/en
Publication of CN111900095A publication Critical patent/CN111900095A/en
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
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Abstract

The invention discloses a multi-chip integrated packaging method, which comprises the following steps: bonding the front side of the first chip to the first chip carrier; performing first plastic packaging, and wrapping a first chip in a first plastic packaging material, so as to reconstruct the first chip into a wafer; thinning the first plastic packaging material of the reconstituted wafer to expose the conductive through hole on the back of the first chip, wherein the surface of the reconstituted wafer on which the thinned back of the first chip is located is the back of the reconstituted wafer, and a first conductive interconnection structure is formed on the back of the reconstituted wafer; bonding the back side of the reconstituted wafer to a second wafer; removing the bonding of the front surface of the first chip, wherein the surface of the reconstituted wafer on which the front surface of the first chip is positioned is the front surface of the reconstituted wafer, and a second conductive interconnection structure is formed on the front surface of the reconstituted wafer; attaching a second chip to the second conductive interconnect structure; performing second plastic packaging, and wrapping the second chip in a second plastic packaging material; thinning the second plastic packaging material; and removing the bond on the back of the reconstituted wafer.

Description

Multi-chip integrated packaging method and packaging structure
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a multi-chip integrated packaging method and a multi-chip integrated packaging structure for a small chip (chipset).
Background
Due to the fact that the development threshold of advanced technology nodes is higher and higher in the post-molarity era, more and more companies begin to put research and development forces into the advanced packaging technology, and the continuous improvement of performance in the fields of 3D packaging and high-density integration is expected to be achieved. The Chiplet concept appeared in recent years is the embodiment of the specific application of the idea. The Chiplet is a small chip, decomposes complex functions, develops a plurality of small chips which have single specific functions and can be assembled in a modularized way, realizes the functions of data storage, calculation, signal processing, data stream management and the like, and finally establishes a chip network of the small chips on the basis of the functions. The small chip is manufactured by selecting proper technical nodes according to the application requirement, and the optimization of performance and cost and the modular manufacturing of the chip are realized.
The currently mainstream 2.5D integration technology is CoWoS introduced by TSMC, which utilizes the resources of the previous process and integrates the development of the packaging technology. The adapter plate is manufactured by using FEOL front-track technology, so that the cost is high, and the use of products except high-performance calculation is limited. Since the sizes of the interposer are usually over 30mm × 28mm, the package is large-sized, and the yield of the product is low.
Disclosure of Invention
The invention provides a high-density and high-integration three-dimensional chip wafer level packaging method aiming at a novel packaging method provided by the chip, which can reduce the manufacturing cost and improve the chip integration level.
The invention uses the chips or silicon substrates with different nodes with good test performance for packaging, reduces the cost, and can integrate more flexibly according to the application requirements.
The wafer is used for plastic package to form the reconstructed wafer, so that the manufacturing efficiency of the integration process is improved, the subsequent chip mounting, holding and chip thinning are facilitated, and the production efficiency is improved.
According to one aspect of the invention, a multi-chip integrated packaging method is provided, which comprises the following steps:
bonding a front side of a first chip to a first chip, the front side of the first chip having pads, the first chip further comprising conductive vias extending from under the pads of the front side to the back side;
performing first plastic packaging, and wrapping a first chip in a first plastic packaging material, so as to reconstruct the first chip into a wafer;
thinning the first plastic packaging material of the reconstituted wafer to expose the conductive through hole on the back of the first chip, wherein the surface of the reconstituted wafer on which the thinned back of the first chip is located is the back of the reconstituted wafer, and a first conductive interconnection structure is formed on the back of the reconstituted wafer;
bonding the back side of the reconstituted wafer to a second wafer;
removing the bonding of the front surface of the first chip, wherein the surface of the reconstituted wafer on which the front surface of the first chip is positioned is the front surface of the reconstituted wafer, and a second conductive interconnection structure is formed on the front surface of the reconstituted wafer;
attaching a second chip to the second conductive interconnect structure;
performing second plastic packaging, and wrapping the second chip in a second plastic packaging material;
thinning the second plastic packaging material; and
and removing the bonding on the back of the reconstituted wafer.
In one embodiment of the invention, the front side of the first chip is bonded to the first carrier sheet by means of a first temporary bonding film.
In one embodiment of the present invention, forming the first conductive interconnect structure comprises:
forming a conductive circuit and a dielectric layer between the conductive circuits on the back of the reconstituted wafer, wherein the conductive circuits are electrically and/or signal connected with the conductive through holes; and
pads and/or solder balls are formed on the conductive lines.
In one embodiment of the invention, the back side of the reconstituted wafer is bonded to a second carrier sheet by a second temporary bonding film.
In one embodiment of the present invention, forming the second conductive interconnect structure comprises:
forming a conducting circuit and a dielectric layer between the conducting circuits on the front side of the reconstituted wafer, wherein the conducting circuits are electrically and/or signal connected with the bonding pads on the front side of the first chip; and
pads and/or solder balls are formed on the conductive lines.
In one embodiment of the present invention, the second molding compound is thinned to a specified thickness by a chemical mechanical polishing process.
In one embodiment of the invention, the multi-chip integrated packaging method further comprises performing an underfill process to fill a void between the second chip and the second conductive interconnect structure after attaching the second chip to the second conductive interconnect structure.
According to another embodiment of the present invention, there is provided a multi-chip integrated package structure including:
a first chip including pads on a front side and conductive vias extending from the front side pads to a back side;
the packaging structure comprises a first plastic packaging material wrapping a first chip, wherein the front surface of the first chip is flush with the front surface of the first plastic packaging material, and the back surface of the first chip is flush with the back surface of the first plastic packaging material;
the first conductive interconnection structure is arranged on the back surface of the first chip and the back surface of the first plastic package material and comprises a first conductive circuit and a dielectric layer between the conductive circuits, the first conductive circuit is electrically and/or signal connected with the conductive through hole, and a first bonding pad and/or a first solder ball is formed on the conductive circuit;
the second conductive interconnection structure is arranged on the front surface of the first chip and the front surface of the first plastic package material, and comprises a second conductive circuit and a dielectric layer between the conductive circuits, and the second conductive circuit is electrically and/or signal connected with the bonding pad on the front surface of the first chip;
a second chip comprising pads at a front side, the second chip being attached at the front side to a second conductive interconnect structure, devices within the second chip forming electrical and/or signal connections with the second conductive interconnect structure; and
and the second plastic package material wraps the second chip and the top surfaces of the second conductive interconnection structures.
In another embodiment of the present invention, the first chip includes a plurality of chips or substrates, the second chip includes a plurality of chips, and a back surface of the second chip is exposed from the second molding compound.
In another embodiment of the present invention, the second chip is bonded to the second conductive interconnect structure by a solder ball, and the underfill material fills a gap between the second chip and the second conductive interconnect structure.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a flow diagram of a multi-chip integrated packaging method according to one embodiment of the invention.
Fig. 2A to 2J are schematic cross-sectional views illustrating a multi-chip integrated packaging process according to an embodiment of the present invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
The embodiment of the invention provides a multi-chip integrated packaging method and a multi-chip integrated packaging structure for a small chip (chiplet), which integrate a plurality of active or passive chips (with Through Silicon Vias (TSV)), are flexible in scheme, and can adopt chips with different process nodes or TSV silicon substrates and corresponding wiring and packaging interconnection of line width and line distance according to requirements. The packaging method and the packaging structure of the invention adopt a wafer-level plastic packaging process to form the reconstituted wafer, and adopt a wafer-level back process, and the reconstituted wafer can utilize the packaging process to carry out a front and back rewiring process.
Fig. 1 shows a flow diagram of a multi-chip integrated packaging method according to one embodiment of the invention. Fig. 2A to 2J are schematic cross-sectional views illustrating a multi-chip integrated packaging process according to an embodiment of the present invention.
First, in step 101, a chip 201 to be integrated is provided, as shown in fig. 2A. In an embodiment of the present invention, the chips 201 to be integrated are chips or substrates at different process nodes, which may have conductive vias 202. For example, the chips 201 to be integrated may be chips of different technology nodes, different functions, different sizes, and the chips have completed the front-side TSV process. Chip 201 may include one or more chips or substrates. The chip 201 may be a logic chip such as a CPU, a DSP, a GPU, an FPGA, etc., a memory chip such as a ROM, a DRAM, a Flash, etc., or other types of chips or sensors such as an SOC, etc. (e.g., MEMS sensors, etc.). The front side of the chip or substrate 201 may have a device region, metal interconnects, pads, and dielectric layer. The chip or substrate may have conductive vias 202 extending from under the front side pads to the back side.
At step 102, the chip 201 to be integrated is bonded to a carrier 203, as shown in fig. 2B. In an embodiment of the invention, the chip 201 to be integrated may be front-bonded to the carrier 203 by means of a temporary bonding film 204. The temporary bonding film may be a thermoplastic or thermosetting organic material, or an inorganic material containing Cu, Ni, Cr, Co, or the like, and may be removed by heating, mechanical, chemical, laser, freezing, or the like.
In step 103, the chip 201 to be integrated is reconstructed into a wafer 205 by wafer molding, as shown in fig. 2C. In the embodiment of the present invention, the wafer molding usually uses thermosetting or thermoplastic resin materials, and the usable polymer materials are wide in variety, including: polyimide PI, bis-benzocyclobutene resin BCB or phenyl benzobisoxazole resin PBO, epoxy resin, organic silicon, acrylic acid derivative and the like. The wafer molding compound has fixing, supporting, and insulating functions on the chip 201.
In step 104, thinning is performed until the conductive through holes TSV on the back side of the chip 201 are exposed, and a conductive interconnection structure 206 is formed above the conductive through holes TSV, as shown in fig. 2D. In an embodiment of the present invention, the thinning of the reconstituted wafer 205 may be performed by a chemical mechanical polishing process until the conductive vias 202 are exposed from the backside of the chip 201. Then, a conductive interconnect structure 206 is formed, including: conductive lines and dielectric layers between the conductive lines are formed on the back side of reconstituted wafer 205 (i.e., the back side of die 201), the conductive lines are electrically and/or signal connected to conductive vias 202, and then pads and/or solder balls are formed on the conductive lines. In particular embodiments of the present invention, for example, forming the conductive interconnect structure 206 may specifically include: forming a seed layer on the surface of the wafer 205, forming photoresist on the seed layer, exposing and developing to pattern the photoresist, electroplating to form a conductive circuit, removing the photoresist and the seed layer, forming a dielectric layer on the conductive circuit by rolling, spin coating, spraying, printing, non-rotation coating, hot pressing, vacuum pressing, soaking, pressure fitting and other modes, exposing a part of the conductive circuit in the dielectric layer to be used as a bonding pad, and then placing a solder ball on the bonding pad. It should be understood by those skilled in the art that other processes may be used to form the conductive interconnect structure 206 and the scope of the present invention is not limited to the specific methods described above. In particular embodiments of the present invention, one or more layers of conductive traces may be formed according to design requirements.
At step 105, the reconstituted wafer 205 is bonded to a slide 207, as shown in FIG. 2E. In an embodiment of the present invention, the backside of the reconstituted wafer 205 may be bonded to the carrier 207 by a temporary bonding film 208. The temporary bonding film may be a thermoplastic or thermosetting organic material, or an inorganic material containing Cu, Ni, Cr, Co, or the like, and may be removed by heating, mechanical, chemical, laser, freezing, or the like.
At step 106, the bonding of the front side of the chip 201 is removed and a conductive interconnect structure 209 is formed on the front side, as shown in fig. 2F. In an embodiment of the present invention, the process used to remove the bond on the front side of chip 201 may be determined based on the material and process selected for the front side of chip 201. For example, if the front side of the chip 201 to be integrated is bonded to the carrier 203 through the temporary bonding film 204, the bonding of the front side of the chip 201 may be removed by heating, mechanical, chemical, laser, freezing, or the like.
Forming the conductive interconnect structure 209 comprises: conductive lines and dielectric layers between the conductive lines are formed on the front side of the reconstituted wafer 205 (i.e., the front side of the die 201), the conductive lines are electrically and/or signal connected to metal interconnects, electrodes or pads on the front side of the die, and then pads and/or solder balls are formed on the conductive lines. In a particular embodiment of the present invention, for example, forming the conductive interconnect structure 209 may specifically include: forming a seed layer on the front surface of the wafer 205, forming photoresist on the seed layer, exposing and developing to pattern the photoresist, electroplating to form a conductive circuit, removing the photoresist and the seed layer, forming a dielectric layer on the conductive circuit by rolling, spin coating, spraying, printing, non-rotation coating, hot pressing, vacuum pressing, soaking, pressure fitting and the like, exposing a part of the conductive circuit in the dielectric layer to be used as a bonding pad, and then placing a solder ball on the bonding pad. It should be understood by those skilled in the art that other processes may be used to form the conductive interconnect structure 209 and the scope of the present invention is not limited to the specific methods described above. In particular embodiments of the present invention, one or more layers of conductive traces may be formed according to design requirements.
At step 107, a chip 210 is attached to the conductive interconnect structure 209 and underfilled, as shown in FIG. 2G. The chip 210 may include one or more chips, and the chip 210 may be a logic chip such as a CPU, a DSP, a GPU, an FPGA, or the like, a memory chip such as a ROM, a DRAM, a Flash, or the like, or other types of chips or sensors (such as a MEMS sensor, or the like) such as an SOC, or the like. The front side of chip 210 may have device regions, metal interconnects, pads, or solder balls. The front side of the chip 210 may be flip-chip bonded to the conductive interconnect 209 to enable electrical and/or signal connections of devices within the chip 210 to the conductive interconnect 209. Next, an underfill material 211 is filled in the gap between the chip 210 and the conductive interconnect structure 209 by an underfill process. The underfill material 211 can distribute the stress experienced by the chip surface and thus improve the reliability of the overall product.
At step 108, the die 210 is wafer molded, as shown in fig. 2H. In the embodiment of the present invention, the wafer molding usually uses thermosetting or thermoplastic resin materials, and the usable polymer materials are wide in variety, including: polyimide PI, bis-benzocyclobutene resin BCB or phenyl benzobisoxazole resin PBO, epoxy resin, organic silicon, acrylic acid derivative and the like. The wafer molding compound has fixing, supporting, and insulating functions on the chip 210.
In step 109, the molding compound 212 is thinned, as shown in fig. 2I. In an embodiment of the present invention, the molding compound may be thinned to a specified thickness by a chemical mechanical polishing process. Since the thicknesses of the plurality of chips 210 may not be uniform, the thinning process may be performed until the back surface of one or more of the chips 210 is exposed, or the back surface of one or more of the chips 210 is thinned by a certain thickness.
At step 110, the bonds on the back side of the reconstituted wafer 205 are removed, as shown in FIG. 2J. In embodiments of the present invention, the process used to remove the bond on the back side of the reconstituted wafer 205 may be determined based on the material and process selected for the back side of the reconstituted wafer 205. For example, if the backside of the reconstituted wafer 205 is bonded to the carrier by a temporary bonding film, the bonding of the backside of the reconstituted wafer 205 may be removed by heating, mechanical, chemical, laser, freezing, etc., such that the reconstituted wafer 205 is separated from the carrier 207 and the conductive interconnect structures 206 of the backside of the reconstituted wafer are exposed.
The package structure shown in fig. 2J includes: the semiconductor package comprises a chip 201, a mold compound 205 wrapping the chip 201, a conductive interconnect structure 206 disposed on a back surface of the chip 201 and the mold compound 205, a conductive interconnect structure 209 disposed on a front surface of the chip 201 and the mold compound 205, a chip 210 attached to the conductive interconnect structure 209, and a mold compound 212 wrapping the chip 210.
The chip 201 may be a chip or a substrate. Chip 201 may include one or more chips or substrates. The front side of the chip or substrate 201 may have a device region, metal interconnects, pads, and dielectric layer. The chip or substrate 201 may have conductive vias 202 extending from under the front side pads to the back side. The conductive vias 202 form electrical or signal connections with the conductive interconnect structures 206.
The backside of the chip 201 is substantially flush with one side of the molding compound 205, and conductive interconnect structures 206 are disposed on the backside of the chip 201 and the molding compound 205. Conductive interconnect structures 206 include conductive lines and dielectric layers between the conductive lines that form electrical and/or signal connections with conductive vias 202. Pads and/or solder balls may be formed on the conductive lines.
The front side of the chip 201 and the other side of the molding compound 205 are substantially flush, and a conductive interconnect structure 209 is disposed on the front side of the chip 201 and the molding compound 205. Conductive interconnect structures 209 include conductive lines and dielectric layers between the conductive lines that make electrical and/or signal connections with pads or electrodes on the front side of chip 201.
Chip 210 may include one or more chips. The front side of the chip 210 may have device regions, metal interconnects, pads, and dielectric layers. The front side of the chip 210 may be flip-chip bonded to the conductive interconnect 209 to enable electrical and/or signal connections of devices within the chip 210 to the conductive interconnect 209. The pads of the die 210 and the conductive interconnect structure 209 are filled with an underfill material 211. The underfill material 211 can distribute the stress experienced by the chip surface and thus improve the reliability of the overall product.
A molding compound 212 encapsulates the top surfaces of the die 210 and the conductive interconnect structures 209. The back surfaces of one or more of the chips 210 may be flush with the top surface of the molding compound 212 and exposed from the top surface of the molding compound 212.
The multi-chip integrated packaging method and the multi-chip integrated packaging structure for the small chip (chiplet) disclosed by the embodiment of the invention can realize the integration of a plurality of active or passive chips (with Through Silicon Vias (TSVs)), have flexible schemes, and can adopt chips with different process nodes or TSV silicon substrates and corresponding wiring and packaging interconnection of line width and line distance according to requirements. And forming the reconstructed wafer by adopting a wafer-level plastic package process. With the wafer level back side process, the reconstituted wafer can utilize the packaging process to perform the front and back side rewiring process.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (10)

1. A multi-chip integrated packaging method comprises the following steps:
bonding a front side of a first chip onto a first chip, the front side of the first chip having pads, the first chip further comprising conductive vias extending from under the pads of the front side to the back side, the first chip comprising a plurality of chips at different technology nodes, different functions and/or different sizes;
performing first plastic packaging, and wrapping a first chip in a first plastic packaging material, so as to reconstruct the first chip into a wafer;
thinning the first plastic packaging material of the reconstituted wafer to expose the conductive through hole on the back of the first chip, wherein the surface of the reconstituted wafer on which the thinned back of the first chip is located is the back of the reconstituted wafer, and a first conductive interconnection structure is formed on the back of the reconstituted wafer;
bonding the back side of the reconstituted wafer to a second wafer;
removing the bonding of the front surface of the first chip, wherein the surface of the reconstituted wafer on which the front surface of the first chip is positioned is the front surface of the reconstituted wafer, and a second conductive interconnection structure is formed on the front surface of the reconstituted wafer;
attaching a second chip to the second conductive interconnect structure;
performing second plastic packaging, and wrapping the second chip in a second plastic packaging material;
thinning the second plastic packaging material; and
and removing the bonding on the back of the reconstituted wafer.
2. The multi-chip integrated package method of claim 1, wherein the front side of the first chip is bonded to the first carrier by a first temporary bonding film.
3. The multi-chip integrated package method of claim 1, wherein forming the first conductive interconnect structure comprises:
forming a conductive circuit and a dielectric layer between the conductive circuits on the back of the reconstituted wafer, wherein the conductive circuits are electrically and/or signal connected with the conductive through holes; and
pads and/or solder balls are formed on the conductive lines.
4. The multi-chip integrated package method of claim 1, wherein the back side of the reconstituted wafer is bonded to a second carrier sheet by a second temporary bonding film.
5. The multi-chip integrated package method of claim 1, wherein forming a second conductive interconnect structure comprises:
forming a conducting circuit and a dielectric layer between the conducting circuits on the front side of the reconstituted wafer, wherein the conducting circuits are electrically and/or signal connected with the bonding pads on the front side of the first chip; and
pads and/or solder balls are formed on the conductive lines.
6. The method of claim 1, wherein the second mold compound is thinned to a specified thickness by a chemical mechanical polishing process.
7. The multi-chip integrated packaging method of claim 1, further comprising performing an underfill process to fill a void between the second chip and the second conductive interconnect structure after attaching the second chip to the second conductive interconnect structure.
8. A multi-chip integrated package structure comprising:
a first chip including pads on a front side and conductive vias extending from the front side pads to a back side;
the packaging structure comprises a first plastic packaging material wrapping a first chip, wherein the front surface of the first chip is flush with the front surface of the first plastic packaging material, and the back surface of the first chip is flush with the back surface of the first plastic packaging material;
the first conductive interconnection structure is arranged on the back surface of the first chip and the back surface of the first plastic package material and comprises a first conductive circuit and a dielectric layer between the conductive circuits, the first conductive circuit is electrically and/or signal connected with the conductive through hole, and a first bonding pad and/or a first solder ball is formed on the conductive circuit;
the second conductive interconnection structure is arranged on the front surface of the first chip and the front surface of the first plastic package material, and comprises a second conductive circuit and a dielectric layer between the conductive circuits, and the second conductive circuit is electrically and/or signal connected with the bonding pad on the front surface of the first chip;
a second chip comprising pads at a front side, the second chip being attached at the front side to a second conductive interconnect structure, devices within the second chip forming electrical and/or signal connections with the second conductive interconnect structure; and
and the second plastic package material wraps the second chip and the top surfaces of the second conductive interconnection structures.
9. The multi-chip integrated package structure of claim 8, wherein the first chip comprises a plurality of chips or substrates, the second chip comprises a plurality of chips, and a backside of the second chip is exposed from the second molding compound.
10. The multi-chip integrated package structure of claim 8, wherein the second chip is bonded to the second conductive interconnect structure by solder balls, and an underfill material fills a gap between the second chip and the second conductive interconnect structure.
CN202010806238.9A 2020-08-12 2020-08-12 Multi-chip integrated packaging method and packaging structure Pending CN111900095A (en)

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Application publication date: 20201106