CN111899777A

CN111899777A - Single-gate multi-write non-volatile memory and operation method thereof

Info

Publication number: CN111899777A
Application number: CN201910367887.0A
Authority: CN
Inventors: 林信章; 骆玮彤; 黄文谦
Original assignee: Yield Microelectronics Corp
Current assignee: Yield Microelectronics Corp
Priority date: 2019-05-05
Filing date: 2019-05-05
Publication date: 2020-11-06

Abstract

A single gate write-in non-volatile memory and its operation method many times, this non-volatile memory is a single floating gate, it sets up transistor and capacitor structure on the semiconductor substrate, the transistor has two ion doped regions as source and drain in the semiconductor substrate of both sides of conducting gate, wherein the width of source and drain is designed to be different, can utilize the edge of the drain as the capacitor, in order to control the floating gate; the invention can use the least control voltage types and the least components during writing, can greatly shorten the length of the control circuit, achieves the effect of reducing the whole area, and further reduces the production cost of the non-volatile memory.

Description

Single-gate multi-write non-volatile memory and operation method thereof

Technical Field

The present invention relates to a single-gate multi-write nonvolatile Memory (Non-Volatile Memory), and more particularly, to a single-gate multi-write nonvolatile Memory using a drain edge as a capacitor to control a floating gate and an operating method thereof.

Background

Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common method for manufacturing Application Specific Integrated Circuits (ASICs). Today, as computer information products are developed, an Electrically Erasable Programmable Read Only Memory (EEPROM) has a nonvolatile Memory function of Electrically programming and erasing data, and data does not disappear after power is turned off, so that it is widely used in electronic products.

Non-volatile memories are programmable, storing charge to change the gate voltage of the memory's transistor, or not storing charge to leave the gate voltage of the memory's transistor. The erase operation removes all the charge stored in the non-volatile memory, and returns all the non-volatile memory to the gate voltage of the transistor of the original memory. In the structure of the existing single-gate non-volatile memory, there are many kinds of control voltages and many storage elements, so the area of the non-volatile memory is larger, resulting in the increase of the cost.

In view of the above, the present invention provides a single-gate multi-write nonvolatile memory and an operating method thereof, which can greatly reduce the area of the single-gate nonvolatile memory and increase the product value of the single-gate nonvolatile memory.

Disclosure of Invention

The main objective of the present invention is to provide a single gate multiple write nonvolatile memory and its operation method, in which the source and drain in the nonvolatile memory are designed to have different widths, and the edge of the drain is used as a capacitor to control the floating gate, so that the minimum voltage variety and the minimum components can be controlled during writing, thereby achieving the effect of reducing the whole area. Compared with the common non-volatile memory which can be written into a single gate and has complicated control, the invention has the advantages of reducing the number of components, greatly reducing the number of control circuits and greatly reducing the cost of the non-volatile memory because the operation is simple and the cost is reduced.

Therefore, in order to achieve the above object, the present invention discloses a single-gate multiple-write nonvolatile memory, which includes a P-type semiconductor substrate, a transistor and a capacitor structure; the transistor and the capacitor structure are arranged on a P-type semiconductor substrate, the transistor is formed by stacking a first conductive gate on the surface of a first dielectric layer, the first dielectric layer is positioned on the P-type semiconductor substrate, two highly conductive ion doped regions are positioned in the P-type semiconductor substrate at two sides of the first conductive gate and the first dielectric layer to form a source electrode and a drain electrode, and the source electrode and the drain electrode have different widths; the capacitor structure uses the edge of the drain as the capacitor to control the floating gate, and the middle of the drain and the floating gate contains the lightly doped region, the lightly doped region and the ion doped region have the same type of ions, and form the single floating gate of the non-volatile memory.

In the invention, the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well, the transistor structure is an N-type transistor, and the lightly doped region and the ion doped region are N-type ion doped regions.

In addition, the single-gate multiple-write nonvolatile memory operation method disclosed by the invention can be used for the single-gate multiple-write nonvolatile memory composed of the P-type semiconductor substrate, the transistor and the capacitor structure, and the substrate voltage V is respectively applied to the P-type semiconductor substrate, the source and the drain_subSource voltage V_sDrain voltage V_dA write or erase process is performed. Wherein, at the time of writing, V is satisfied_subTo ground (═ 0), V_d＝V_sHigh Voltage (HV); or V_dHigh Voltage (HV), and V_sMedium (MV) or Low (LV) pressure; or V_dMedium Voltage (MV), V_sLow Voltage (LV) or ground (0). At the time of erasing, satisfy V_subIs grounded (0), V_dHigh Voltage (HV), V_sFloating connection; or V_dHigh Voltage (HV), V_sIs ground (═ 0); or V_sHigh Voltage (HV), and V_dGround (0); or V_sHigh Voltage (HV), and V_dNamely floating joint.

The purpose, technical content, features and effects of the present invention will be more readily understood by the following detailed description of the embodiments taken in conjunction with the accompanying drawings.

Drawings

FIG. 1 is a cross-sectional view of a single-gate multiple-write nonvolatile memory structure according to one embodiment of the present invention.

FIG. 2 shows a layout structure of sources and drains with different widths according to an embodiment of the present invention.

FIG. 3 shows another layout structure of source and drain with different widths according to one embodiment of the present invention.

Fig. 4 is a schematic diagram of a structure with three end points according to an embodiment of the present invention.

Description of reference numerals: 100-single gate multiple write non-volatile memory; 110-NMOS transistor; 111-a first dielectric layer; 112-a first conductive gate; 113-a source; 114-a drain; 115-channel; 116-lightly doped region; a 120-N type capacitor structure; 130-P type semiconductor substrate; l is_d-a length; l is_s-a length; v_d-a drain voltage; v_s-a source voltage; v_sub-a substrate voltage; w_d-a width; w_s-a width.

Detailed Description

Referring to fig. 1, a cross-sectional view of a single-gate multi-write nonvolatile memory structure according to an embodiment of the present invention is shown.

The single-gate write-many nonvolatile memory 100 includes a P-type semiconductor substrate 130, which may also be a semiconductor substrate with a P-type well, here, the P-type semiconductor substrate 130 is taken as an example, and an NMOS transistor (NMOSFET)110 and an N-type capacitor structure 120 are disposed in the P-type semiconductor substrate 130; the NMOS transistor 110 includes a first dielectric layer 111 on the surface of the P-type semiconductor substrate 130, a first conductive gate 112 overlying the first dielectric layer 111, and two ion-doped regions in the P-type semiconductor substrate 130, respectively serving as a source 113 and a drain 114 thereof, forming a channel 115 between the source 113 and the drain 114, wherein the source 113 and the drain 114 have different widths; the N-type capacitor structure 120 uses the edge of the drain 114 as a capacitor to control a floating gate and form a floating gate of the non-volatile memory 100. Specifically, the edge of the drain 114 is in the middle of the floating gate. Wherein the drain 114 and the floating gate have a lightly doped region 116 in between, and the ion doped region and the lightly doped region are N-type ion doped regions.

In the present invention, the width of the source 113 and the drain 114 refers to the length of the side along a horizontal axis (i.e. the parallel direction from the source 113 to the drain 114), and as shown in FIG. 1, the width W of the drain 114 of the present embodiment is_dIs greater than the width W of the source 113_s. In addition, the lengths of the source 113 and the drain 114 can be different, as shown in FIG. 2, one aspect of the present embodiment is to make the length L of the ion doped region of the drain 114 be different_dDesigned to be longer than the length L of the ion-doped region of the source 113_s(ii) a In addition, as shown in FIG. 3, another aspect of the present embodiment is to adjust the length L of the ion doped region of the drain 114_dDesigned to be longer than the length L of the ion-doped region of the source 113_sAnd two opposite sides of the elastic piece form an included angle.

The single-gate multiple-write nonvolatile memory 100 has three terminals, as shown in FIG. 4, which are a source, a drain and a substrate connection structure, respectively, and a substrate voltage V is applied to the P-type semiconductor substrate 130, the source 113 and the drain 114, respectively_subSource voltage V_sAnd a drain voltage V_d. The operating voltage process conditions for the single-gate multiple-write nonvolatile memory 100 are as follows:

when writing:

a.V_subground (0).

b.V_d＝V_sHigh Voltage (HV); or

V_dHigh Voltage (HV), and V_sMedium (MV) or Low (LV) pressure; or

V_dMedium Voltage (MV), and V_sLow Voltage (LV) or ground (0).

During erasing:

a.V_subground (0).

b.V_dHigh Voltage (HV), and V_sGround (0); or

V_dHigh Voltage (HV), and V_sFloating connection; or

V_sHigh Voltage (HV), and V_dGround (0); or

V_sHigh pressure(HV), and V_dNamely floating joint.

Further, the ranges of "high voltage", "middle voltage" and "low voltage" proposed in the above bias conditions are specified, wherein "high voltage" refers to the drain-to-source breakdown voltage-the threshold voltage V of the transistor_t(ii) a "Medium Voltage" refers to the drain-to-source breakdown voltage x 1/2; and "low voltage" refers to the drain-to-source breakdown voltage x 1/4.

The structure of FIG. 1 is fabricated on a P-type silicon wafer, after the basic isolation structure is completed by standard isolation module process, the channel of an NMOS transistor is formed by ion implantation, after the dielectric layer of the first conductive gate is grown, polysilicon is deposited and patterned by photolithography to form a single floating gate; then, ion implantation is performed to form the drain and source electrodes of the NMOS transistor. After metallization, the fabrication of many single-gate multiple-write non-volatile memory structures is completed.

In summary, according to the single-gate multi-write nonvolatile memory and the operating method thereof disclosed by the invention, compared with a general single-gate writable nonvolatile memory, the control is complex and the cost is higher, the invention can control the voltage and the components at least during writing, the area of the nonvolatile memory can be greatly reduced, the length of a control circuit can be shortened, and the purpose of greatly reducing the production cost can be achieved.

The foregoing is illustrative of the nature of the invention provided by the embodiments and the objects thereof are to be understood by those skilled in the art that the invention is not to be limited to the embodiments disclosed herein, but rather, it is to be understood that various modifications and equivalent arrangements may be devised without departing from the spirit and scope of the present invention.

Claims

1. A single gate multiple write non-volatile memory, comprising:

a P-type semiconductor substrate;

a transistor, which is arranged on the P-type semiconductor substrate and comprises a first dielectric layer, a first conductive gate and a plurality of ion doped regions, wherein the first dielectric layer is positioned on the surface of the P-type semiconductor substrate, the first conductive gate is overlapped on the first dielectric layer, the plurality of ion doped regions are arranged in the semiconductor substrate and positioned at two sides of the first conductive gate to respectively form a source electrode and a drain electrode, and the source electrode and the drain electrode have different widths; and

and a capacitor structure disposed on the P-type semiconductor substrate, wherein the capacitor structure uses the edge of the drain as a capacitor to control a floating gate, and a lightly doped region is provided between the drain and the floating gate, and has ions of the same type as those of the ion doped regions to form a single floating gate of the non-volatile memory.

2. A single gate multiple write operation method of non-volatile memory includes a P-type semiconductor substrate, a transistor and a capacitor structure, the transistor is set on the P-type semiconductor substrate, the transistor includes a first dielectric layer, a first conductive gate and multiple ion doped regions, the first dielectric layer is set on the surface of the P-type semiconductor substrate, the first conductive gate is set on the first dielectric layer, the multiple ion doped regions are set in the semiconductor substrate and set on two sides of the first conductive gate to form source and drain separately, the width of the source and drain are different, the capacitor structure uses the edge of the drain as capacitor to control a floating gate, and the middle of the drain and the floating gate includes a lightly doped region, the lightly doped region and the multiple ion doped regions have the same type of ions, and forming a single floating gate of the non-volatile memory, wherein the operating method comprises the steps of:

respectively applying a substrate voltage V to the P-type semiconductor substrate, the source and the drain_subA source voltage V_sAnd a drain voltage V_dAnd satisfies the following conditions:

when writing:

a.V_subground (0); and

b.V_d＝V_shigh Voltage (HV); or