CN111897747A - Cache dynamic allocation method of on-chip coprocessor and on-chip system - Google Patents
Cache dynamic allocation method of on-chip coprocessor and on-chip system Download PDFInfo
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- CN111897747A CN111897747A CN202010724922.2A CN202010724922A CN111897747A CN 111897747 A CN111897747 A CN 111897747A CN 202010724922 A CN202010724922 A CN 202010724922A CN 111897747 A CN111897747 A CN 111897747A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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Abstract
The invention provides a Cache dynamic allocation method of an on-chip coprocessor and an on-chip system, wherein the method comprises the following steps: dividing partial area in the on-chip SRAM as the Cache of the coprocessor; and the CPU dynamically allocates the capacity of the Cache according to the application. The invention multiplexes the Cache of the coprocessor and the on-chip SRAM resources, thereby improving the utilization rate of the SRAM and reducing the on-chip storage area.
Description
Technical Field
The invention relates to the technical field of Cache allocation inside a chip, in particular to a Cache dynamic allocation method of an on-chip coprocessor and an on-chip system.
Background
The Cache is also called Cache memory, belongs to a high-speed Cache memory, and is a high-speed small-capacity memory positioned between a CPU and a main memory. Usually, the speed of the CPU is much higher than that of the memory, so when the CPU accesses data directly from the memory, the data cannot be directly extracted completely, and time buffering is required. The Cache has the function of storing a part of data which is used or recycled by the CPU, once the CPU needs to use the part of data again, the data can be directly called from the Cache without calling the data from the memory again, and therefore the efficiency of the system is improved.
With the continuous increase of the application complexity of the chip, the number of the multi-core system on a chip is increased, and the system architecture of the CPU and the coprocessor can flexibly meet various complex application requirements. In a multi-core system on a chip, each processor is provided with a private Cache, but the equivalent storage space of the private Cache is smaller, so that more accesses to an external storage unit are caused; if the Cache space is increased, the chip area is increased, and if the coprocessor does not participate in the work, Cache resources of the coprocessor cannot be released, so that the waste of the resources is caused.
The structure of a conventional system on chip is shown in fig. 1, and the system on chip includes 3 processors: a general purpose processor CPU for processing communication and task scheduling; the first coprocessor is used for executing logic control tasks; the second is used to perform motion control tasks. To improve system performance, typically both coprocessors need to be provided with a private Cache, with the Cache size being 4 KB. Two coprocessors then require 8KB of Cache space, which is certainly a large occupancy for on-chip resource-hungry systems. And two coprocessors in the system on chip belong to a special processor and are started only when the function is needed. For example, the second coprocessor is only activated when applied to the control of motors, machine tools, etc. When the second coprocessor is turned off, the private Cache space of the second coprocessor cannot be allocated to other processors for use, so that the space is wasted.
Therefore, there is a need for an improved method for Cache dynamic allocation of on-chip coprocessors and an improved system-on-chip.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a Cache dynamic allocation method of an on-chip coprocessor and an on-chip system, which improve the utilization rate of an SRAM and reduce the on-chip storage area by multiplexing Cache resources and the on-chip SRAM.
In a first aspect, the present invention provides a method for dynamically allocating Cache of an on-chip coprocessor, comprising the following steps: dividing partial area in the on-chip SRAM as the Cache of the coprocessor; and the CPU dynamically allocates the capacity of the Cache according to the application.
Optionally, the step of dividing a partial area in the on-chip SRAM into caches serving as coprocessors further includes the following steps: a plurality of Cache partitions are configured in the on-chip SRAM, and the address of each partition can be continuous or discontinuous.
Optionally, the step of performing, by the CPU, dynamic allocation of the Cache capacity according to the application specifically includes: and the CPU configures whether each coprocessor has a Cache and the position and the size of the Cache in the SRAM on the chip according to the application.
Optionally, the method further comprises: and connecting the coprocessor and the Cache distributed by the coprocessor in the on-chip SRAM through an AHB-LITE bus.
Optionally, a Cache management module is further arranged in the coprocessor and used for managing caches allocated by the coprocessor in the on-chip SRAM, and if the CPU does not allocate a Cache to the coprocessor, the Cache management module is closed.
Furthermore, the invention also provides an on-chip system, which comprises a CPU, at least one coprocessor and an on-chip SRAM; and dividing partial area in the on-chip SRAM to serve as Cache of the at least one coprocessor, and performing dynamic allocation of Cache capacity by the CPU according to application.
Optionally, multiple Cache partitions are configured in the on-chip SRAM, and each partition address may be continuous or discontinuous.
Optionally, the CPU configures, according to an application, whether the at least one coprocessor has a Cache, and a position and a size of the Cache in the on-chip SRAM.
Optionally, the coprocessor and the Cache allocated by the coprocessor in the on-chip SRAM are connected through an AHB-LITE bus.
Optionally, a Cache management module is further arranged in the coprocessor and used for managing caches allocated by the coprocessor in the on-chip SRAM, and if the CPU does not allocate a Cache to the coprocessor, the Cache management module is closed.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention divides partial area of the on-chip SRAM as the Cache of the coprocessor to realize the multiplexing of Cache resources and the on-chip SRAM, can flexibly configure whether each coprocessor has the Cache, can leave the memory space for the CPU or the coprocessor with higher performance requirement for use without allocating the Cache in the application with lower performance requirement of the coprocessor, thereby improving the performance of the whole on-chip system.
2. The invention can also flexibly configure the position and the size of each coprocessor Cache in the on-chip SRAM, can balance and allocate the memory space of each coprocessor Cache and the CPU according to the application, and can greatly improve the utilization rate of SRAM resources on the premise of ensuring the performance of the coprocessor.
3. The CPU has access authority to the Cache space of the coprocessor, and the flexibility of Cache management and the adaptability to special applications are improved.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of a conventional system on a chip;
FIG. 2 is a block diagram of a system on a chip according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for dynamically allocating Cache of an on-chip coprocessor according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Fig. 2 is a block diagram of a system on chip according to an embodiment of the present invention, and as shown in fig. 2, the system on chip includes a CPU 1, at least one coprocessor, an on-chip SRAM 4, and a Flash 5, in this embodiment, the at least one coprocessor includes a first coprocessor 2 and a second coprocessor 3.
In this embodiment, a partial area in the on-chip SRAM 4 is divided to be used as a Cache of the coprocessor, the CPU dynamically allocates the Cache capacity according to the application, and can flexibly configure whether each coprocessor has a Cache and the position and size of the Cache in the on-chip SRAM 4 as needed.
Specifically, the private Cache of the coprocessor in the prior art is replaced by one or more BANKs of an on-chip shared SRAM, and the coprocessor and the Cache distributed in the on-chip SRAM by the coprocessor are connected through an AHB-LITE bus. In addition, the SRAM access time sequence of the system is the same as the access time sequence of the private Cache through the AHB-LITE, and the access efficiency is not influenced by changing the AHB-LITE bus into the AHB-LITE bus. The sizes of the caches of the coprocessors can be integrally coordinated according to application scenes and shared SRAM allocation. Therefore, the capacity of the SRAM can be ensured, and larger Cache space can be given to the coprocessor to the greatest extent, so that the hit rate of the Cache is improved, the access times of the coprocessor to the flash in the system on chip are reduced, and the system performance is improved.
Optionally, if one coprocessor is allocated with a Cache in the on-chip SRAM 4, the address and size of the Cache are allocated by the CPU, and the coprocessor further includes a Cache management module, where the Cache management module is configured to manage the Cache allocated by the coprocessor in the on-chip SRAM 4, and the Cache management module belongs to a part of the coprocessor and is integrated in each coprocessor. The Cache management module manages 8 partitions of the instruction Cache, and comprises the operations of mapping, replacing, clearing, matching and the like. Firstly, a Cache management module judges whether an instruction is stored in the Cache according to address information of a read instruction request, and if so, a hit instruction address is given; if the instruction is not in the Cache, reading a corresponding instruction from the Flash 5, updating the instruction into the Cache, and feeding back the hit instruction address.
The register is used for storing basic configuration information of the CPU to the Cache management module of the coprocessor, and specifically, the register of the Cache management module in this embodiment includes the following table 1:
TABLE 1
In addition, if the CPU does not allocate the Cache to the coprocessor, the Cache management module is closed, and the coprocessor directly reads the instruction from the code storage area of the Flash 5 and executes the instruction.
In an alternative embodiment, multiple Cache partitions are configured in the on-chip SRAM 4, and each partition address may be continuous or discontinuous.
Further, the present invention also provides a method for dynamically allocating Cache of an on-chip coprocessor, as shown in fig. 3, the method for dynamically allocating Cache of an on-chip coprocessor includes the following steps:
s31: dividing partial area in the on-chip SRAM as the Cache of the coprocessor; and
s32: and the CPU dynamically allocates the capacity of the Cache according to the application.
Specifically, the private Cache of the coprocessor in the prior art is replaced by one or more BANKs of an on-chip shared SRAM, and the coprocessor and the Cache distributed in the on-chip SRAM by the coprocessor are connected through an AHB-LITE bus. And the CPU selectively configures whether each coprocessor has a Cache and the position and the size of the Cache in the SRAM on the chip according to the application.
In this embodiment, both the CPU and the coprocessor in the system on chip may access the Cache space.
In an alternative embodiment, multiple Cache partitions are configured in the on-chip SRAM 4, and each partition address may be continuous or discontinuous.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A Cache dynamic allocation method of an on-chip coprocessor is characterized in that: the method comprises the following steps:
dividing partial area in the on-chip SRAM as the Cache of the coprocessor; and
and the CPU dynamically allocates the capacity of the Cache according to the application.
2. A method for dynamically allocating Cache of an on-chip coprocessor according to claim 1, characterized by: the step of dividing partial area in the on-chip SRAM as the Cache of the coprocessor further comprises the following steps: a plurality of Cache partitions are configured in the on-chip SRAM, and the address of each partition can be continuous or discontinuous.
3. A method for dynamically allocating Cache of an on-chip coprocessor according to claim 1, characterized by: the step of dynamically allocating the Cache capacity by the CPU according to the application specifically comprises: and the CPU configures whether each coprocessor has a Cache and the position and the size of the Cache in the SRAM on the chip according to the application.
4. A method for dynamically allocating Cache of an on-chip coprocessor according to claim 3, characterized by: the method further comprises the following steps: and connecting the coprocessor and the Cache distributed by the coprocessor in the on-chip SRAM through an AHB-LITE bus.
5. The method for dynamically allocating Cache of an on-chip coprocessor according to any one of claims 1 to 4, wherein: and the coprocessor is also provided with a Cache management module for managing the Cache distributed in the SRAM by the coprocessor, and if the CPU does not distribute the Cache to the coprocessor, the Cache management module is closed.
6. A system on a chip, characterized by: the system on chip comprises a CPU, at least one coprocessor and an on-chip SRAM; and dividing partial area in the on-chip SRAM to serve as Cache of the at least one coprocessor, and performing dynamic allocation of Cache capacity by the CPU according to application.
7. The system on a chip of claim 6, wherein: a plurality of Cache partitions are configured in the on-chip SRAM, and the address of each partition can be continuous or discontinuous.
8. The system on a chip of claim 6, wherein: and the CPU configures whether the at least one coprocessor has a Cache and the position and the size of the Cache in the on-chip SRAM according to the application.
9. The system on a chip of claim 8, wherein: and connecting the coprocessor and the Cache distributed by the coprocessor in the on-chip SRAM through an AHB-LITE bus.
10. The system on chip of any of claims 6 to 9, wherein: and the coprocessor is also internally provided with a Cache management module for managing the Cache distributed in the on-chip SRAM by the coprocessor, and if the CPU does not distribute the Cache to the coprocessor, the Cache management module is closed.
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2020
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| CN1607509A (en) * | 2003-08-16 | 2005-04-20 | 三星电子株式会社 | Apparatus and method for composing a cache memory of a wireless terminal having a coprocessor |
| CN102591799A (en) * | 2011-12-30 | 2012-07-18 | 华为技术有限公司 | Method and device for data storage |
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