CN111896291A

CN111896291A - Sample preparation method and device

Info

Publication number: CN111896291A
Application number: CN202010795796.XA
Authority: CN
Inventors: 夏思; 张洋
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-08-10
Filing date: 2020-08-10
Publication date: 2020-11-06
Anticipated expiration: 2040-08-10
Also published as: CN111896291B

Abstract

The invention provides a sample preparation method and a sample preparation device, wherein a layer to be detected on the section of a 3D-NAND memory is marked, the layer to be detected is positioned on a 3D-NAND memory substrate, and the section is a surface vertical to the substrate direction; extracting a sample along a direction perpendicular to the cross section and parallel to the substrate, the sample including a layer to be detected; and thinning the sample according to the mark to obtain the layer to be detected in the sample. In this way, the layer to be detected is marked on the surface of the 3D-NAND memory perpendicular to the substrate direction, then the sample is taken along the perpendicular direction of the cross section and the direction parallel to the substrate, and only the layer to be detected and a small number of laminated layers around the layer to be detected need to be taken in the process of taking the sample. The sample is taken from a cross-section, with little volume and mass compared to taking a sample from the surface of a 3D-NAND memory. And when the extracted sample is thinned, only part of other laminated layers around the layer to be detected need to be removed, so that the waste of machine resources is reduced.

Description

Sample preparation method and device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a sample preparation method and a sample preparation device.

Background

The storing and reading functions of the 3D NAND memory are closely related to the topography of the channel holes in the stack layers, and thus the storing and reading functions of the 3D NAND memory are often verified by detecting the channel holes.

The existing method for detecting the topography of a channel hole is to extract a sample from the surface of a stack layer of a 3D NAND memory, where the sample includes a layer to be detected, and then scan the layer to be detected by a TEM (Transmission Electron Microscope), so as to obtain the topography of the channel hole in the layer to be detected, for example, the size of the channel hole, the thickness of a functional layer stored in the channel hole, and the like.

However, as the number of stacked layers increases, when the topography of the channel hole at the bottom of the stacked layer is detected, deep samples, such as 192 layers and 256 layers, need to be extracted from the surface of the stacked layer, so that the depth of downward digging is large, which not only takes a long time, but also the volume and weight of the extracted sample are large, which makes the extraction of the sample difficult. In addition, because the volume of the extracted sample is very large, when the layer to be detected is detected, a large number of stacked layers except the layer to be detected need to be removed, and machine resources are wasted.

Disclosure of Invention

In view of the above, the present invention provides a sample preparation method and apparatus, which can reduce the mass and volume of the extracted sample.

In order to achieve the purpose, the invention has the following technical scheme:

a method of sample preparation comprising:

marking a layer to be detected on the section of the 3D-NAND memory, wherein the layer to be detected is positioned on a substrate of the 3D-NAND memory, and the section is a surface vertical to the direction of the substrate;

extracting a sample along the vertical direction of the cross section and the direction parallel to the substrate, wherein the sample comprises a layer to be detected;

and thinning the sample according to the mark to obtain the layer to be detected in the sample.

Optionally, the sample comprises the substrate, the substrate comprising a first region and a second region;

said thinning said sample according to said indicia comprises:

only the layer to be detected and the first region above the second region are retained.

Optionally, the method further includes:

attaching an additional substrate to one side of the sample;

then, when the sample is thinned according to the mark, the method further comprises: thinning the attached additional substrate.

Optionally, the attaching an additional substrate to one side of the sample includes:

adhering the substrate to a side of the sample close to the substrate of the 3D-NAND memory.

Optionally, the method further includes:

and detecting the layer to be detected in the sample to obtain the appearance of the channel hole in the layer to be detected in the sample.

Optionally, the marking the layer to be detected on the cross section of the 3D-NAND memory includes:

and coating a protective layer on the surface of the layer to be detected on the section of the 3D-NAND memory.

Optionally, the stacking layer of the 3D-NAND memory includes a silicon oxide layer and a silicon nitride layer, and the layer to be detected is the silicon oxide layer or the silicon nitride layer;

before marking the layer to be detected of the 3D-NAND memory section, the method further comprises the following steps:

etching the silicon oxide layer or the silicon nitride layer in the cross section to distinguish the silicon oxide layer from the silicon nitride layer.

A sample preparation device, comprising:

the marking unit is used for marking a layer to be detected on the section of the 3D-NAND memory, the layer to be detected is positioned on a substrate of the 3D-NAND memory, and the section is a surface vertical to the direction of the substrate;

the extraction unit is used for extracting a sample along the vertical direction of the cross section and the direction parallel to the substrate, and the sample comprises a layer to be detected;

and the thinning unit is used for thinning the sample according to the mark so as to obtain the layer to be detected in the sample.

the thinning unit is specifically configured to only reserve the layer to be detected and the first region above the second region.

Optionally, the method further includes:

an adhering unit for adhering an additional substrate to one side of the sample;

the thinning unit is specifically used for thinning the attached additional substrate.

According to the sample preparation method and device provided by the embodiment of the invention, the layer to be detected on the section of the 3D-NAND memory is marked, the layer to be detected is positioned on the substrate of the 3D-NAND memory, and the section is a surface vertical to the direction of the substrate; extracting a sample along a direction perpendicular to the cross section and parallel to the substrate, the sample including a layer to be detected; and thinning the sample according to the mark to obtain the layer to be detected in the sample. In this way, the layer to be detected is marked on the surface of the 3D-NAND memory perpendicular to the substrate direction, then the sample is taken along the perpendicular direction of the cross section and the direction parallel to the substrate, and only the layer to be detected and a small number of laminated layers around the layer to be detected need to be taken in the process of taking the sample. The sample is taken from a cross-section, with little volume and mass compared to taking a sample from the surface of a 3D-NAND memory. And when the extracted sample is thinned, only part of other laminated layers around the layer to be detected need to be removed, so that the waste of machine resources is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 shows a schematic flow diagram of sample preparation according to an embodiment of the present invention;

FIG. 2 shows a schematic view of a cross-sectional load bearing apparatus according to an embodiment of the present invention;

FIG. 3 shows a schematic structural view of a cross-section according to an embodiment of the invention;

FIG. 4 shows an electron microscope picture with cross-section marked according to an embodiment of the invention;

FIG. 5 shows a schematic structural view of a cross-section according to an embodiment of the invention;

6-13 show electron microscope pictures of a cross-section according to an embodiment of the present invention;

FIG. 14 shows a schematic structural diagram of a layer to be detected according to an embodiment of the invention;

FIG. 15 shows an electron microscope picture of a layer to be detected according to an embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

As described in the background art, as the number of stacked layers increases, when the topography of the channel hole at the bottom of the stacked layer is detected, it is necessary to extract deep samples, for example, 192 layers and 256 layers, from the surface of the stacked layer, and thus the depth of the downward digging is large, which not only takes a long time, but also extracts a large volume and weight of the sample, resulting in difficulty in sample extraction. In addition, because the volume of the extracted sample is very large, when the layer to be detected is detected, a large number of stacked layers except the layer to be detected need to be removed, and machine resources are wasted.

Marking a layer to be detected on the section of the 3D-NAND memory, wherein the layer to be detected is positioned on a substrate of the 3D-NAND memory, and the section of the layer to be detected is a surface vertical to the direction of the substrate; extracting a sample along a direction perpendicular to the cross section and parallel to the substrate, the sample including a layer to be detected; and thinning the sample according to the mark to obtain the layer to be detected in the sample. In this way, the layer to be detected is marked on the surface of the 3D-NAND memory perpendicular to the substrate direction, then the sample is taken along the perpendicular direction of the cross section and the direction parallel to the substrate, and only the layer to be detected and a small number of laminated layers around the layer to be detected need to be taken in the process of taking the sample. The sample is taken from a cross-section, with little volume and mass compared to taking a sample from the surface of a 3D-NAND memory. And when the extracted sample is thinned, only part of other laminated layers around the layer to be detected need to be removed, so that the waste of machine resources is reduced.

In order to facilitate understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

In step S01, referring to fig. 1, the layer to be detected 12 on the 3D-NAND memory section 10 is marked, the layer to be detected 120 is located on the substrate 100 of the 3D-NAND memory, and the section 10 is a surface perpendicular to the substrate 100.

In the embodiment of the present application, the 3D-NAND memory includes a substrate 100 and a stack layer 130 above the substrate, and the substrate 100 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate may also be a substrate of other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like.

The stack layer 130 includes an insulating layer 121 and a sacrificial layer 122, the insulating layer 121 is located between adjacent sacrificial layers 122, between the sacrificial layer 122 and the substrate 100 and on the sacrificial layer 122 at the top layer, the sacrificial layer 122 is used for occupying positions for subsequently forming a gate layer, and the insulating layer 121 is used for isolating the adjacent gate layers. The larger the number of layers of the insulating layer 121 or the sacrificial layer 122, the larger the memory cell in the memory cell string formed, and the higher the integration degree of the device. The number of layers of the insulating layer 121 or the sacrificial layer 122 may be, for example, 16, 32, 48, 64, 72, 96, or 128 layers. In a specific embodiment, the insulating layer 121 may be a silicon oxide layer, and the sacrificial layer 122 may be a silicon nitride layer.

Stack 130 may include a core storage region generally formed in a middle region of stack 130 and a staging region generally formed around the core storage region for forming a string of memory cells and the staging region for forming a contact to a gate layer. The memory cell string includes a channel hole 123, a memory function layer and a channel layer 134 sequentially formed in the channel hole 123, the channel hole 123 penetrating through the stacked layer 130 to the substrate 100, the channel layer 134 formed on a sidewall of the memory function layer and a bottom of the channel hole 123 in contact with the epitaxial structure 110, and a filling layer 135 layer, which may be formed with an insulating material, between the channel layers 134. The storage function layer may include a charge blocking layer 131, a charge storage layer 132, and a charge tunneling layer 133, which are sequentially stacked. In a specific embodiment, the charge blocking layer 131, the charge storage layer 132, and the charge tunneling layer 133 may be an ONO (Oxide-Nitride-Oxide) stack, i.e., a stack of Oxide, Nitride, and Oxide, the channel layer 134 may be a polysilicon layer, and the filling layer 135 may be a silicon Oxide layer.

For convenience of description, the 3D direction will be defined as a first axis X, a second axis Y, and a third axis Z, the first axis X and the second axis Y being two axes orthogonal in a plane in which the surface of the substrate 100 is located, the first axis X being an axis extending along the core storage region, the second axis Y being perpendicular to the first axis X, and the third axis Z being an axis perpendicular to the surface of the substrate 100. In the embodiment of the present application, the cross section 10 of the 3D-NAND memory is a surface perpendicular to the substrate 100, that is, a plane where the first axis X and the third axis Z are located and a plane where the second axis Y and the third axis Z are located. In this application, a plane where the first axis X and the third axis Z are located is referred to as an XZ plane, and a plane where the second axis Y and the third axis Z are located is referred to as a YZ plane. In this embodiment, the cross-section 10 may be an XZ plane or a YZ plane of the core storage region.

In the embodiment of the application, the layer 120 to be detected on the 3D-NAND memory section 10 is marked, the layer 120 to be detected is located on the substrate 100 of the 3D-NAND memory, and the layer 120 to be detected may be any one of the stacked layers 130, for example, may be a certain insulating layer or a certain sacrificial layer in the stacked layers 130. In a specific application, when the topography of the channel hole in the 32 nd insulating layer needs to be detected, the XZ plane of the 3-NAND memory is ground to expose the stacked layers, and then the 32 nd insulating layer is marked. Specifically, a protective layer may be coated on the surface of the layer to be detected 120, i.e., the 32 th insulating layer, so as to accurately obtain the layer to be detected 120, and the protective layer protects the layer to be detected from being damaged in the process of extracting the sample, and may be tungsten. The surface of the layer to be detected 120 may be coated with a tungsten protective layer by Ion Beam Enhanced Deposition (IBED) method.

In a specific application, the layer 120 to be detected on the 3D-NAND memory section 10 is marked, and may be the ground 3D-NAND memory placed on a support device (holder) with a section, as shown in fig. 2, the section 10 may be an XZ plane of the substrate 100 and the stacked layer 130, or a YZ plane of the substrate 100 and the stacked layer 130, as shown in fig. 3. Then, the layer to be detected 120 on the cross section 10 is marked, as shown in fig. 4 and 5, fig. 4 is a scanning schematic diagram of a transmission electron microscope, and fig. 5 is a structural schematic diagram of the cross section on which the layer to be detected has been marked.

In this embodiment, the insulating layer 121 is a silicon oxide layer, the sacrificial layer 122 is a silicon nitride layer, and a cross-sectional view of the 3D-NAND memory is obtained according to a transmission electron microscope, but since a difference between the silicon oxide layer and the silicon nitride layer is small, a boundary between the silicon oxide layer and the silicon nitride layer in the cross-sectional view obtained by the transmission electron microscope is not clear, and the silicon oxide layer or the silicon nitride layer in the cross-section may be etched before the layer to be detected is marked to distinguish the silicon oxide layer from the silicon nitride layer, so as to increase the accuracy of marking. Referring to fig. 6-8, a BOE (Buffered Oxide Etch) may be used to Etch the silicon Oxide layer, since the BOE has a relatively high corrosivity to silicon Oxide and a relatively low corrosivity to silicon nitride, the silicon Oxide layer is etched only for 5-10 seconds during the etching process, so as to save the process time and improve the process efficiency. Phosphoric acid can also be used for corroding the silicon nitride layer, and phosphoric acid has small corrosivity to silicon oxide and can also play a role in distinguishing the silicon oxide layer from the silicon nitride layer. Fig. 6 is a transmission electron microscope picture of a silicon oxide layer and a silicon nitride layer after electron Beam (E-Beam) etching, fig. 7 is a projection electron microscope picture of a silicon oxide layer and a silicon nitride layer after ion Beam (I-Beam) etching, and fig. 8 is a comparison picture between before and after ion Beam etching, and it can be seen from fig. 6-8 that, after the silicon oxide layer is etched, a recess appears at the position where the silicon oxide layer is located, so that the boundary between the silicon oxide layer and the silicon nitride layer is clearer, and thus the accurate position of the layer to be detected can be obtained.

In step S02, a sample is taken in a direction perpendicular to the cross-section 10 and parallel to the substrate 100, the sample including the layer 120 to be detected, as shown with reference to fig. 9.

In the present embodiment, the sample is extracted along the vertical direction of the cross section 10 and the direction parallel to the substrate 100, since the layer to be detected 120 is marked, the layer to be detected 120 and the part of the stacked layers around the layer to be detected 120 can be extracted during the process of extracting the sample according to the mark, and the part of the stacked layers around the layer to be detected 120 is extracted simultaneously during the process of extracting the layer to be detected 120, so as to protect the layer to be detected 120 from being damaged, as shown in fig. 9. For example, when it is desired to obtain the profile of the channel hole in the 72 th insulating layer, a mark may be made on the 72 th insulating layer of the cross-section 10, and then the 72 th insulating layer and the partial stacked layers around it may be extracted from the direction perpendicular to the cross-section 10 and parallel to the substrate 100. In the prior art, a sample is extracted downwards from the surface of a 3D-NAND memory, the extracted sample comprises 1 st to 72 th insulating layers and a sacrificial layer between the 1 st to 72 th insulating layers, so that the weight and the volume of the extracted sample are very large, and a needle used for extracting the sample can not extract the sample in the process of extracting the sample upwards. In the present application, the sample is extracted along the direction perpendicular to the cross-section 10 and perpendicular to the substrate 100, and only the layer to be detected 120 and a part of the stacked layers around the layer need to be extracted during the extraction of the sample. Compared with the sample obtained by the method in the prior art, the volume and the mass of the sample extracted by the method are small, and the sample can be easily extracted in the process of extracting the sample.

In this embodiment, the extracted sample may include the substrate 100 or may not include the substrate 100, for example, when the layer 120 to be detected is a top insulating layer or a top sacrificial layer, the extracted sample does not include the substrate 100, and when the layer 120 to be detected is a bottom insulating layer or a bottom sacrificial layer, the extracted sample may include the substrate 100. Usually, the distance between the layer to be detected 120 and the substrate 100 is more than 1 μm, the distance between the layer to be detected 120 and the substrate 100 is far, and the extracted sample does not include the substrate 100; when the distance between the layer to be detected 120 and the substrate 100 is within 1 μm, the distance between the layer to be detected 120 and the substrate 100 is short, and the extracted sample includes the substrate 100.

In this embodiment, when the layer to be detected 120 is close to the substrate 100, that is, when the distance between the layer to be detected 120 and the substrate 100 is within 1 μm, since the distance between the layer to be detected 120 and the substrate 100 is close, the extracted sample may include the substrate 100, and the volume and the mass of the sample including the substrate 100 are not too large. The substrate in the sample may then be divided into a first region and a second region, which may be the same or different in area, for example, the area of the first region is smaller than the area of the second region. When the layer 120 to be detected is far from the substrate 100, that is, when the distance between the layer 120 to be detected and the substrate 100 is more than 1 μm, since the distance between the layer 120 to be detected and the substrate 100 is far, if the substrate 100 is included in the extraction process, a plurality of laminated layers between the substrate 100 and the layer 120 to be detected need to be included at the same time, so that the volume and mass of the extracted sample are too large, and the sample cannot be extracted by the extraction needle, therefore, when the distance between the layer 120 to be detected and the substrate 100 is far, the extracted sample does not include the substrate 100.

In a specific application, since diffraction and band adjustment axes cannot be performed when the extracted sample does not include the substrate 100, an additional substrate may be attached to the sample side of the sample that does not include the substrate 100, and the additional substrate is the same as the substrate 100 of the 3D-NAND memory, for example, a silicon substrate. The additional substrate may be a part extracted from the substrate 100 of the 3D-NAND memory, or may be a substrate obtained by other means. Referring to fig. 10, which is a schematic view of a structure for attaching a sample to a test carrier in fig. 10, in particular, an additional substrate may be attached to a side of the sample adjacent to the substrate of the 3D-NAND memory, i.e., below the sample shown in fig. 10.

In step S03, the sample is thinned according to the label to obtain the layer to be detected 120 in the sample.

In the embodiment of the present application, since the extracted sample includes the layer to be detected 120 and the partial laminated layer around the layer to be detected, in order to avoid that the layer to be detected 120 is not affected by the layer to be detected in the process of detecting the layer to be detected 20, before the layer to be detected 120 is detected, the partial laminated layer, which is the non-layer to be detected, around the layer to be detected 120 needs to be removed, so as to obtain the layer to be detected 120 in the sample, as shown in fig. 13 and fig. 14.

In this embodiment, when the extracted sample includes the substrate 100, the substrate 100 is thinned simultaneously in the process of thinning the sample, and only the layer to be detected 120 above the first region of the substrate 100 and the second region of the substrate 100 remains. Specifically, the stacked layer 130 and the layer to be detected 120 above the first region of the substrate 100 may be removed, and the substrate 100 in the first region is retained, while the stacked layer 130 and the layer to be detected 120 above the second region of the substrate 100 are removed, and the layer to be detected 120 above the second region is retained, as shown in fig. 14. The stacked layer 130 and the layer to be detected 120 above the first region, and the stacked layer 130 above the second region and the second region of the substrate 100 may be removed by dry etching, when the stacked layer 130 and the layer to be detected 120 above the first region are removed, a hard mask layer may be formed above the second region, and when the stacked layer 130 and the layer to be detected 120 above the first region are removed, the first hard mask layer protects the layer to be detected 120 and the stacked layer 130 above the second region from being lost. After removing the stacked layer 130 and the layer to be detected 120 above the first region, the stacked layer 130 above the second region and the second region is removed, a second hard mask layer may be formed on the back surface of the first region, i.e., the surface facing away from the stacked layer 130 and the layer to be detected 120, and then the substrate of the second region and the stacked layer 130 above the second region are removed by dry etching, so that only the first region of the substrate 100 and the layer to be detected 120 above the second region of the substrate 100 are remained. When the layer to be detected 120 is located above the substrate 100, the substrate 100 is thinned, and only the substrate in the first region and the layer to be detected above the second region of the substrate 100 may be removed. Subsequently, the second hard mask layer may be removed.

In this embodiment, when the extracted sample does not include the substrate 100, an additional substrate is adhered to the bottom of the sample, specifically, the additional substrate may be first placed on the test carrier, as shown in fig. 11, where fig. 11 is a schematic structural diagram of the test carrier, and then the sample is placed above the additional substrate, as shown in fig. 12, where fig. 12 is a schematic structural diagram of the sample and the additional substrate placed on the test carrier. The additional substrate is thinned while the sample is thinned, and for convenience of description, the additional substrate may be divided into a first additional substrate and a second additional substrate, and the sample and the additional substrate may be thinned simultaneously such that only the layer to be detected 120 above the first additional substrate and the second additional substrate remains. Generally, when the sample is adhered to the additional substrate, a non-to-be-detected layer, that is, other stacked layers, is included between the to-be-detected layer and the additional substrate, in the process of thinning, a third hard mask layer may be formed above the to-be-detected layer 120 and the stacked layer 130 above the second additional substrate, and then the to-be-detected layer 120 and the stacked layer 130 above the first additional substrate are removed, and the first additional substrate is remained. Subsequently, a fourth hard mask layer may be formed on the back side of the first additional substrate, i.e., the side facing away from the stacked layer 130 and the layer to be detected 120, the second additional substrate and the non-detection layer above the second additional substrate are removed, and the layer to be detected 120 above the second additional substrate is exposed, so that only the layer to be detected 120 above the first additional substrate and the second additional substrate remains. In this embodiment, the first additional substrate and the second additional substrate may have the same area or different areas, and the area of the first additional substrate may be smaller than that of the second additional substrate.

In this embodiment, after the layer to be detected 120 is obtained, the layer to be detected 120 may be detected to obtain the feature of the channel hole in the layer to be detected 120 in the sample, as shown in fig. 15, so as to further obtain the size of the channel hole, the thickness of the storage function layer and the channel layer in the channel hole, and the like. The N concentration, O concentration, TiN crystallinity, etc. in the channel hole of the layer 120 to be detected can also be analyzed according to EELS (Electron Energy loss Spectroscopy)/EDX (Energy Dispersive X-Ray Spectroscopy).

In the above detailed description of the sample preparation method provided by the embodiment of the present application, the layer to be detected is marked on the surface of the 3D-NAND memory perpendicular to the substrate direction, then the sample is extracted along the direction perpendicular to the cross section and parallel to the substrate direction, and only the layer to be detected and a small number of stacked layers around the layer to be detected need to be extracted in the process of extracting the sample. The sample is taken from a cross-section, with little volume and mass compared to taking a sample from the surface of a 3D-NAND memory. And when the extracted sample is thinned, only part of other laminated layers around the layer to be detected need to be removed, so that the waste of machine resources is reduced.

The embodiment of this application still provides a sample preparation facilities, includes:

In this embodiment, the sample includes a substrate including a first region and a second region, and the thinning unit is specifically configured to retain only the layer to be detected over the first region of the substrate and the second region of the substrate.

In this embodiment, the apparatus further comprises an adhesion unit for adhering an additional substrate to one side of the sample for diffraction and tuning the band axis. The thinning unit is used for thinning the additional substrate while thinning the sample.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.

The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims

1. A method of sample preparation, comprising:

2. The method of claim 1, wherein the sample comprises the substrate, the substrate comprising a first region and a second region;

said thinning said sample according to said indicia comprises:

3. The method of claim 1, further comprising:

attaching an additional substrate to one side of the sample;

4. The method of claim 3, wherein said adhering an additional substrate to one side of said sample comprises:

5. The method of any one of claims 1-4, further comprising:

6. The method according to any one of claims 1 to 4, wherein marking the layer to be detected on the 3D-NAND memory cross section comprises:

7. The method according to any one of claims 1 to 4, wherein the stacked layers of the 3D-NAND memory comprise a silicon oxide layer and a silicon nitride layer, and the layer to be detected is the silicon oxide layer or the silicon nitride layer;

8. A sample preparation device, comprising:

9. The apparatus of claim 8, wherein the sample comprises the substrate, the substrate comprising a first region and a second region;

10. The apparatus of claim 8, further comprising: