CN111880005B - Loop resistance tester and control method thereof - Google Patents
Loop resistance tester and control method thereof Download PDFInfo
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- CN111880005B CN111880005B CN202010717344.XA CN202010717344A CN111880005B CN 111880005 B CN111880005 B CN 111880005B CN 202010717344 A CN202010717344 A CN 202010717344A CN 111880005 B CN111880005 B CN 111880005B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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- Y02E60/10—Energy storage using batteries
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Abstract
The embodiment of the invention provides a loop resistance tester and a control method thereof, wherein the loop resistance tester comprises: at least one battery, a current limiting resistor, a charging capacitor, a bus capacitor and a semiconductor device group; the semiconductor device group includes: a first semiconductor device, a second semiconductor device, a third semiconductor device, and a fourth semiconductor device; the second semiconductor device and the third semiconductor device are disconnected in the charging stage of the loop resistance tester and are connected in the power supply stage of the loop resistance tester; the first semiconductor device and the fourth semiconductor device are used for conducting the battery, the current limiting resistor and the first capacitor in a charging stage, and stopping a discharging current from flowing from the first end of the charging capacitor to the second end of the charging capacitor in a power supply stage. The technical scheme provided by the embodiment of the invention reduces the output current of the battery, reduces the number of the batteries, reduces the cost, reduces the volume and the weight of the device and simplifies the control of the circuit.
Description
Technical Field
The embodiment of the invention relates to the technical field of power supply circuits, in particular to a loop resistance tester and a control method thereof.
Background
At present, a loop resistance testing instrument mostly adopts a mode of taking electricity from an overhaul power box or a battery-powered circuit.
However, the mode of getting electricity from the maintenance power box needs to adopt a transformer for reducing voltage, and combines a conversion circuit from alternating current to direct current and from direct current to realize the final low-voltage and high-current output function. The circuit that adopts battery power supply type gets the mode of electricity, because battery discharge capacity is limited, need provide a large amount of battery power supplies in order to guarantee output current and output voltage, lead to loop resistance tester cost to increase, device volume and weight increase, although can adopt switch direct current boost circuit to reduce the output current of battery for the electric capacity charges, in order to reduce the use quantity of battery, but need carry out high frequency chopping control to the semiconductor switch who is connected with electric charging capacitor electricity, for guaranteeing that the electric capacity charges to suitable voltage, still need closed-loop control, the operation is complicated.
Disclosure of Invention
The embodiment of the invention provides a loop resistance tester and a control method thereof, which are used for realizing the low-voltage large-current output function, reducing the output current of a battery, reducing the number of batteries, reducing the cost, reducing the volume and the weight of a device and simplifying the control of a circuit.
In a first aspect, an embodiment of the present invention provides a loop resistance tester, including:
at least one battery, a current limiting resistor, a charging capacitor, a bus capacitor and a semiconductor device group;
the semiconductor device group includes: a first semiconductor device, a second semiconductor device, a third semiconductor device, and a fourth semiconductor device; the positive terminal of the battery is electrically connected with the first terminal of the first semiconductor device and the first terminal of the second semiconductor device; the second end of the first semiconductor device is electrically connected with the first end of the current limiting resistor; the second end of the current-limiting resistor is electrically connected with the first end of the charging capacitor and the first end of the third semiconductor device; a second terminal of the third semiconductor device is electrically connected to a first terminal of the fourth semiconductor device; a second terminal of the fourth semiconductor device is electrically connected with a second terminal of the second semiconductor device and a second terminal of the charging capacitor; the second semiconductor device and the third semiconductor device are disconnected in the charging stage of the loop resistance tester and are connected in the power supply stage of the loop resistance tester; the first semiconductor device and the fourth semiconductor device are used for conducting the battery, the current limiting resistor and the charging capacitor in a charging stage, and stopping discharging current from flowing from a first end of the charging capacitor to a second end of the charging capacitor in a power supply stage;
the charging capacitor is used for storing the electric energy output by the battery in the charging stage; the bus capacitor is used for outputting the electric energy stored by the battery and the charging capacitor in the power supply stage so as to reduce the output current of the battery.
Optionally, the first semiconductor device and the fourth semiconductor device include field effect switching tubes and/or diodes, and the second control switch and the third control switch include field effect switching tubes.
Optionally, the semiconductor device group further includes: a fifth semiconductor device and a sixth semiconductor device; a first end of the bus capacitor is electrically connected with a second end of the third semiconductor device, a first end of the fourth semiconductor device and a first end of the fifth semiconductor device, and a second end of the bus capacitor is electrically connected with a negative electrode end of the battery and a second end of the sixth semiconductor device; a second terminal of the fifth semiconductor device and a first terminal of the sixth semiconductor device are electrically connected; the fifth semiconductor device and the sixth semiconductor device may be turned on and off; the semiconductor device group is also used for adjusting the output voltage of the bus capacitor according to the fifth semiconductor device and the sixth semiconductor device.
Optionally, the fifth semiconductor device and the sixth semiconductor device include field effect switching transistors; the fifth semiconductor device and the sixth semiconductor device are turned on in the charging phase, and the fifth semiconductor device and the sixth semiconductor device are turned on at a set duty ratio in the power supply phase to regulate the output voltage of the bus capacitor.
Optionally, the loop resistance tester further includes a filtering unit, and the filtering unit is configured to filter an alternating current signal in the output voltage of the loop resistance tester.
Optionally, the filtering unit includes a second inductor and a third capacitor; the first end of the second inductor is electrically connected with the common end of the fifth semiconductor device and the sixth semiconductor device, the second end of the second inductor is electrically connected with the first end of the third capacitor, and the second end of the third capacitor is electrically connected with the second end of the sixth semiconductor device.
In a second aspect, an embodiment of the present invention provides a method for controlling a loop resistance tester, where the loop resistance tester includes at least one battery, a current-limiting resistor, a charging capacitor, a bus capacitor, and a semiconductor device group; the semiconductor device group includes: a first semiconductor device, a second semiconductor device, a third semiconductor device, and a fourth semiconductor device; the positive terminal of the battery is electrically connected with the first terminal of the first semiconductor device and the first terminal of the second semiconductor device; the second end of the first semiconductor device is electrically connected with the first end of the current limiting resistor; the second end of the current-limiting resistor is electrically connected with the first end of the charging capacitor and the first end of the third semiconductor device; a second terminal of the third semiconductor device is electrically connected to a first terminal of the fourth semiconductor device; a second terminal of the fourth semiconductor device is electrically connected to a second terminal of the second semiconductor device and a second terminal of the charging capacitor, and the control method includes:
turning on the first semiconductor device and the fourth semiconductor device, and turning off the second semiconductor device and the third semiconductor device to turn on a battery pack, the first semiconductor device, a current limiting resistor, a charging capacitor, and the fourth semiconductor device to charge the charging capacitor with the battery pack;
and disconnecting the first semiconductor device and the fourth semiconductor device, and connecting the second semiconductor device and the third semiconductor device to enable the electric energy stored in the battery pack and the charging capacitor to be output through the bus capacitor so as to reduce the output current of the battery pack.
Optionally, the first semiconductor device and the fourth semiconductor device include field effect switching tubes and/or diodes, and the second control switch and the third control switch include field effect switching tubes.
Optionally, the semiconductor device group further includes: a fifth semiconductor device and a sixth semiconductor device; a first end of the bus capacitor is electrically connected with a second end of the third semiconductor device, a first end of the fourth semiconductor device and a first end of the fifth semiconductor device, and a second end of the bus capacitor is electrically connected with a negative electrode end of the battery and a second end of the sixth semiconductor device; a second terminal of the fifth semiconductor device and a first terminal of the sixth semiconductor device are electrically connected; the fifth semiconductor device and the sixth semiconductor device may be turned on and off;
in the charging stage, turning on a fifth semiconductor device and a sixth semiconductor device; and in the power supply phase, complementarily conducting the fifth semiconductor device and the sixth semiconductor device at a set duty ratio.
Optionally, the voltage at which the battery charges the charging capacitor is determined based on:
the output voltage of the bus capacitance is determined based on:
The output current of the battery is determined based on:
The embodiment of the invention provides a loop resistance tester and a control method thereof, wherein the loop resistance tester comprises: at least one battery, a current limiting resistor, a charging capacitor, a bus capacitor and a semiconductor device group;
the semiconductor device group includes: a first semiconductor device, a second semiconductor device, a third semiconductor device, and a fourth semiconductor device; the second semiconductor device and the third semiconductor device are disconnected in the charging stage of the loop resistance tester and are connected in the power supply stage of the loop resistance tester; the first semiconductor device and the fourth semiconductor device are used for conducting the battery, the current limiting resistor and the first capacitor in a charging stage, and stopping a discharging current from flowing from the first end of the charging capacitor to the second end of the charging capacitor in a power supply stage. The technical scheme provided by the embodiment of the invention switches the charging stage and the power supply stage of the loop resistance tester through the conducting states of the first semiconductor device, the second semiconductor device, the third semiconductor device and the fourth semiconductor device; the battery charges the charging capacitor, and the electric energy stored by the battery and the charging capacitor is output through the bus capacitor so as to reduce the output current of the battery, thereby reducing the number of the batteries, reducing the cost, reducing the volume and the weight of the device and simplifying the control of a circuit.
Drawings
Fig. 1 is a block diagram of a loop resistance tester according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a loop resistance tester according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of another loop resistance tester provided in accordance with an embodiment of the present invention;
FIG. 4 is a circuit diagram of another loop resistance tester provided in accordance with an embodiment of the present invention;
FIG. 5 is a circuit diagram of another loop resistance tester provided in accordance with an embodiment of the present invention;
fig. 6 is a flowchart of a control method of a loop resistance tester according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
An embodiment of the present invention provides a loop resistance tester, and fig. 1 is a block diagram of a structure of the loop resistance tester provided in the embodiment of the present invention, and referring to fig. 1, the loop resistance tester includes:
at least one battery B1, a current limiting resistor R1, a charging capacitor C1, a bus capacitor C2 and a semiconductor device group;
the semiconductor device group includes: a first semiconductor device S1, a second semiconductor device S2, a third semiconductor device S3, and a fourth semiconductor device S4; the positive terminal of the battery B1 is electrically connected to the first terminal of the first semiconductor device S1 and the first terminal of the second semiconductor device S2; a second terminal of the first semiconductor device S1 is electrically connected with a first terminal of a current limiting resistor R1; a second end of the current limiting resistor R1 is electrically connected to a first end of the charging capacitor C1 and a first end of the third semiconductor device S3; a second terminal of the third semiconductor device S3 is electrically connected with a first terminal of the fourth semiconductor device S4; a second terminal of the fourth semiconductor device S4 is electrically connected to a second terminal of the second semiconductor device S2 and a second terminal of the charging capacitor C1; the second semiconductor device S2 and the third semiconductor device S3 are disconnected in the charging stage of the loop resistance tester and are connected in the power supply stage of the loop resistance tester; the first semiconductor device S1 and the fourth semiconductor device S4 are used for turning on the battery B1, the current-limiting resistor R1 and the charging capacitor C1 in a charging stage, and turning off a discharging current from a first end of the charging capacitor C1 to a second end of the charging capacitor C2 in a power supply stage;
the charging capacitor C2 is used for storing the electric energy output by the battery in the charging phase; the bus capacitor C2 is used for outputting the stored energy of the battery B1 and the charging capacitor C1 in the power supply stage to reduce the output current of the battery B1.
Specifically, the loop resistance tester includes: at least one battery B1, a current limiting resistor R1, a charging capacitor C1, a bus capacitor C2 and a semiconductor device group. The charging capacitor C1 stores the electric energy output by the battery B1 in the charging stage; the bus capacitor C2 outputs the electric energy stored by the battery B1 and the charging capacitor C1 in the power supply stage to reduce the output current of the battery. The current limiting resistor R1 plays a technical role in protecting the charging capacitor C1 during charging, and the charging capacitor C1 is damaged due to too large current output by the protection battery B1. The semiconductor device group comprises a first semiconductor device S1, a second semiconductor device S2, a third semiconductor device S3 and a fourth semiconductor device S4, wherein the first semiconductor device S1, the second semiconductor device S2, the third semiconductor device S3 and the fourth semiconductor device S4 can be turned on and off, and the charging phase and the power supply phase of the resistance tester are switched back through the on states of the first semiconductor device S1, the second semiconductor device S2, the third semiconductor device S3 and the fourth semiconductor device S4. The second semiconductor device S2 and the third semiconductor device S3 are turned off during the charging phase of the loop resistance tester, and the second semiconductor device S2 and the third semiconductor device S3 are turned on during the powering phase of the loop resistance tester; the battery B1, the current-limiting resistor R1 and the charging capacitor C1 are switched on in the charging phase through the first semiconductor device S1 and the fourth semiconductor device S4; the first semiconductor device S1 and the fourth semiconductor device S4 cut off the discharge current from flowing from the first terminal of the charging capacitor C1 to the second terminal of the charging capacitor C1 during the power supply phase.
The battery can be a polymer lithium battery or a lithium iron phosphate battery, wherein a single polymer lithium battery is generally 3-4.2V, and a single lithium iron phosphate battery is generally 2.5-3.7V. When the loop resistance tester comprises a battery B1, the loop resistance tester is suitable for measuring the situation that the loop resistance is small. It should be noted that the loop resistance tester output current is not equal to the output current of battery B1. The output current of the battery B1 is the current output by the battery B1 when the battery B1 and the charging capacitor C1 transmit electric energy to the bus capacitor C2 together when the loop resistance tester supplies power. The output current of the loop resistance tester is the current output by the bus capacitor C2 in the power supply stage, which is the current output by the whole loop resistance tester. When the battery B1 and the charging capacitor C1 transmit electric energy to the bus capacitor C2 together, and the voltage value at the two ends of the bus capacitor C2 is equal to the voltage value output by the loop resistance tester last time, the current output by the battery B1 is equal to the current output by the loop resistance tester in terms of value at this time. If the voltage value at the two ends of the bus capacitor C2 is output after being regulated, namely the last output voltage value of the loop resistance tester is not equal to the voltage value at the two ends of the bus C2, according to the energy conservation principle,
wherein Ib is the output current of the battery, VC2 is the voltage across the bus capacitor C2, Io is the output current of the loop resistance tester, Io is the output voltage of the loop resistance tester, and it can be seen that the current output by the battery B1 is not equal to the loop resistance testThe current output by the tester. According to the technical scheme provided by the embodiment of the invention, the charging capacitor C1 is charged through the battery B1 in the charging stage, so that the electric energy of the battery B1 and the electric energy of the charging capacitor C1 are transmitted to the bus capacitor C2 in the discharging stage, and the voltage value of the two ends of the bus capacitor C2 is twice that of the battery voltage directly applied to the bus capacitor C2. The output current of the battery is reduced while the low-voltage large-current output function of the loop resistance tester is realized, so that the number of the batteries is reduced, the cost is reduced, and the size and the weight of the device are reduced. In addition, the technical scheme provided by the embodiment of the invention does not need to carry out high-frequency chopping control on the semiconductor device electrically connected with the charging capacitor, thereby avoiding closed-loop control and simplifying the control on the circuit.
Alternatively, fig. 2 is a circuit diagram of a loop resistance tester provided in the first embodiment of the present invention, fig. 3 is a circuit diagram of another loop resistance tester provided in the first embodiment of the present invention, fig. 4 is a circuit diagram of another loop resistance tester provided in the first embodiment of the present invention, fig. 5 is a circuit diagram of another loop resistance tester provided in the first embodiment of the present invention, and refer to fig. 2 to 5; the first semiconductor device S1 and the fourth semiconductor device S4 include field effect switching transistors and/or diodes, and the second control switch S2 and the third control switch S3 include field effect switching transistors.
Specifically, the first semiconductor device S1, the second semiconductor device S2, the third semiconductor device S3, and the fourth semiconductor device S4 may all be field effect switching transistors (refer to fig. 2), and output a control signal to control terminals of the field effect switching transistors corresponding to the first semiconductor device S1, the second semiconductor device S2, the third semiconductor device S3, and the fourth semiconductor device S4, so as to control on/off of the first semiconductor device S1, the second semiconductor device S2, the third semiconductor device S3, and the fourth semiconductor device S4, thereby implementing switching between a charging stage and a power supply stage of the loop resistance tester. The first semiconductor device S1 and the fourth semiconductor device S2 may adopt diodes (refer to fig. 3), and by using the unidirectional conductive performance of the diodes, the battery B1 and the charging capacitor C1 are turned on in the charging stage, so that the battery B1 charges the charging capacitor C1, and the discharging current of the charging capacitor C1 is turned off in the power supply stage, and the discharging current directly flows from the first end of the charging capacitor C1 to the second end of the charging capacitor C1, so that the normal discharging of the charging capacitor C1 is ensured. In addition, the first semiconductor device S1 and the fourth semiconductor device S2 may also be one using a field effect transistor and the other using a diode (refer to fig. 4 and 5), and the operation is the same as above, and will not be described again here.
Optionally, with continuing reference to fig. 2-5, the semiconductor device group further includes: a fifth semiconductor device S5 and a sixth semiconductor device S5; a first end of a bus capacitor C2 is electrically connected with the second end of the third semiconductor device S3, the first end of the fourth semiconductor device S4 and the first end of the fifth semiconductor device S5, and a second end of a bus capacitor C2 is electrically connected with the negative end of the battery B1 and the second end of the sixth semiconductor device S6; a second terminal of the fifth semiconductor device S5 and a first terminal of the sixth semiconductor device S6 are electrically connected; the fifth semiconductor device S5 and the sixth semiconductor device S6 may be turned on or off; the semiconductor device group is also used for adjusting the output voltage of the bus capacitor C2 according to the fifth semiconductor device S5 and the sixth semiconductor device S6.
The fifth semiconductor device S5 and the sixth semiconductor device S6 include field effect switching transistors, and the fifth semiconductor device S5 and the sixth semiconductor device S6 are turned on and off by inputting a control signal to a control terminal of the corresponding field effect switching transistor. The fifth semiconductor device S5 and the sixth semiconductor device S6 are turned on in the charging stage, so that the current flowing out of the positive terminal of the battery B1 sequentially passes through the first semiconductor device S1, the current-limiting resistor R1, the charging capacitor C1, the fourth semiconductor device S4, the fifth semiconductor device S5 and the sixth semiconductor device S6, and returns to the negative terminal of the battery B1 to form a closed loop, thereby realizing the charging of the charging capacitor C1 by the battery B1. In the power supply phase, the fifth semiconductor device S5 and the sixth semiconductor device S6 are turned on at a set duty ratio and operate complementarily at a high frequency, and if the duty ratio of the fifth semiconductor device S5 is D2, the duty ratio of the sixth semiconductor device S6 is (1-D2). The duty ratios of the fifth semiconductor device S5 and the sixth semiconductor device S6 in the power supply stage correspond to the output voltage of the bus capacitor C2, that is, the output voltage of the loop resistance tester at this time is determined based on the formula Vo = (Vb + VC 1) × D2; wherein VC1 is the voltage of charging capacitor C1, and Vb is the voltage of battery B1.
Optionally, the resistance tester further comprises a filtering unit 10, and the filtering unit 10 is configured to filter an alternating current signal in the output voltage of the loop resistance tester.
Specifically, in the power supply stage, the fifth semiconductor device S5 and the sixth semiconductor device S6 complementarily operate at a set duty ratio high frequency. And a filtering unit is arranged on the voltage output side of the loop resistance tester to filter secondary ripples generated when the fifth semiconductor device S5 and the sixth semiconductor device S6 work in a high-frequency complementary mode, and direct-current voltage is output from the loop resistance tester. Optionally, the filtering unit provided in the embodiment of the present invention may be a filtering circuit formed by the second inductor L2 and the third capacitor C3. A first terminal of the second inductor L2 is electrically connected to a common terminal of the fifth semiconductor device S5 and the sixth semiconductor device S6, a second terminal of the second inductor L2 is electrically connected to a first terminal of the third capacitor C3, and a second terminal of the third capacitor C3 is electrically connected to a second terminal of the sixth semiconductor device S6.
The loop resistance tester provided by the embodiment of the invention comprises: at least one battery, a current limiting resistor, a charging capacitor, a bus capacitor and a semiconductor device group; the semiconductor device group includes: a first semiconductor device, a second semiconductor device, a third semiconductor device, and a fourth semiconductor device; the second semiconductor device and the third semiconductor device are disconnected in the charging stage of the loop resistance tester and are connected in the power supply stage of the loop resistance tester; the first semiconductor device and the fourth semiconductor device are used for conducting the battery, the current limiting resistor and the first capacitor in a charging stage, and stopping a discharging current from flowing from the first end of the charging capacitor to the second end of the charging capacitor in a power supply stage. The technical scheme provided by the embodiment of the invention switches the charging stage and the power supply stage of the loop resistance tester through the conducting states of the first semiconductor device, the second semiconductor device, the third semiconductor device and the fourth semiconductor device; the battery charges the charging capacitor, and the electric energy stored by the battery and the charging capacitor is output through the bus capacitor so as to reduce the output current of the battery, thereby reducing the number of the batteries, reducing the cost, reducing the volume and the weight of the device and simplifying the control of a circuit.
Example two
An embodiment of the present invention provides a control method for a loop resistance tester, which may be applied to the loop resistance tester provided in the embodiment of the present invention, taking the loop resistance tester shown in fig. 1 as an example, referring to fig. 1, the loop resistance tester includes at least one battery B1, a current limiting resistor R1, a charging capacitor C1, a bus capacitor C2, and a semiconductor device group; the semiconductor device group includes: a first semiconductor device S1, a second semiconductor device S2, a third semiconductor device S3, and a fourth semiconductor device S4; the positive terminal of the battery B1 is electrically connected to the first terminal of the first semiconductor device S1 and the first terminal of the second semiconductor device S2; a second terminal of the first semiconductor device S1 is electrically connected to a first terminal of a current limiting resistor R1; a second end of the current limiting resistor R1 is electrically connected to a first end of the charging capacitor C1 and a first end of the third semiconductor device S3; a second terminal of the third semiconductor device S3 is electrically connected with a first terminal of the fourth semiconductor device S4; a second terminal of the fourth semiconductor device S4 is electrically connected to a second terminal of the second semiconductor device S2 and a second terminal of the charging capacitor C1; wherein the first semiconductor device, the second semiconductor device, the third semiconductor device and the fourth semiconductor device may be turned on or off; the second semiconductor device S2 and the third semiconductor device S3 are disconnected in the charging stage of the loop resistance tester and are connected in the power supply stage of the loop resistance tester; the first semiconductor device S1 and the fourth semiconductor device S4 are used for turning on the battery B1, the current-limiting resistor R1 and the charging capacitor C1 in a charging phase, and turning off a discharging current from the first end of the charging capacitor C1 to the second end of the charging capacitor C2 in a power supply phase;
fig. 6 is a flowchart of a control method of a loop resistance tester according to a second embodiment of the present invention, and referring to fig. 1 and 6, the control method includes:
and S10, turning on the first semiconductor device and the fourth semiconductor device, and turning off the second semiconductor device and the third semiconductor device to turn on the battery, the first semiconductor device, the current limiting resistor, the charging capacitor and the fourth semiconductor device to enable the battery to charge the charging capacitor.
Specifically, the first semiconductor device S1, the second semiconductor device S2, the third semiconductor device S3, and the fourth semiconductor device S4 may be turned on or off. The second semiconductor device S2 and the third semiconductor device S3 are turned off, and the first semiconductor device S1 and the fourth semiconductor device S4 are turned on, so that the current flowing from the battery B1 passes through the first semiconductor device S1, the current-limiting resistor R1, the charging capacitor C1 and the fourth semiconductor device S4 in sequence, and the battery B1 charges the charging capacitor C1. The current in the circuit is reduced through the current limiting resistor R1, and the phenomenon that the charging capacitor C1 is burnt due to too large current when the battery B1 directly charges the charging capacitor C1 can be avoided.
And S20, disconnecting the first semiconductor device and the fourth semiconductor device, and connecting the second semiconductor device and the third semiconductor device to enable the electric energy stored in the battery and the charging capacitor to be output through the bus capacitor so as to reduce the output current of the battery pack.
Specifically, after the charging capacitor C1 is charged by the battery B1, the second semiconductor device S2 and the third semiconductor device S3 are turned on, wherein the charging time may take several minutes. After the second semiconductor device S2 and the third semiconductor device S3 are turned on, the bus capacitor C2 outputs the electric energy stored in the battery B1 and the charging capacitor C2, and at this time, the first semiconductor device S1 and the fourth semiconductor device S4 are in an off state, so that the discharging current of the charging capacitor C1 during discharging is prevented from flowing from the first end of the charging capacitor C1 to the second end of the charging capacitor C1, and the charging capacitor C1 is prevented from being discharged inefficiently. When battery B1 and charging capacitor C1 are discharged, battery B1 and charging capacitor C1 are connected in series, and therefore, the voltage actually transmitted across bus capacitor C2 is twice the voltage of battery B1. The battery B1 and the charging capacitor C1 are connected in series and provide the total electric energy stored by the battery B1 and the charging capacitor C1 for the bus capacitor C2, so that the voltage at two ends of the bus capacitor C2 can be increased, the output current of the battery is reduced according to the energy conservation principle, the use number of the batteries is reduced, the cost is reduced, and the weight and the volume of the loop resistance tester are reduced.
Optionally, the first semiconductor device S1 and the fourth semiconductor device S2 include field effect switching transistors and/or diodes, and the second semiconductor device S2 and the third semiconductor device S3 include field effect switching transistors.
Alternatively, referring to fig. 2, the semiconductor device group may further include: a fifth semiconductor device S5 and a sixth semiconductor device S6; a first end of the bus capacitor C2 is electrically connected with a second end of the third semiconductor device S3, a first end of the fourth semiconductor device S4 and a first end of the fifth semiconductor device S5, and a second end of the bus capacitor C2 is electrically connected with a negative end of the battery B1 and a second end of the sixth semiconductor device S6; a second terminal of the fifth semiconductor device S5 and a first terminal of the sixth semiconductor device S6 are electrically connected; the fifth semiconductor device S5 and the sixth semiconductor device S6 may be turned on or off;
in the charging stage, the fifth semiconductor device S5 and the sixth semiconductor device S6 are turned on; in the power supply phase, the fifth semiconductor device S5 and the sixth semiconductor device S6 are complementarily turned on at a set duty ratio.
Alternatively, the voltage at which battery B1 charges charging capacitor C1 is determined based on:
the output voltage of the bus capacitor C2 is determined based on:
The output current of battery B1 is determined based on:
For example, assuming that the output voltage of the loop resistance tester is 10V at most and the output current of the loop resistance tester is 100A at most, two polymer lithium batteries are connected in series to form a battery pack (the voltage range is 6V-8.4V), and the voltage VC2 at two ends of the bus capacitor C2 ranges from 12V to 16.8V. The voltage value of the two ends of the bus capacitor C2 is 12V, the duty ratio D2 of the fifth semiconductor device S5 is 1, that is, the fifth semiconductor device S5 is in a state of being always turned on in the power supply stage, and the discharging current of the battery B1 in the discharging stage is Ib =10 × 100/12= 83.3A. Assuming that the battery B1 is directly discharged, the discharging current Ib =10 × 100/6=166.7A, and thus it is known that the battery discharging current can be reduced by at least half by the control loop resistance tester provided by the embodiment of the present invention.
The control method of the loop resistance tester provided by the embodiment of the invention is used for controlling the loop resistance tester in any embodiment. The control method comprises the following steps: disconnecting the second semiconductor device and the third semiconductor device to turn on the battery, the first semiconductor device, the current limiting resistor, the charging capacitor, and the fourth semiconductor device to charge the charging capacitor with the battery pack; and conducting the second semiconductor device and the third semiconductor device to enable the electric energy stored in the battery and the charging capacitor to be output through the bus capacitor so as to reduce the output current of the battery pack.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. A loop resistance tester, comprising:
at least one battery, a current limiting resistor, a charging capacitor, a bus capacitor and a semiconductor device group;
the semiconductor device group includes: a first semiconductor device, a second semiconductor device, a third semiconductor device, and a fourth semiconductor device; the positive terminal of the battery is electrically connected with the first terminal of the first semiconductor device and the first terminal of the second semiconductor device; the second end of the first semiconductor device is electrically connected with the first end of the current limiting resistor; the second end of the current limiting resistor is electrically connected with the first end of the charging capacitor and the first end of the third semiconductor device; a second end of the third semiconductor device is electrically connected with a first end of the fourth semiconductor device; a second terminal of the fourth semiconductor device is electrically connected with a second terminal of the second semiconductor device and a second terminal of the charging capacitor; the second semiconductor device and the third semiconductor device are disconnected in the charging stage of the loop resistance tester and are connected in the power supply stage of the loop resistance tester; the first semiconductor device and the fourth semiconductor device are used for conducting the battery, the current limiting resistor and the charging capacitor in a charging stage and disconnecting the battery, the current limiting resistor and the charging capacitor in a power supply stage so as to stop a discharging current from flowing from a first end of the charging capacitor to a second end of the charging capacitor;
the semiconductor device group further includes: a fifth semiconductor device and a sixth semiconductor device; a first end of the bus capacitor is electrically connected with a second end of the third semiconductor device, a first end of the fourth semiconductor device and a first end of the fifth semiconductor device, and a second end of the bus capacitor is electrically connected with a negative electrode end of the battery and a second end of the sixth semiconductor device; a second terminal of the fifth semiconductor device and a first terminal of the sixth semiconductor device are electrically connected; the fifth semiconductor device and the sixth semiconductor device may be turned on and off; the fifth semiconductor device and the sixth semiconductor device are conducted in the charging stage, and the fifth semiconductor device and the sixth semiconductor device are conducted in the power supply stage at a set duty ratio to regulate the output voltage of the bus capacitor;
the charging capacitor is used for storing the electric energy output by the battery in the charging stage; the bus capacitor is used for outputting the electric energy stored by the battery and the charging capacitor in the power supply stage so as to reduce the output current of the battery.
2. The loop resistance tester of claim 1, wherein the first and fourth semiconductor devices comprise field effect switching transistors and/or diodes, and the second and third semiconductor devices comprise field effect switching transistors.
3. The loop resistance tester of claim 1, wherein the fifth and sixth semiconductor devices comprise field effect switching transistors.
4. The loop resistance tester of claim 1, further comprising a filtering unit for filtering out ac signals in the output voltage of the loop resistance tester.
5. The loop resistance tester of claim 4, wherein the filter unit comprises a second inductor and a third capacitor; the first end of the second inductor is electrically connected with the common end of the fifth semiconductor device and the sixth semiconductor device, the second end of the second inductor is electrically connected with the first end of the third capacitor, and the second end of the third capacitor is electrically connected with the second end of the sixth semiconductor device.
6. A control method of a loop resistance tester comprises at least one battery, a current limiting resistor, a charging capacitor, a bus capacitor and a semiconductor device group; the semiconductor device group includes: a first semiconductor device, a second semiconductor device, a third semiconductor device, and a fourth semiconductor device; the positive terminal of the battery is electrically connected with the first terminal of the first semiconductor device and the first terminal of the second semiconductor device; the second end of the first semiconductor device is electrically connected with the first end of the current limiting resistor; the second end of the current limiting resistor is electrically connected with the first end of the charging capacitor and the first end of the third semiconductor device; a second terminal of the third semiconductor device is electrically connected to a first terminal of the fourth semiconductor device; a second end of the fourth semiconductor device is electrically connected with a second end of the second semiconductor device and a second end of the charging capacitor; the semiconductor device group further includes: a fifth semiconductor device and a sixth semiconductor device; a first end of the bus capacitor is electrically connected with a second end of the third semiconductor device, a first end of the fourth semiconductor device and a first end of the fifth semiconductor device, and a second end of the bus capacitor is electrically connected with a negative electrode end of the battery and a second end of the sixth semiconductor device; a second terminal of the fifth semiconductor device and a first terminal of the sixth semiconductor device are electrically connected; the fifth semiconductor device and the sixth semiconductor device may be turned on and off; the control method is characterized by comprising the following steps:
in a charging stage, the first semiconductor device, the fourth semiconductor device, the fifth semiconductor device and the sixth semiconductor device are turned on, and the second semiconductor device and the third semiconductor device are turned off to turn on a battery, the first semiconductor device, the current limiting resistor, a charging capacitor and the fourth semiconductor device so that the battery charges the charging capacitor;
in the power supply stage, the first semiconductor device and the fourth semiconductor device are disconnected, the second semiconductor device and the third semiconductor device are conducted, and the fifth semiconductor device and the sixth semiconductor device are conducted complementarily at a set duty ratio, so that the electric energy stored in the battery and the charging capacitor is output through the bus capacitor to reduce the output current of the battery.
7. The method of claim 6, wherein the first and fourth semiconductor devices comprise field effect transistors and/or diodes, and the second and third semiconductor devices comprise field effect transistors.
8. The method of claim 6, wherein the voltage at which the battery charges the charging capacitor is determined based on:
VC1= Vb; wherein VC1 is the voltage of the charging capacitor, Vb is the battery voltage;
the output voltage of the bus capacitance is determined based on:
vo = (Vb + VC 1) × D2; wherein Vo is an output voltage of the loop resistance tester, and D2 is a duty cycle of the fifth semiconductor device;
the output current of the battery is determined based on:
ib = Io Vo/(Vb + VC 1); wherein, Ib is the output current of the battery, and Io is the output current of the loop resistance tester.
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