CN1118752C - Method for simulating ISA bus by VXI digital I/O module - Google Patents
Method for simulating ISA bus by VXI digital I/O module Download PDFInfo
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Abstract
The present invention discloses a method for simulating ISA bus by VXI digital I/O modules. First, each input/output signal of each VXI digital I/O module is endowed with each signal significance defined in an ISA bus pin, and then operations in ISA bus periods are realized through the operation function of a VXI bus. Because the present invention uses a VXI bus test platform, the standardization of system hardware and software is realized. Moreover, the VXI bus test platform is a really open structure system, the present invention has the advantages of high system interoperability and flexibility and easy integration and application.
Description
Technical field
The present invention relates to VXI (VMEbus is at the expansion VMEbuseXtensions of instrument field for Instrumentation) bus and ISA (industrial standard architectures Industry StandardArchitecture) bus in the field tests, more specifically to using digital I/O (I/O) the module simulation isa bus in the vxi bus test platform, the method for test I SA integrated circuit board.VXI, isa bus all are a kind of industrial standard architecture bus.
Background technology
In existing testing apparatus, test I SA integrated circuit board generally is to be inserted on the ISA slot of computing machine to test, its shortcoming is if there is other interface to exist on the ISA integrated circuit board, for example E1 interface (digital interface), audio interface or the like, so also need other instruments or test board pumping signal to be provided and to receive response signal to integrated circuit board, the test macro software and hardware standardization level of building like this is low, function singleness, versatility, reliability and maintainability are poor, the potentiality of transforming in design are little, can not adapt to the frequent upgrading of ISA integrated circuit board version.
Vxi bus is open, the module instrument bus standard that produces and rise the late nineteen eighties.The core of vxi bus test platform has solved the standardization of vxi bus system hardware and software, thereby has improved the interoperability of system, makes it to be easier to integrated and application.It has computing machine, intelligence instrument, personal instrument, GPIB (General Purpose Interface Bus, a kind of digital interface standard of international programmable instrument) system, advantage such as the system integration is convenient, data throughput is high, compatibility is strong, extensibility is good are acknowledged as 21 century instrument bus system and the outstanding platform of Auto-Test System.
Summary of the invention
The object of the present invention is to provide a kind of method with vxi bus numeral input and output I/O module simulation isa bus test I SA card.
For achieving the above object, the method for VXI numeral I/O module simulation isa bus of the present invention may further comprise the steps:
(1) with each signal of the corresponding isa bus definition of each passage of VXI numeral I/O module: 16 BDB Bi-directional Data Bus of the corresponding isa bus of 16 tunnel I/O passages of VXI numeral I/O module, 16 bit address buses of the corresponding isa bus of 16 tunnel output channels, the control bus of the corresponding isa bus of all the other 13 tunnel output channels and 2 tunnel input channels, wherein 2 tunnel input channels respectively the I/O port of corresponding isa bus be ready to signal and interrupt input signal, 5 tunnel output channels are the I/O port reads signal of corresponding isa bus respectively, I/O port write signal, the memory read signal, memory write signals and address latch signal remain corresponding other control signals of isa bus of 8 tunnel output channels; Each passage is controlled by the configuration register of one group of 64 byte that is comprised in the VXI numeral I/O module respectively, and corresponding position is 1 o'clock, and passage is a high level, and corresponding position is 0 o'clock, and passage is a low level;
(2) by the driving function of vxi bus vxi bus is controlled, realized operation the isa bus cycle.
The signal content of isa bus described in the step (1) definition comprises: digital output signal CH1～CH8, CH33～CH40 are respectively D0～D7 control of 16 by the D0～D7 of offset address 8 and offset address; Corresponding position is 1 o'clock, and passage is a high level; Corresponding position is 0 o'clock, and passage is a low level; Digital input signals CH1～CH8, CH33～CH40 are that D0～D7 of 16 links to each other with the D0～D7 of offset address 8 and offset address respectively; By the D0～D15 control of offset address 10, by the D0～D7 control of offset address 12, TSOUT1～TSOUT5 is controlled by the D0～D7 of offset address 14 respectively CH25～CH32 CH9～CH24 respectively respectively; Digital input signals TSINP1, TSINP2 link to each other with the D0～D1 of offset address 10 respectively; TSOUT1～TSOUT5 difference Simulation with I SA bus /IOR ,/IOW ,/SMEMR ,/SMEMW, ALE, TSINP1 Simulation with I/ORDY, input signal is interrupted in the TSINP2 simulation;
Realize described in the step (2) that the method for bus cycles is included in the method for operating of I/O port reads cycle, I/O port write cycle, memory read cycle, memory write cycle;
Described method of operating in the I/O port reads cycle may further comprise the steps:
1. make earlier/inefficacy of OE enable signal, it is changed to high level;
2. write the I/O port address;
3. make ale signal TSOUT5 effective, it is changed to low level;
4. make I/O port reads control line TSOUT1 effective, it is changed to low level;
5. reading of data;
I/O port reads control line TSOUT1 was lost efficacy, it is changed to high level;
7. make ale signal TSOUT5 invalid, it is changed to high level;
Described method of operating in the I/O port write cycle may further comprise the steps:
1. make earlier/inefficacy of OE enable signal, it is changed to high level;
2. write the I/O port address;
3. make ale signal TSOUT5 effective, it is changed to low level;
4. write data;
5. make I/O port write control line TSOUT2 effective, it is changed to low level;
I/O port write control line TSOUT2 was lost efficacy, it is changed to high level;
7. make ale signal TSOUT5 invalid, it is changed to high level;
Described method of operating in memory read cycle may further comprise the steps:
1. make earlier/inefficacy of OE enable signal, it is changed to high level;
2. the least-significant byte of write store address;
3. the most-significant byte of write store address;
4. make memory read control line TSOUT3 effective, it is changed to low level;
5. reading of data;
Memory read control line TSOUT3 was lost efficacy, it is changed to high level;
Described method of operating at memory write cycle may further comprise the steps:
1. make earlier/inefficacy of OE enable signal, it is changed to high level;
2. the least-significant byte of write store address;
3. the most-significant byte of write store address;
4. write data;
5. make memory write control line TSOUT4 effective, it is changed to low level;
Memory write control line TSOUT4 was lost efficacy, it is changed to high level.
Because the present invention has used the vxi bus test platform, has solved the standardization issue of system hardware and software, and at hardware aspect, the vxi bus test macro is real open structural system, improved the interoperability of system, increased dirigibility greatly, made it to be easier to integrated and application.
Below in conjunction with accompanying drawing and specific embodiment the present invention is done further detailed description.
Fig. 1 is the schematic block circuit diagram of VXI numeral I/O module.
Embodiment
Vxi bus numeral I/O module just is based on a kind of general module of vxi bus, in the method for Simulation with I SA bus, the meaning of giving each signal wire that defines in the isa bus at first with each input/output signal of this VXI numeral I/O module, by handling function, can realize operation then to isa bus to vxi bus.
One, VXI numeral I/O module hardware explanation
VXI numeral I/O module in the present embodiment is the VXI numeral input/output module of C size, register base, single groove, static configuration, A16/D16 addressing mode.Module has 16 tunnel I/O channel C H1～CH8, CH33～CH40,29 tunnel output channel CH9～CH32, TSOUT1～TSOUT5,2 road input signal TSINP1～TSINP2.Each input/output signal level is Transistor-Transistor Logic level (Transistor-Transistor-Logic, triode-triode logical circuit).Numeral I/O module is used for simulating the read-write cycle of PC isa bus, comprises memory read cycle, memory write cycle, I/O port reads cycle and I/O port write cycle.When resetting, bus is isolated, and each road I/O is in high-impedance state.The schematic block circuit diagram of VXI numeral I/O module as shown in Figure 1.
VXI numeral I/O module is made up of 4 parts such as bus driving circuits 106, VXI interface circuit 103/104/105, output latch circuit 102, I/O channel separation circuit 101.Wherein the VXI interface circuit is relatively reached 3 parts such as address latch decoding scheme 103 and ID (device identification Identification), DT (type of device Device Type), SR (state Status), CR (control Control) register circuit 104 and forms by logical address initialization circuit 105, logical address.
Bus driving circuits 106 finish the VXI data bus (bi-directional drive of D0～D15), address bus (A1～A15), address modification sign indicating number (AM0～AM5), control signal (/AS ,/DS0 ,/DS1 ,/WRITE ,/LWORD ,/DTACK ,/ACFAIL ,/SYSFAIL), reset signal (/SYSRESET), clock signal (SYSCLK), look-at-me (/IACK ,/IACKIN ,/IACKOUT), the unidirectional drive of module identification signal (MODID) etc.Mainly finish by chip 74HC245.
Logical address initialization circuit 105 is by realizations such as 8 waver S1, resistor chains.Logical address is 8 bits, and address realm is 0～255.The 1st of waver is the lowest order of logical address, and the 8th of waver is the most significant digit of logical address.When waver placed ON, corresponding logical address bit was 0.When waver placed 1, corresponding logical address bit was 1.In the VXI system, logical address 0 keeps for Zero greeve controller.Logical address is 255 o'clock, represents this module support dynamic logic address configuration, is promptly determined the logical address of this module according to the logical address situation of module in the cabinet by Zero greeve controller.The MXI-2 Zero greeve controller also takies logical address 1.This module is not supported dynamic-configuration.Therefore, the logical address of this module can not be set at 0,1 and 255.
Address latch and decoding scheme 103 comprise the decoding, data answering circuit etc. of comparison, address latch, base address and offset address of selection, the address modification sign indicating number of addressing mode (A16/D16), bus timing, are mainly finished by the EPLD programmable logic device (PLD).Address width in the vxi bus system optional 16 (A16), 24 (A24), 32 3 kinds of modes such as (A32).This module is selected the A16 mode for use.Vxi bus data width optional 8 (D08), 16 (D16), 32 several modes such as (D32).This module is selected the D16 mode for use.
What output latch circuit 102 adopted is the user definition register of vxi bus regulation, is made up of 5 16 bit locations such as offset addresss 8,10,12,14,16.Mainly realize by chip 74HC273.Vxi bus has distributed 64 bytes of memory unit for each logical address.For the register base device, 0,1 input block is the ID register.02,03 input block is the DT register.04,05 input block is the SR register, and output unit is the CR register.Unit 06～63 is the operable I/O register of user.
I/O channel separation circuit 101 is finished by chip 74HC245, and Board Under Test UUT and digital I/O module are effectively isolated, and can play the effect of the digital I/O module that adequately protects.
Two, interface specification
1, the setting of logical address
The logical address of this module is set by 8 waver S1,1～8 difference corresponding address signal A6～A13 of S1.When waver placed ON, corresponding address was 0, and when waver placed OFF, corresponding address was 1.The address that waver is set is base address (BASE).The A14 and the A15 of base address are 1.The base address of device is:
BASE＝LOGICAL_ADDRESS*64+49152
Wherein, LOGICAL_ADDRESS represents the logical address of device.
2, the setting of ID, DT, SR, CR register value
(1) ID register
ID is a device identification input register, and offset address is 0.The content of this register is manufacturer's identification code.The value of this module I D register is by waver S2 and S3 decision.S2 is a least-significant byte, S3 position most-significant byte.For digital I/O module, its value is that 16 systems are counted 0X0900H.
(2) DT register
DT is the type of device input register, and offset address is 2.The value of DT register is by waver S4 and S5 decision.S4 is a least-significant byte, S5 position most-significant byte.This module settings DT is that 16 systems are counted 0X8001H.
(3) SR register
SR is the device state input register, and offset address is 4.The value of SR register is by waver S6 and S7 decision.S6 is a least-significant byte, and S7 is a most-significant byte.The D14 of SR is by pattern-recognition signal/MODID decision.This module settings is that 2 systems are counted 0X00000000001100.Wherein, X is by/MODID decision.
(4) CR register
CR is the control output register, and offset address is 4.The D0 of this register is the software reset, and D1 is SYSFAILINHIBIT.Other position can be defined by the user.This module is only used the D0 software reset.This position writes at 1 o'clock, and this module is in reset mode.
3, the control of I/O passage
This section meaning that content gives each signal wire that defines in the isa bus promptly for each input/output signal of VXI numeral I/O module.
In the present embodiment, channel C H1～CH8, CH33～CH40 are used for 16 bit data bus of Simulation with I SA bus, channel C H9～CH24 is used for 16 bit address buses of Simulation with I SA bus, channel C H25～CH32, TSOUT1～5, TSINP1～2 are used for the control bus of Simulation with I SA bus.Digital output signal CH1～CH8, CH33～CH40 are respectively D0～D7 control of 16 by the D0～D7 of offset address 8 and offset address.Corresponding position is 1 o'clock, and passage is a high level.Corresponding position is 0 o'clock, and passage is low level (state of other passage is identical therewith).Digital input signals CH1～CH8, CH33～CH40 are that D0～D7 of 16 links to each other with the D0～D7 of offset address 8 and offset address respectively.By the D0～D15 control of offset address 10, by the D0～D7 control of offset address 12, TSOUT1～TSOUT5 is controlled by the D0～D7 of offset address 14 respectively CH25～CH32 CH9～CH24 respectively respectively.Digital input signals TSINP1, TSINP2 link to each other with the D0～D1 of offset address 10 respectively.TSOUT1～TSOUT5 is I/O port reads/IOR, I/O port write/IOW, memory read/SMEMR, memory write/SMEMW, the address latch ALE of Simulation with I SA bus respectively.TSINP1 Simulation with I/O is ready to I/ORDY, and input signal is interrupted in the TSINP2 simulation.
After giving meaning to each input/output signal of VXI numeral I/O module, by handling function, realize operation again to isa bus to vxi bus.Below the 4th part introduce the basic driver function earlier.
4, basic driving function
High-level functions VXIoutReg (), VXIinReg () in the VXI built-in function of employing Logical_Addressbwindows/CVI can realize the control to this module.
Prototype to function is described as follows:
NIVXI_STATUS?VXIoutReg(INT16?Logical_Address，UINT16?Register，UINT16?Value)
This function is that an individual character is write on the appointment VXI register offset address of VXI device of appointment.The logical address of the device of appointment is Logical_Address, and offset address is Register, and the oneword value that writes is Value.
NIVXI_STATUSVXIinReg(INT16Logical_Address，UINT16Register，UINT16*Value)；
This function reads an individual character from the appointment VXI register offset address of the VXI device of an appointment.The logical address of the device of appointment is Logical_Address, and offset address is Register, and the oneword value of reading is Value.
The logical address of supposing this module is 8, and passage 4 is changed to high level, and other passage is a low level, and the driving function that calls is as follows:
Logical_Address＝8；Register＝8；Value＝8；
/ * Logical_Address represents the logical address of digital I/O module, and the offset address of passage 4 corresponding registers is 8, data value be 8*/
VXIoutReg(Logical_Address，Register，Value)；
The logical address of supposing this module is 8, thinks the state of fetch channel 4, and the driver that calls is as follows:
Logical_Address＝8；Register＝8；Value；
/ * Logical_Address represents the logical address of digital I/O module, passage 4 corresponding register offset addresss be 8*/
VXIinReg(Logical_Address，Register，&Value)；
The value of the D3 position of the binary value (D7D6D5D4D3D2D1D0) by Value can know that passage 4 is low level or high level.
5, realize the isa bus reading/writing method
By above-mentioned driving function to vxi bus, the present invention can realize the operation to isa bus, and the step of specific implementation I/O port reads cycle, I/O port write cycle, memory read cycle and memory write cycle is as follows:
(1) the I/O port reads cycle
1. make earlier/inefficacy of OE enable signal, it is changed to high level, function setup is: and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
2. write the I/O port address, function setup is: and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=I/O port address;
3. make ale signal TSOUT5 effective, it is changed to low level, function setup is: and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
4. make I/O port reads control line TSOUT1 (/IOR) effective, it is changed to low level, function setup is: VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
5. reading of data, function setup is: VXIinReg (Logical_Address, Register ， ﹠amp; Value), Register=register decoding offset address;
I/O port reads control line TSOUT1 was lost efficacy, it is changed to high level, function setup is: and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
7. make ale signal TSOUT5 invalid, it is changed to high level, function setup is: and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
(2) the I/O port write cycle
1. make earlier/inefficacy of OE enable signal, it is changed to high level, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
2. write the I/O port address, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=IO port address;
3. make ale signal TSOUT5 effective, it is changed to low level, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
4. write data, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, the data that Value=need write;
5. make I/O port write control line TSOUT2 (/IOW) effective, it is changed to low level, VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
I/O port write control line TSOUT2 was lost efficacy, it is changed to high level, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
7. make ale signal TSOUT5 invalid, it is changed to high level, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
(3) memory read cycle
1. make earlier/inefficacy of OE enable signal, it is changed to high level, and VXIoutReg (Logical_Address, Register, Value), and Register=register decoding offset address, Value=controls number;
2. the least-significant byte of write store address, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=storer least-significant byte address;
3. the most-significant byte of write store address, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=storer most-significant byte address;
4. make memory read control line TSOUT3 (/SMEMR) effective, it is changed to low level, VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
5. reading of data, VXIinReg (Logical_Address, Register ， ﹠amp; Value), Register=8;
Memory read control line TSOUT3 was lost efficacy, it is changed to high level, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
(4) memory write cycle
1. make earlier/inefficacy of OE enable signal, it is changed to high level, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
2. the least-significant byte of write store address, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=storage address least-significant byte;
3. the most-significant byte of write store address, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=storage address most-significant byte;
4. write data, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, the data that Value=need write;
5. make memory write control line TSOUT4 (/SMEMW) effective, it is changed to low level, VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data;
Memory write control line TSOUT4 was lost efficacy, it is changed to high level, and VXIoutReg (Logical_Address, Register, Value), Register=register decoding offset address, Value=control data.
Claims (2)
1, a kind of method of VXI numeral I/O module simulation isa bus may further comprise the steps:
(1) with each signal of the corresponding isa bus definition of each passage of VXI numeral I/O module: 16 BDB Bi-directional Data Bus of the corresponding isa bus of 16 tunnel I/O passages of VXI numeral I/O module, 16 bit address buses of the corresponding isa bus of 16 tunnel output channels, the control bus of the corresponding isa bus of all the other 13 tunnel output channels and 2 tunnel input channels, wherein 2 tunnel input channels respectively the I/O port of corresponding isa bus be ready to signal and interrupt input signal, 5 tunnel output channels are the I/O port reads signal of corresponding isa bus respectively, I/O port write signal, the memory read signal, memory write signals and address latch signal remain corresponding other control signals of isa bus of 8 tunnel output channels; Each passage is controlled by the configuration register of one group of 64 byte that is comprised in the VXI numeral I/O module respectively, and corresponding position is 1 o'clock, and passage is a high level, and corresponding position is 0 o'clock, and passage is a low level;
(2) by the driving function of vxi bus vxi bus is controlled, realized operation the isa bus cycle.
2, the method for VXI numeral I/O module simulation isa bus as claimed in claim 1 is characterized in that:
The signal content of isa bus described in the step (1) definition comprises: digital output signal CH1～CH8, CH33～CH40 are respectively D0～D7 control of 16 by the D0～D7 of offset address 8 and offset address; Corresponding position is 1 o'clock, and passage is a high level; Corresponding position is 0 o'clock, and passage is a low level; Digital input signals CH1～CH8, CH33～CH40 are that D0～D7 of 16 links to each other with the D0～D7 of offset address 8 and offset address respectively; By the D0～D15 control of offset address 10, by the D0～D7 control of offset address 12, TSOUT1～TSOUT5 is controlled by the D0～D7 of offset address 14 respectively CH25～CH32 CH9～CH24 respectively respectively; Digital input signals TSINP1, TSINP2 link to each other with the D0～D1 of offset address 10 respectively; TSOUT1～TSOUT5 difference Simulation with I SA bus /IOR ,/IOW ,/SMEMR ,/SMEMW, ALE, TSINP1 Simulation with I/ORDY, input signal is interrupted in the TSINP2 simulation;
Realize described in the step (2) that the method for bus cycles is included in the method for operating of I/O port reads cycle, I/O port write cycle, memory read cycle, memory write cycle;
Described method of operating in the I/O port reads cycle may further comprise the steps:
1. make earlier/inefficacy of OE enable signal, it is changed to high level;
2. write the I/O port address;
3. make ale signal TSOUT5 effective, it is changed to low level;
4. make I/O port reads control line TSOUT1 effective, it is changed to low level;
5. reading of data;
I/O port reads control line TSOUT1 was lost efficacy, it is changed to high level;
7. make ale signal TSOUT5 invalid, it is changed to high level;
Described method of operating in the I/O port write cycle may further comprise the steps:
1. make earlier/inefficacy of OE enable signal, it is changed to high level;
2. write the I/O port address;
3. make ale signal TSOUT5 effective, it is changed to low level;
4. write data;
5. make I/O port write control line TSOUT2 effective, it is changed to low level;
I/O port write control line TSOUT2 was lost efficacy, it is changed to high level;
7. make ale signal TSOUT5 invalid, it is changed to high level;
Described method of operating in memory read cycle may further comprise the steps:
1. make earlier/inefficacy of OE enable signal, it is changed to high level;
2. the least-significant byte of write store address;
3. the most-significant byte of write store address;
4. make memory read control line TSOUT3 effective, it is changed to low level;
5. reading of data;
Memory read control line TSOUT3 was lost efficacy, it is changed to high level;
Described method of operating at memory write cycle may further comprise the steps:
1. make earlier/inefficacy of OE enable signal, it is changed to high level;
2. the least-significant byte of write store address;
3. the most-significant byte of write store address;
4. write data;
5. make memory write control line TSOUT4 effective, it is changed to low level;
Memory write control line TSOUT4 was lost efficacy, it is changed to high level.
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| CN 00114216 CN1118752C (en) | 2000-04-20 | 2000-04-20 | Method for simulating ISA bus by VXI digital I/O module |
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| CN 00114216 CN1118752C (en) | 2000-04-20 | 2000-04-20 | Method for simulating ISA bus by VXI digital I/O module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102364908A (en) * | 2011-10-21 | 2012-02-29 | 深圳航天东方红海特卫星有限公司 | Information transmission system and method based on satellite-borne electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100346329C (en) * | 2005-04-30 | 2007-10-31 | 哈尔滨工业大学 | Zero greeve controller with universal series bus interface |
| CN100369025C (en) * | 2005-05-13 | 2008-02-13 | 武汉大学 | VXI bus register base interface and implement method thereof |
| CN101635696B (en) * | 2009-08-21 | 2012-11-14 | 中国电子科技集团公司第四十一研究所 | VXI bus C-size double-groove width I/Q vector signal generation device |
| CN101866312A (en) * | 2010-06-18 | 2010-10-20 | 北京北大众志微***科技有限责任公司 | System and method for detecting hardware failure based on dynamic I/O value invariance |
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| CN102364908A (en) * | 2011-10-21 | 2012-02-29 | 深圳航天东方红海特卫星有限公司 | Information transmission system and method based on satellite-borne electronic equipment |
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